Merge "ARM: dts: msm: Add CRM device for camera and PCIe for sun"

bindings/soc/qcom/qcom,crm.yaml

@@ -19,22 +19,31 @@ properties:
       - items:
           - const: cam_crm
           - const: pcie_crm
+          - const: disp_crm
       - description: Specifies the name of the CRM.
 
   compatible:
     enum:
       - qcom,cam-crm
       - qcom,pcie-crm
+      - qcom,cam-crm-v2
+      - qcom,pcie-crm-v2
+      - qcom,disp-crm-v2
 
   reg:
-    maxItems: 1
+    maxItems: 4
     items:
-      - description: Should specify the base address for the CRM device.
+      - description:
+        Should specify the addresses for the CRM device which includes
+        the base, common, crm_c and crm_b address.
 
   reg-names:
-    maxItems: 1
+    maxItems: 4
     items:
       - const: base
+      - const: common
+      - const: crm_b
+      - const: crm_c
 
   interrupts:
     maxItems: 1
@@ -47,6 +56,7 @@ properties:
       - items:
           - const: cam_crm
           - const: pcie_crm
+          - const: disp_crm
 
   qcom,hw-drv-ids:
     description: List of HW DRV IDs.

qcom/sun.dtsi

@@ -959,6 +959,30 @@
 		};
 	};
 
+	cam_crm: crm@adcb000 {
+		label = "cam_crm";
+		compatible = "qcom,cam-crm-v2";
+		reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd600 0x2000>, <0xadcfd00 0x100>;
+		reg-names = "base", "crm_b", "crm_c", "common";
+		interrupts = <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "cam_crm_drv0";
+		clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
+		qcom,hw-drv-ids = <0 1 2>;
+		qcom,sw-drv-ids = <0>;
+	};
+
+	pcie_crm: crm@1d01000 {
+		label = "pcie_crm";
+		compatible = "qcom,pcie-crm-v2";
+		reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03800 0x2000>, <0x1d05f00 0x100>;
+		reg-names = "base", "crm_b", "crm_c", "common";
+		interrupts = <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "pcie_crm_drv0";
+		clocks = <&pcie_0_pipe_clk>;
+		qcom,hw-drv-ids = <0 1>;
+		qcom,sw-drv-ids = <0>;
+	};
+
 	cluster-device0 {
 		compatible = "qcom,lpm-cluster-dev";
 		power-domains = <&CLUSTER_PD0>;