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ARM: dts: msm: Add dtsi entry to configure cpu mask

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Add dtsi entry to configure cpu mask for wlan rx and tx completion
interrupt affinity.

Change-Id: I3930e401df2e37818405accadb8d5449bc16b5b7
CRs-Fixed: 3837616
This commit is contained in:
Venkateswara Naralasetty
2024-06-10 14:47:17 +05:30
parent 8ef99d091e
commit bfb14148a8
5 changed files with 23 additions and 0 deletions
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3
bindings/cnss-wlan.yaml
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@@ -211,6 +211,9 @@ properties:
qcom,bus-bw-cfg: qcom,bus-bw-cfg:
description: Bus bandwidth voting data. description: Bus bandwidth voting data.
wlan-txrx-intr-cpumask:
description: cpumask for wlan tx rx interrupt affinity
qcom,tcs_offset_int_pow_amp_vreg: qcom,tcs_offset_int_pow_amp_vreg:
description: | description: |
TCS CMD register offset for Voltage TCS CMD register offset for Voltage

5
sun-kiwi-cnss-v8.dtsi
View File

@@ -187,6 +187,11 @@
"{class: wlan_pdc, ss: bb, res: s5f.v, enable: 1}", "{class: wlan_pdc, ss: bb, res: s5f.v, enable: 1}",
"{class: wlan_pdc, ss: bb, res: s5f.v, upval: 932}", "{class: wlan_pdc, ss: bb, res: s5f.v, upval: 932}",
"{class: wlan_pdc, ss: bb, res: s5f.v, dwnval: 444}"; "{class: wlan_pdc, ss: bb, res: s5f.v, dwnval: 444}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
}; };
}; };

5
sun-kiwi-cnss.dtsi
View File

@@ -189,6 +189,11 @@
"{class: wlan_pdc, ss: bb, res: s4j.v, enable: 1}", "{class: wlan_pdc, ss: bb, res: s4j.v, enable: 1}",
"{class: wlan_pdc, ss: bb, res: s4j.v, upval: 932}", "{class: wlan_pdc, ss: bb, res: s4j.v, upval: 932}",
"{class: wlan_pdc, ss: bb, res: s4j.v, dwnval: 444}"; "{class: wlan_pdc, ss: bb, res: s4j.v, dwnval: 444}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
}; };
}; };

5
sun-peach-cnss-v8.dtsi
View File

@@ -193,6 +193,11 @@
"{class: wlan_pdc, ss: rf, res: s5f.v, enable: 1}", "{class: wlan_pdc, ss: rf, res: s5f.v, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s5f.v, upval: 876}", "{class: wlan_pdc, ss: rf, res: s5f.v, upval: 876}",
"{class: wlan_pdc, ss: rf, res: s5f.v, dwnval: 876}"; "{class: wlan_pdc, ss: rf, res: s5f.v, dwnval: 876}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
}; };
}; };

5
sun-peach-cnss.dtsi
View File

@@ -192,6 +192,11 @@
"{class: wlan_pdc, ss: rf, res: s4j.v, enable: 1}", "{class: wlan_pdc, ss: rf, res: s4j.v, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s4j.v, upval: 876}", "{class: wlan_pdc, ss: rf, res: s4j.v, upval: 876}",
"{class: wlan_pdc, ss: rf, res: s4j.v, dwnval: 876}"; "{class: wlan_pdc, ss: rf, res: s4j.v, dwnval: 876}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
}; };
}; };