From bfb14148a81947a8e1363d65bee3aeecae0de3a8 Mon Sep 17 00:00:00 2001 From: Venkateswara Naralasetty Date: Mon, 10 Jun 2024 14:47:17 +0530 Subject: [PATCH] ARM: dts: msm: Add dtsi entry to configure cpu mask Add dtsi entry to configure cpu mask for wlan rx and tx completion interrupt affinity. Change-Id: I3930e401df2e37818405accadb8d5449bc16b5b7 CRs-Fixed: 3837616 --- bindings/cnss-wlan.yaml | 3 +++ sun-kiwi-cnss-v8.dtsi | 5 +++++ sun-kiwi-cnss.dtsi | 5 +++++ sun-peach-cnss-v8.dtsi | 5 +++++ sun-peach-cnss.dtsi | 5 +++++ 5 files changed, 23 insertions(+) diff --git a/bindings/cnss-wlan.yaml b/bindings/cnss-wlan.yaml index e2ef1e30..20a9b7cb 100644 --- a/bindings/cnss-wlan.yaml +++ b/bindings/cnss-wlan.yaml @@ -211,6 +211,9 @@ properties: qcom,bus-bw-cfg: description: Bus bandwidth voting data. + wlan-txrx-intr-cpumask: + description: cpumask for wlan tx rx interrupt affinity + qcom,tcs_offset_int_pow_amp_vreg: description: | TCS CMD register offset for Voltage diff --git a/sun-kiwi-cnss-v8.dtsi b/sun-kiwi-cnss-v8.dtsi index bd28a0cd..8c8fce19 100644 --- a/sun-kiwi-cnss-v8.dtsi +++ b/sun-kiwi-cnss-v8.dtsi @@ -187,6 +187,11 @@ "{class: wlan_pdc, ss: bb, res: s5f.v, enable: 1}", "{class: wlan_pdc, ss: bb, res: s5f.v, upval: 932}", "{class: wlan_pdc, ss: bb, res: s5f.v, dwnval: 444}"; + + /* cpu mask used for wlan tx rx interrupt affinity + * + */ + wlan-txrx-intr-cpumask = <0x3 0x30>; }; }; diff --git a/sun-kiwi-cnss.dtsi b/sun-kiwi-cnss.dtsi index 185769f5..85dc7b1e 100644 --- a/sun-kiwi-cnss.dtsi +++ b/sun-kiwi-cnss.dtsi @@ -189,6 +189,11 @@ "{class: wlan_pdc, ss: bb, res: s4j.v, enable: 1}", "{class: wlan_pdc, ss: bb, res: s4j.v, upval: 932}", "{class: wlan_pdc, ss: bb, res: s4j.v, dwnval: 444}"; + + /* cpu mask used for wlan tx rx interrupt affinity + * + */ + wlan-txrx-intr-cpumask = <0x3 0x30>; }; }; diff --git a/sun-peach-cnss-v8.dtsi b/sun-peach-cnss-v8.dtsi index c51b6b36..3e2b6ac8 100644 --- a/sun-peach-cnss-v8.dtsi +++ b/sun-peach-cnss-v8.dtsi @@ -193,6 +193,11 @@ "{class: wlan_pdc, ss: rf, res: s5f.v, enable: 1}", "{class: wlan_pdc, ss: rf, res: s5f.v, upval: 876}", "{class: wlan_pdc, ss: rf, res: s5f.v, dwnval: 876}"; + + /* cpu mask used for wlan tx rx interrupt affinity + * + */ + wlan-txrx-intr-cpumask = <0x3 0x30>; }; }; diff --git a/sun-peach-cnss.dtsi b/sun-peach-cnss.dtsi index 38520f13..234feb43 100644 --- a/sun-peach-cnss.dtsi +++ b/sun-peach-cnss.dtsi @@ -192,6 +192,11 @@ "{class: wlan_pdc, ss: rf, res: s4j.v, enable: 1}", "{class: wlan_pdc, ss: rf, res: s4j.v, upval: 876}", "{class: wlan_pdc, ss: rf, res: s4j.v, dwnval: 876}"; + + /* cpu mask used for wlan tx rx interrupt affinity + * + */ + wlan-txrx-intr-cpumask = <0x3 0x30>; }; };