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ARM: dts: msm: add xo clock in sde_cesta for tuna target

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Add xo clock in sde_cesta for tuna target. This will help
to vote for xo frequency during cesta idle time.

Change-Id: I7cbf64c3121044d8976272bd690a718fda18a443
Signed-off-by: Sampurna Bolloju <quic_sampboll@quicinc.com>
This commit is contained in:
Sampurna Bolloju
2025-01-10 14:35:41 +05:30
committed by V S Ganga VaraPrasad (VARA) Adabala
parent 90c31f63d6
commit be951b9363
1 changed files with 7 additions and 6 deletions
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13
display/tuna-sde.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/clock/qcom,dispcc-tuna.h> #include <dt-bindings/clock/qcom,dispcc-tuna.h>
@@ -222,12 +222,13 @@
reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_XO_CLK_SRC>;
clock-names = "branch_clk", "core_clk"; clock-names = "branch_clk", "core_clk", "xo";
clock-rate = <660000000 660000000>; clock-rate = <660000000 660000000 19200000>;
clock-max-rate = <660000000 660000000>; clock-max-rate = <660000000 660000000 19200000>;
clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>;
interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0
&mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,