From be951b936323279c58eaa56f95775c11bf2e44cf Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Fri, 10 Jan 2025 14:35:41 +0530 Subject: [PATCH] ARM: dts: msm: add xo clock in sde_cesta for tuna target Add xo clock in sde_cesta for tuna target. This will help to vote for xo frequency during cesta idle time. Change-Id: I7cbf64c3121044d8976272bd690a718fda18a443 Signed-off-by: Sampurna Bolloju --- display/tuna-sde.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index a1de8490..672b44cc 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -222,12 +222,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <660000000 660000000>; - clock-max-rate = <660000000 660000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,