samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: msm: Fix IOMMU address reserve definition

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In order to ensure that IOMMU returns a 32 bit address, extend the
address and size cells to 2, in order to define a region that will
block 0xf0000000--0xffffffffffffffff.  By increasing the address and
size cells for the parent node, the DWC3 child node has to also
change the 'reg' entry to accommodate the added values.

Change-Id: Iaa413f0c3ac7100afea9a6d8e020bdb795866501
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
This commit is contained in:
Wesley Cheng
2024-03-21 15:53:03 -07:00
parent d8764e49fd
commit be60d48e81
1 changed files with 9 additions and 4 deletions
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13
qcom/sun-usb.dtsi
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@@ -12,8 +12,8 @@
reg = <0xa600000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
@@ -59,11 +59,11 @@
dwc3_0: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd93c>;
reg = <0x0 0xa600000 0x0 0xd93c>;
iommus = <&apps_smmu 0x40 0x0>;
qcom,iommu-dma = "atomic";
iommu-addresses = <&dwc3_0 0x0 0x90000000>, <&dwc3_0 0xf0000000 0x10000000>;
memory-region = <&dwc3_mem_region>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
@@ -83,6 +83,11 @@
};
};
dwc3_mem_region: dwc3_mem_region {
iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>,
<&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>;
};
/* USB port related High Speed PHY */
eusb2_phy0: hsphy@88e3000 {
compatible = "qcom,usb-m31-eusb2-phy";