From be60d48e81a72040a1383e05b62d212d53a7c433 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Thu, 21 Mar 2024 15:53:03 -0700 Subject: [PATCH] ARM: dts: msm: Fix IOMMU address reserve definition In order to ensure that IOMMU returns a 32 bit address, extend the address and size cells to 2, in order to define a region that will block 0xf0000000--0xffffffffffffffff. By increasing the address and size cells for the parent node, the DWC3 child node has to also change the 'reg' entry to accommodate the added values. Change-Id: Iaa413f0c3ac7100afea9a6d8e020bdb795866501 Signed-off-by: Wesley Cheng --- qcom/sun-usb.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/qcom/sun-usb.dtsi b/qcom/sun-usb.dtsi index 5f3be9fa..0a0d8f5e 100644 --- a/qcom/sun-usb.dtsi +++ b/qcom/sun-usb.dtsi @@ -12,8 +12,8 @@ reg = <0xa600000 0x100000>; reg-names = "core_base"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; @@ -59,11 +59,11 @@ dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xd93c>; + reg = <0x0 0xa600000 0x0 0xd93c>; iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "atomic"; - iommu-addresses = <&dwc3_0 0x0 0x90000000>, <&dwc3_0 0xf0000000 0x10000000>; + memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; @@ -83,6 +83,11 @@ }; }; + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, + <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + /* USB port related High Speed PHY */ eusb2_phy0: hsphy@88e3000 { compatible = "qcom,usb-m31-eusb2-phy";