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Merge f2b3fc782e on remote branch

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Change-Id: I25b95b94e9c69653ae3b26ec13f5833982c35241
This commit is contained in:
Linux Build Service Account
2024-05-21 00:37:59 -07:00
parent db52b9a9d5 f2b3fc782e
commit b9501a1c6c
7 changed files with 561 additions and 44 deletions
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3
Kbuild
View File

@@ -4,7 +4,8 @@ dtbo-y += gpu/pineapple-gpu.dtbo \
endif
ifeq ($(CONFIG_ARCH_SUN), y)
dtbo-y += gpu/sun-gpu.dtbo
dtbo-y += gpu/sun-gpu.dtbo \
gpu/sun-v2-gpu.dtbo
endif
always-y := $(dtb-y) $(dtbo-y)

124
gpu/sun-gpu-pwrlevels.dtsi
View File

@@ -4,18 +4,20 @@
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L1 0xa8285ffd
#define ACD_LEVEL_NOM_L1 0x88295ffd
#define ACD_LEVEL_NOM 0x88295ffd
#define ACD_LEVEL_SVS_L2 0x882a5ffd
#define ACD_LEVEL_SVS_L1 0x882a5ffd
#define ACD_LEVEL_SVS_L0 0xa82b5ffd
#define ACD_LEVEL_SVS 0xa82c5ffd
#define ACD_LEVEL_LOW_SVS_L1 0x882e5ffd
#define ACD_LEVEL_LOW_SVS 0xc0295ffd
#define ACD_LEVEL_LOW_SVS_D0 0xc02a5ffd
#define ACD_LEVEL_LOW_SVS_D1 0xc02b5ffd
#define ACD_LEVEL_LOW_SVS_D2 0xe8285ffd
#define ACD_LEVEL_TURBO_L4 0x88295ffd
#define ACD_LEVEL_TURBO_L3 0x882a5ffd
#define ACD_LEVEL_TURBO_L1 0x882a5ffd
#define ACD_LEVEL_NOM_L1 0x882b5ffd
#define ACD_LEVEL_NOM 0x882b5ffd
#define ACD_LEVEL_SVS_L2 0x882b5ffd
#define ACD_LEVEL_SVS_L1 0xa82b5ffd
#define ACD_LEVEL_SVS_L0 0x882d5ffd
#define ACD_LEVEL_SVS 0xa82e5ffd
#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd
#define ACD_LEVEL_LOW_SVS 0xe02d5ffd
#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd
#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd
#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd
&msm_gpu {
/* Power levels */
@@ -30,6 +32,7 @@
#size-cells = <0>;
qcom,initial-pwrlevel = <10>;
qcom,initial-min-pwrlevel = <10>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
@@ -175,18 +178,56 @@
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
};
/* Low_SVS_D3 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <125000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
qcom,bus-freq = <2>;
qcom,bus-min = <2>;
qcom,bus-max = <2>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <11>;
qcom,initial-pwrlevel = <13>;
qcom,initial-min-pwrlevel = <13>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
/* TURBO_L1 */
/* TURBO_L4 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1150000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L4>;
};
/* TURBO_L3 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
};
/* TURBO_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <967000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
@@ -198,8 +239,8 @@
};
/* NOM_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@@ -211,8 +252,8 @@
};
/* NOM */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -224,8 +265,8 @@
};
/* SVS_L2 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <779000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -237,8 +278,8 @@
};
/* SVS_L1 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -250,8 +291,8 @@
};
/* SVS_L0 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
@@ -263,8 +304,8 @@
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -276,8 +317,8 @@
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
@@ -289,8 +330,8 @@
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -302,8 +343,8 @@
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
@@ -315,8 +356,8 @@
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
@@ -328,8 +369,8 @@
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-pwrlevel@13 {
reg = <13>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
@@ -339,6 +380,17 @@
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
};
/* Low_SVS_D3 */
qcom,gpu-pwrlevel@14 {
reg = <14>;
qcom,gpu-freq = <125000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
qcom,bus-freq = <2>;
qcom,bus-min = <2>;
qcom,bus-max = <2>;
};
};
};
};

5
gpu/sun-gpu.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/clock/qcom,gpucc-sun.h>
#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sun.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -21,6 +22,6 @@
/ {
model = "Qualcomm Technologies, Inc. sun";
compatible = "qcom,sun";
qcom,msm-id = <618 0x10000>, <639 0x10000>;
qcom,msm-id = <0x26a 0x10000>, <0x27f 0x10000>, <0x100026a 0x10000>, <0x100027f 0x10000>;
qcom,board-id = <0 0>;
};

63
gpu/sun-gpu.dtsi
View File

@@ -136,7 +136,7 @@
compatible = "qcom,kgsl-smmu-v2";
reg = <0x3da0000 0x40000>;
vddcx-supply = <&gpu_cc_cx_gdsc>;
power-domains = <&gpucc GPU_CC_CX_GDSC>;
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
@@ -169,10 +169,9 @@
<0 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
regulator-names = "vddcx", "vdd";
vddcx-supply = <&gpu_cc_cx_gdsc>;
vdd-supply = <&gx_clkctl_gx_gdsc>;
power-domains = <&gpucc GPU_CC_CX_GDSC>,
<&gxclkctl GX_CLKCTL_GX_GDSC>;
power-domain-names = "cx", "gx";
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
@@ -196,4 +195,58 @@
qcom,qmp = <&aoss_qmp>;
};
coresight_cx_dgbc: qcom,gpu-coresight-cx {
compatible = "qcom,gpu-coresight-cx";
coresight-name = "coresight-gfx-cx";
out-ports {
port {
cx_dbgc_out_funnel_gfx: endpoint {
remote-endpoint =
<&funnel_gfx_in_cx_dbgc>;
};
};
};
};
coresight_gx_dgbc: qcom,gpu-coresight-gx {
compatible = "qcom,gpu-coresight-gx";
coresight-name = "coresight-gfx";
out-ports {
port {
gx_dbgc_out_funnel_gfx: endpoint {
remote-endpoint =
<&funnel_gfx_in_gx_dbgc>;
};
};
};
};
};
&funnel_gfx {
status = "ok";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_gfx_in_gx_dbgc: endpoint {
remote-endpoint =
<&gx_dbgc_out_funnel_gfx>;
};
};
port@1 {
reg = <1>;
funnel_gfx_in_cx_dbgc: endpoint {
remote-endpoint =
<&cx_dbgc_out_funnel_gfx>;
};
};
};
};

369
gpu/sun-v2-gpu-pwrlevels.dtsi Normal file
View File

@@ -0,0 +1,369 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L3 0x882a5ffd
#define ACD_LEVEL_TURBO_L1 0x882a5ffd
#define ACD_LEVEL_NOM_L1 0x882b5ffd
#define ACD_LEVEL_NOM 0x882b5ffd
#define ACD_LEVEL_SVS_L2 0x882b5ffd
#define ACD_LEVEL_SVS_L1 0xa82b5ffd
#define ACD_LEVEL_SVS_L0 0x882d5ffd
#define ACD_LEVEL_SVS 0xa82e5ffd
#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd
#define ACD_LEVEL_LOW_SVS 0xe02d5ffd
#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd
#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd
#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd
&msm_gpu {
/* Power levels */
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels-bins";
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <9>;
qcom,initial-min-pwrlevel = <9>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
/* NOM */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <10>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
};
/* Low_SVS_D3 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <160000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
qcom,bus-freq = <2>;
qcom,bus-min = <2>;
qcom,bus-max = <2>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <12>;
qcom,initial-min-pwrlevel = <12>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
/* TURBO_L3 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1150000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
};
/* TURBO_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* NOM_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <967000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <10>;
qcom,bus-min = <10>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* NOM */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <10>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <10>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
};
/* Low_SVS_D3 */
qcom,gpu-pwrlevel@13 {
reg = <13>;
qcom,gpu-freq = <160000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
qcom,bus-freq = <2>;
qcom,bus-min = <2>;
qcom,bus-max = <2>;
};
};
};
};

27
gpu/sun-v2-gpu.dts Normal file
View File

@@ -0,0 +1,27 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/clock/qcom,gpucc-sun.h>
#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sun.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sun-v2-gpu.dtsi"
#include "sun-v2-gpu-pwrlevels.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sun";
compatible = "qcom,sun";
qcom,msm-id = <0x26a 0x20000>, <0x27f 0x20000>, <0x100026a 0x20000>, <0x100027f 0x20000>;
qcom,board-id = <0 0>;
};

14
gpu/sun-v2-gpu.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-gpu.dtsi"
&msm_gpu {
compatible = "qcom,adreno-gpu-gen8-0-1", "qcom,kgsl-3d0";
qcom,gpu-model = "Adreno830v2";
qcom,chipid = <0x44050001>;
};