From 791bff1a21ca7cbb7e2dbfb874dac70ea6dcc843 Mon Sep 17 00:00:00 2001
From: Kamal Agrawal <quic_kamaagra@quicinc.com>
Date: Sat, 20 Jan 2024 14:59:59 +0530
Subject: [PATCH 1/8] ARM: dts: msm: Add coresight configurations for sun

Add device tree nodes for coresight CX and GX DBGC blocks
for sun devices. Also, add coresight funnel configuration
for graphics funnel device.

Change-Id: Id0a73ac9ef51e1039b718d5d51a4fc063d218a94
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
---
 gpu/sun-gpu.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi
index 46db9ce5..36642261 100644
--- a/gpu/sun-gpu.dtsi
+++ b/gpu/sun-gpu.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
@@ -178,4 +178,58 @@
 
 		qcom,ipc-core = <0x00400000 0x140000>;
 	};
+
+	coresight_cx_dgbc: qcom,gpu-coresight-cx {
+		compatible = "qcom,gpu-coresight-cx";
+
+		coresight-name = "coresight-gfx-cx";
+
+		out-ports {
+			port {
+				cx_dbgc_out_funnel_gfx: endpoint {
+					remote-endpoint =
+					  <&funnel_gfx_in_cx_dbgc>;
+				};
+			};
+		};
+	};
+
+	coresight_gx_dgbc: qcom,gpu-coresight-gx {
+		compatible = "qcom,gpu-coresight-gx";
+
+		coresight-name = "coresight-gfx";
+
+		out-ports {
+			port {
+				gx_dbgc_out_funnel_gfx: endpoint {
+					remote-endpoint =
+					  <&funnel_gfx_in_gx_dbgc>;
+				};
+			};
+		};
+	};
+};
+
+&funnel_gfx {
+	status = "ok";
+	in-ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			funnel_gfx_in_gx_dbgc: endpoint {
+			remote-endpoint =
+				<&gx_dbgc_out_funnel_gfx>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			funnel_gfx_in_cx_dbgc: endpoint {
+			remote-endpoint =
+				<&cx_dbgc_out_funnel_gfx>;
+			};
+		};
+	};
 };

From 300aef810b6a30b3912a02ab9d7c817ae03db6e5 Mon Sep 17 00:00:00 2001
From: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Date: Tue, 5 Mar 2024 10:18:50 -0800
Subject: [PATCH 2/8] ARM: dts: msm: Add turbo_l3 power level to Sun GPU

Add supported higher power level to Sun GPU.

Change-Id: I6b33a69d09285f480bc24acfdd0df462ff25bcfb
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
---
 gpu/sun-gpu-pwrlevels.dtsi | 62 +++++++++++++++++++++++---------------
 1 file changed, 38 insertions(+), 24 deletions(-)

diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi
index 86732352..5f15d4bd 100644
--- a/gpu/sun-gpu-pwrlevels.dtsi
+++ b/gpu/sun-gpu-pwrlevels.dtsi
@@ -4,6 +4,7 @@
  */
 
 /* ACD Control register values */
+#define ACD_LEVEL_TURBO_L3    0xa02f5ffd
 #define ACD_LEVEL_TURBO_L1    0xa8285ffd
 #define ACD_LEVEL_NOM_L1      0x88295ffd
 #define ACD_LEVEL_NOM         0x88295ffd
@@ -181,12 +182,25 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			qcom,initial-pwrlevel = <11>;
+			qcom,initial-pwrlevel = <12>;
 			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
 
-			/* TURBO_L1 */
+			/* TURBO_L3 */
 			qcom,gpu-pwrlevel@0 {
 				reg = <0>;
+				qcom,gpu-freq = <1050000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+
+				qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
+			};
+
+			/* TURBO_L1 */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
 				qcom,gpu-freq = <967000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 
@@ -198,8 +212,8 @@
 			};
 
 			/* NOM_L1 */
-			qcom,gpu-pwrlevel@1 {
-				reg = <1>;
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
 				qcom,gpu-freq = <900000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 
@@ -211,8 +225,8 @@
 			};
 
 			/* NOM */
-			qcom,gpu-pwrlevel@2 {
-				reg = <2>;
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
 				qcom,gpu-freq = <832000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
@@ -224,8 +238,8 @@
 			};
 
 			/* SVS_L2 */
-			qcom,gpu-pwrlevel@3 {
-				reg = <3>;
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
 				qcom,gpu-freq = <779000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
@@ -237,8 +251,8 @@
 			};
 
 			/* SVS_L1 */
-			qcom,gpu-pwrlevel@4 {
-				reg = <4>;
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
 				qcom,gpu-freq = <734000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
@@ -250,8 +264,8 @@
 			};
 
 			/* SVS_L0 */
-			qcom,gpu-pwrlevel@5 {
-				reg = <5>;
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
 				qcom,gpu-freq = <660000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
 
@@ -263,8 +277,8 @@
 			};
 
 			/* SVS */
-			qcom,gpu-pwrlevel@6 {
-				reg = <6>;
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
 				qcom,gpu-freq = <607000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
 
@@ -276,8 +290,8 @@
 			};
 
 			/* Low_SVS_L1 */
-			qcom,gpu-pwrlevel@7 {
-				reg = <7>;
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
 				qcom,gpu-freq = <525000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
 
@@ -289,8 +303,8 @@
 			};
 
 			/* Low_SVS */
-			qcom,gpu-pwrlevel@8 {
-				reg = <8>;
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
 				qcom,gpu-freq = <443000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 
@@ -302,8 +316,8 @@
 			};
 
 			/* Low_SVS_D0 */
-			qcom,gpu-pwrlevel@9 {
-				reg = <9>;
+			qcom,gpu-pwrlevel@10 {
+				reg = <10>;
 				qcom,gpu-freq = <389000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
 
@@ -315,8 +329,8 @@
 			};
 
 			/* Low_SVS_D1 */
-			qcom,gpu-pwrlevel@10 {
-				reg = <10>;
+			qcom,gpu-pwrlevel@11 {
+				reg = <11>;
 				qcom,gpu-freq = <342000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
 
@@ -328,8 +342,8 @@
 			};
 
 			/* Low_SVS_D2 */
-			qcom,gpu-pwrlevel@11 {
-				reg = <11>;
+			qcom,gpu-pwrlevel@12 {
+				reg = <12>;
 				qcom,gpu-freq = <222000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
 

From 2cc3321179d81ae7388562bb6c54db616db87d0b Mon Sep 17 00:00:00 2001
From: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Date: Tue, 19 Mar 2024 15:51:47 -0700
Subject: [PATCH 3/8] ARM: dts: msm: Add lowSVS_D3 power level to Sun GPU

Add supported lower power level to Sun GPU.

Change-Id: I896fe7cd45d1b1a824d3a0d7c47115952d8598ea
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
---
 gpu/sun-gpu-pwrlevels.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi
index 5f15d4bd..38f67d72 100644
--- a/gpu/sun-gpu-pwrlevels.dtsi
+++ b/gpu/sun-gpu-pwrlevels.dtsi
@@ -31,6 +31,7 @@
 			#size-cells = <0>;
 
 			qcom,initial-pwrlevel = <10>;
+			qcom,initial-min-pwrlevel = <10>;
 			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
 					SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
 
@@ -176,6 +177,17 @@
 
 				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
 			};
+
+			/* Low_SVS_D3 */
+			qcom,gpu-pwrlevel@11 {
+				reg = <11>;
+				qcom,gpu-freq = <125000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+
+				qcom,bus-freq = <2>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <2>;
+			};
 		};
 
 		qcom,gpu-pwrlevels-1 {
@@ -183,6 +195,7 @@
 			#size-cells = <0>;
 
 			qcom,initial-pwrlevel = <12>;
+			qcom,initial-min-pwrlevel = <12>;
 			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
 
 			/* TURBO_L3 */
@@ -353,6 +366,17 @@
 
 				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
 			};
+
+			/* Low_SVS_D3 */
+			qcom,gpu-pwrlevel@13 {
+				reg = <13>;
+				qcom,gpu-freq = <125000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+
+				qcom,bus-freq = <2>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <2>;
+			};
 		};
 	};
 };

From cb1a9008b35a4133536f7f641b5be12d53b7c2ea Mon Sep 17 00:00:00 2001
From: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Date: Tue, 5 Mar 2024 10:23:28 -0800
Subject: [PATCH 4/8] ARM: dts: msm: Add turbo_l4 power level to Sun GPU

Add supported higher power level to Sun GPU.

Change-Id: Icfbdae6f7b44edea00fbf3374224cb407bd0968d
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
---
 gpu/sun-gpu-pwrlevels.dtsi | 72 +++++++++++++++++++++++---------------
 1 file changed, 43 insertions(+), 29 deletions(-)

diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi
index 38f67d72..4e8c09c1 100644
--- a/gpu/sun-gpu-pwrlevels.dtsi
+++ b/gpu/sun-gpu-pwrlevels.dtsi
@@ -4,6 +4,7 @@
  */
 
 /* ACD Control register values */
+#define ACD_LEVEL_TURBO_L4    0x802e5ffd
 #define ACD_LEVEL_TURBO_L3    0xa02f5ffd
 #define ACD_LEVEL_TURBO_L1    0xa8285ffd
 #define ACD_LEVEL_NOM_L1      0x88295ffd
@@ -194,13 +195,26 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			qcom,initial-pwrlevel = <12>;
-			qcom,initial-min-pwrlevel = <12>;
+			qcom,initial-pwrlevel = <13>;
+			qcom,initial-min-pwrlevel = <13>;
 			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
 
-			/* TURBO_L3 */
+			/* TURBO_L4 */
 			qcom,gpu-pwrlevel@0 {
 				reg = <0>;
+				qcom,gpu-freq = <1150000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+
+				qcom,acd-level = <ACD_LEVEL_TURBO_L4>;
+			};
+
+			/* TURBO_L3 */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
 				qcom,gpu-freq = <1050000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
 
@@ -212,8 +226,8 @@
 			};
 
 			/* TURBO_L1 */
-			qcom,gpu-pwrlevel@1 {
-				reg = <1>;
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
 				qcom,gpu-freq = <967000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 
@@ -225,8 +239,8 @@
 			};
 
 			/* NOM_L1 */
-			qcom,gpu-pwrlevel@2 {
-				reg = <2>;
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
 				qcom,gpu-freq = <900000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 
@@ -238,8 +252,8 @@
 			};
 
 			/* NOM */
-			qcom,gpu-pwrlevel@3 {
-				reg = <3>;
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
 				qcom,gpu-freq = <832000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
@@ -251,8 +265,8 @@
 			};
 
 			/* SVS_L2 */
-			qcom,gpu-pwrlevel@4 {
-				reg = <4>;
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
 				qcom,gpu-freq = <779000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
@@ -264,8 +278,8 @@
 			};
 
 			/* SVS_L1 */
-			qcom,gpu-pwrlevel@5 {
-				reg = <5>;
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
 				qcom,gpu-freq = <734000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
@@ -277,8 +291,8 @@
 			};
 
 			/* SVS_L0 */
-			qcom,gpu-pwrlevel@6 {
-				reg = <6>;
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
 				qcom,gpu-freq = <660000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
 
@@ -290,8 +304,8 @@
 			};
 
 			/* SVS */
-			qcom,gpu-pwrlevel@7 {
-				reg = <7>;
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
 				qcom,gpu-freq = <607000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
 
@@ -303,8 +317,8 @@
 			};
 
 			/* Low_SVS_L1 */
-			qcom,gpu-pwrlevel@8 {
-				reg = <8>;
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
 				qcom,gpu-freq = <525000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
 
@@ -316,8 +330,8 @@
 			};
 
 			/* Low_SVS */
-			qcom,gpu-pwrlevel@9 {
-				reg = <9>;
+			qcom,gpu-pwrlevel@10 {
+				reg = <10>;
 				qcom,gpu-freq = <443000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 
@@ -329,8 +343,8 @@
 			};
 
 			/* Low_SVS_D0 */
-			qcom,gpu-pwrlevel@10 {
-				reg = <10>;
+			qcom,gpu-pwrlevel@11 {
+				reg = <11>;
 				qcom,gpu-freq = <389000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
 
@@ -342,8 +356,8 @@
 			};
 
 			/* Low_SVS_D1 */
-			qcom,gpu-pwrlevel@11 {
-				reg = <11>;
+			qcom,gpu-pwrlevel@12 {
+				reg = <12>;
 				qcom,gpu-freq = <342000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
 
@@ -355,8 +369,8 @@
 			};
 
 			/* Low_SVS_D2 */
-			qcom,gpu-pwrlevel@12 {
-				reg = <12>;
+			qcom,gpu-pwrlevel@13 {
+				reg = <13>;
 				qcom,gpu-freq = <222000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
 
@@ -368,8 +382,8 @@
 			};
 
 			/* Low_SVS_D3 */
-			qcom,gpu-pwrlevel@13 {
-				reg = <13>;
+			qcom,gpu-pwrlevel@14 {
+				reg = <14>;
 				qcom,gpu-freq = <125000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
 

From 69ade8a5f00c24f4224aa56d782ec5c6ef572ecc Mon Sep 17 00:00:00 2001
From: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Date: Fri, 8 Mar 2024 10:25:45 -0800
Subject: [PATCH 5/8] ARM: dts: msm: Update ACD values for Sun GPU

Update ACD control register values with characterized values.

Change-Id: I6e605b578db6da4d31e28e5fadc1bad991a2d9d1
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
---
 gpu/sun-gpu-pwrlevels.dtsi | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi
index 4e8c09c1..41adb786 100644
--- a/gpu/sun-gpu-pwrlevels.dtsi
+++ b/gpu/sun-gpu-pwrlevels.dtsi
@@ -4,20 +4,20 @@
  */
 
 /* ACD Control register values */
-#define ACD_LEVEL_TURBO_L4    0x802e5ffd
-#define ACD_LEVEL_TURBO_L3    0xa02f5ffd
-#define ACD_LEVEL_TURBO_L1    0xa8285ffd
-#define ACD_LEVEL_NOM_L1      0x88295ffd
-#define ACD_LEVEL_NOM         0x88295ffd
-#define ACD_LEVEL_SVS_L2      0x882a5ffd
-#define ACD_LEVEL_SVS_L1      0x882a5ffd
-#define ACD_LEVEL_SVS_L0      0xa82b5ffd
-#define ACD_LEVEL_SVS         0xa82c5ffd
-#define ACD_LEVEL_LOW_SVS_L1  0x882e5ffd
-#define ACD_LEVEL_LOW_SVS     0xc0295ffd
-#define ACD_LEVEL_LOW_SVS_D0  0xc02a5ffd
-#define ACD_LEVEL_LOW_SVS_D1  0xc02b5ffd
-#define ACD_LEVEL_LOW_SVS_D2  0xe8285ffd
+#define ACD_LEVEL_TURBO_L4    0x88295ffd
+#define ACD_LEVEL_TURBO_L3    0x882a5ffd
+#define ACD_LEVEL_TURBO_L1    0x882a5ffd
+#define ACD_LEVEL_NOM_L1      0x882b5ffd
+#define ACD_LEVEL_NOM         0x882b5ffd
+#define ACD_LEVEL_SVS_L2      0x882b5ffd
+#define ACD_LEVEL_SVS_L1      0xa82b5ffd
+#define ACD_LEVEL_SVS_L0      0x882d5ffd
+#define ACD_LEVEL_SVS         0xa82e5ffd
+#define ACD_LEVEL_LOW_SVS_L1  0xc0285ffd
+#define ACD_LEVEL_LOW_SVS     0xe02d5ffd
+#define ACD_LEVEL_LOW_SVS_D0  0xe02f5ffd
+#define ACD_LEVEL_LOW_SVS_D1  0xe8285ffd
+#define ACD_LEVEL_LOW_SVS_D2  0xe82f5ffd
 
 &msm_gpu {
 	/* Power levels */

From 564471dede9eda4d761c97aa97811d485fffbab3 Mon Sep 17 00:00:00 2001
From: Kamal Agrawal <quic_kamaagra@quicinc.com>
Date: Tue, 13 Feb 2024 01:47:52 +0530
Subject: [PATCH 6/8] ARM: dts: msm: Add power domains for sun GPU
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

GDSCs were modeled as regulators till now. However,
moving forward, GDSCs will be treated as power domains.
Consequently, replace references to ‘regulators’ with
‘power domains’ for the sun GPU.

Change-Id: I607a511754d56728d5013004d0ae83544f873df6
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
---
 gpu/sun-gpu.dts  | 3 ++-
 gpu/sun-gpu.dtsi | 9 ++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts
index eda85863..e0cc7986 100644
--- a/gpu/sun-gpu.dts
+++ b/gpu/sun-gpu.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 /dts-v1/;
@@ -9,6 +9,7 @@
 #include <dt-bindings/clock/qcom,aop-qmp.h>
 #include <dt-bindings/clock/qcom,gcc-sun.h>
 #include <dt-bindings/clock/qcom,gpucc-sun.h>
+#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interconnect/qcom,sun.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi
index 548a1bb0..21cbd14d 100644
--- a/gpu/sun-gpu.dtsi
+++ b/gpu/sun-gpu.dtsi
@@ -136,7 +136,7 @@
 		compatible = "qcom,kgsl-smmu-v2";
 		reg = <0x3da0000 0x40000>;
 
-		vddcx-supply = <&gpu_cc_cx_gdsc>;
+		power-domains = <&gpucc GPU_CC_CX_GDSC>;
 
 		gfx3d_user: gfx3d_user {
 			compatible = "qcom,smmu-kgsl-cb";
@@ -169,10 +169,9 @@
 			<0 305 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "hfi", "gmu";
 
-		regulator-names = "vddcx", "vdd";
-
-		vddcx-supply = <&gpu_cc_cx_gdsc>;
-		vdd-supply = <&gx_clkctl_gx_gdsc>;
+		power-domains = <&gpucc GPU_CC_CX_GDSC>,
+				<&gxclkctl GX_CLKCTL_GX_GDSC>;
+		power-domain-names = "cx", "gx";
 
 		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
 			<&gpucc GPU_CC_CXO_CLK>,

From 669e9df2ea76a84551666011cffaffdaaeec34ef Mon Sep 17 00:00:00 2001
From: Carter Cooper <quic_ccooper@quicinc.com>
Date: Fri, 29 Mar 2024 15:21:29 -0600
Subject: [PATCH 7/8] ARM: dts: msm: Add additional Sun GPU msm-id support

Add new msm-id support for Sun GPU V1.

Change-Id: I38eeabb8a13ac533b76abfb26f0faa81214f36bf
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
---
 gpu/sun-gpu.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts
index eda85863..26c509a4 100644
--- a/gpu/sun-gpu.dts
+++ b/gpu/sun-gpu.dts
@@ -21,6 +21,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. sun";
 	compatible = "qcom,sun";
-	qcom,msm-id = <618 0x10000>, <639 0x10000>;
+	qcom,msm-id = <0x26a 0x10000>, <0x27f 0x10000>, <0x100026a 0x10000>, <0x100027f 0x10000>;
 	qcom,board-id = <0 0>;
 };

From 5641f98ed82df2fff798fac50f628251f09d3212 Mon Sep 17 00:00:00 2001
From: Carter Cooper <quic_ccooper@quicinc.com>
Date: Tue, 12 Mar 2024 14:40:49 -0600
Subject: [PATCH 8/8] ARM: dts: msm: Add Sun V2 GPU support

Add GPU support for Sun V2 devices.

Change-Id: I8fab9d400ace2257e486fadc5e41836013e09c77
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
---
 Kbuild                        |   3 +-
 gpu/sun-v2-gpu-pwrlevels.dtsi | 369 ++++++++++++++++++++++++++++++++++
 gpu/sun-v2-gpu.dts            |  27 +++
 gpu/sun-v2-gpu.dtsi           |  14 ++
 4 files changed, 412 insertions(+), 1 deletion(-)
 create mode 100644 gpu/sun-v2-gpu-pwrlevels.dtsi
 create mode 100644 gpu/sun-v2-gpu.dts
 create mode 100644 gpu/sun-v2-gpu.dtsi

diff --git a/Kbuild b/Kbuild
index 82161dd3..da849afb 100644
--- a/Kbuild
+++ b/Kbuild
@@ -4,7 +4,8 @@ dtbo-y += gpu/pineapple-gpu.dtbo \
 endif
 
 ifeq ($(CONFIG_ARCH_SUN), y)
-dtbo-y += gpu/sun-gpu.dtbo
+dtbo-y += gpu/sun-gpu.dtbo \
+		gpu/sun-v2-gpu.dtbo
 endif
 
 always-y    := $(dtb-y) $(dtbo-y)
diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi
new file mode 100644
index 00000000..8d44b096
--- /dev/null
+++ b/gpu/sun-v2-gpu-pwrlevels.dtsi
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/* ACD Control register values */
+#define ACD_LEVEL_TURBO_L3    0x882a5ffd
+#define ACD_LEVEL_TURBO_L1    0x882a5ffd
+#define ACD_LEVEL_NOM_L1      0x882b5ffd
+#define ACD_LEVEL_NOM         0x882b5ffd
+#define ACD_LEVEL_SVS_L2      0x882b5ffd
+#define ACD_LEVEL_SVS_L1      0xa82b5ffd
+#define ACD_LEVEL_SVS_L0      0x882d5ffd
+#define ACD_LEVEL_SVS         0xa82e5ffd
+#define ACD_LEVEL_LOW_SVS_L1  0xc0285ffd
+#define ACD_LEVEL_LOW_SVS     0xe02d5ffd
+#define ACD_LEVEL_LOW_SVS_D0  0xe02f5ffd
+#define ACD_LEVEL_LOW_SVS_D1  0xe8285ffd
+#define ACD_LEVEL_LOW_SVS_D2  0xe82f5ffd
+
+&msm_gpu {
+	/* Power levels */
+	qcom,gpu-pwrlevel-bins {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "qcom,gpu-pwrlevels-bins";
+
+		qcom,gpu-pwrlevels-0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,initial-pwrlevel = <9>;
+			qcom,initial-min-pwrlevel = <9>;
+			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
+					SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
+
+			/* NOM */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <900000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+
+				qcom,acd-level = <ACD_LEVEL_NOM>;
+			};
+
+			/* SVS_L2 */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <832000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L2>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <734000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq = <8>;
+				qcom,bus-min = <6>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L1>;
+			};
+
+			/* SVS_L0 */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <660000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L0>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <607000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS>;
+			};
+
+			/* Low_SVS_L1 */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <525000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
+			};
+
+			/* Low_SVS */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <443000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
+			};
+
+			/* Low_SVS_D0 */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <389000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
+			};
+
+			/* Low_SVS_D1 */
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <342000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
+			};
+
+			/* Low_SVS_D2 */
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
+				qcom,gpu-freq = <222000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <3>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
+			};
+
+			/* Low_SVS_D3 */
+			qcom,gpu-pwrlevel@10 {
+				reg = <10>;
+				qcom,gpu-freq = <160000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+
+				qcom,bus-freq = <2>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <2>;
+			};
+		};
+
+		qcom,gpu-pwrlevels-1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,initial-pwrlevel = <12>;
+			qcom,initial-min-pwrlevel = <12>;
+			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
+
+			/* TURBO_L3 */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1150000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+
+				qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
+			};
+
+			/* TURBO_L1 */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <1050000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+
+				qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
+			};
+
+			/* NOM_L1 */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <967000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <10>;
+				qcom,bus-max = <11>;
+
+				qcom,acd-level = <ACD_LEVEL_NOM_L1>;
+			};
+
+			/* NOM */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <900000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <ACD_LEVEL_NOM>;
+			};
+
+			/* SVS_L2 */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <832000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L2>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <734000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq = <8>;
+				qcom,bus-min = <6>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L1>;
+			};
+
+			/* SVS_L0 */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <660000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L0>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <607000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS>;
+			};
+
+			/* Low_SVS_L1 */
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <525000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
+			};
+
+			/* Low_SVS */
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
+				qcom,gpu-freq = <443000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
+			};
+
+			/* Low_SVS_D0 */
+			qcom,gpu-pwrlevel@10 {
+				reg = <10>;
+				qcom,gpu-freq = <389000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
+			};
+
+			/* Low_SVS_D1 */
+			qcom,gpu-pwrlevel@11 {
+				reg = <11>;
+				qcom,gpu-freq = <342000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
+			};
+
+			/* Low_SVS_D2 */
+			qcom,gpu-pwrlevel@12 {
+				reg = <12>;
+				qcom,gpu-freq = <222000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <3>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
+			};
+
+			/* Low_SVS_D3 */
+			qcom,gpu-pwrlevel@13 {
+				reg = <13>;
+				qcom,gpu-freq = <160000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+
+				qcom,bus-freq = <2>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <2>;
+			};
+		};
+	};
+};
diff --git a/gpu/sun-v2-gpu.dts b/gpu/sun-v2-gpu.dts
new file mode 100644
index 00000000..662cfb91
--- /dev/null
+++ b/gpu/sun-v2-gpu.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
+#include <dt-bindings/clock/qcom,gpucc-sun.h>
+#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,sun.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sun-v2-gpu.dtsi"
+#include "sun-v2-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. sun";
+	compatible = "qcom,sun";
+	qcom,msm-id = <0x26a 0x20000>, <0x27f 0x20000>, <0x100026a 0x20000>, <0x100027f 0x20000>;
+	qcom,board-id = <0 0>;
+};
diff --git a/gpu/sun-v2-gpu.dtsi b/gpu/sun-v2-gpu.dtsi
new file mode 100644
index 00000000..b9366d3f
--- /dev/null
+++ b/gpu/sun-v2-gpu.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sun-gpu.dtsi"
+
+&msm_gpu {
+	compatible = "qcom,adreno-gpu-gen8-0-1", "qcom,kgsl-3d0";
+
+	qcom,gpu-model = "Adreno830v2";
+
+	qcom,chipid = <0x44050001>;
+};