samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge 565fe13eff on remote branch

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Change-Id: Id333822600b8184755a55cffb3955b97c05464b3
This commit is contained in:
Linux Build Service Account
2025-03-07 04:01:13 -08:00
parent 36353b1e55 565fe13eff
commit b25f8771b8
3 changed files with 147 additions and 80 deletions
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8
kera-qca6750.dtsi
View File

@@ -125,11 +125,15 @@
qcom,qmp = <&aoss_qmp>; qcom,qmp = <&aoss_qmp>;
qcom,vreg_ol_cpr ="s3b"; qcom,vreg_ol_cpr ="s3b";
icnss_cdev_apss: qcom,icnss_cdev1 { icnss_cdev_apss: icnss_cdev1 {
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
icnss_cdev_wpss: qcom,icnss_cdev2 { icnss_cdev_wpss: icnss_cdev2 {
#cooling-cells = <2>;
};
icnss_cdev_bw: icnss_cdev3 {
#cooling-cells = <2>; #cooling-cells = <2>;
}; };

106
kera-wcn7750.dtsi
View File

@@ -146,50 +146,106 @@
qcom,icc-path-count = <2>; qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>; qcom,bus-bw-cfg-count = <9>;
/* ddr_type = 8(LPDDR5) */
ddr_cfg@0 {
ddr_type = <8>;
qcom,bus-bw-cfg = qcom,bus-bw-cfg =
/** ICC Path 1 **/ /** ICC Path 1 **/
<0 0>, /* no vote */ <0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 1200000>, <2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */ /* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 1200000>, <7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 1200000>, <30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 1200000>, <100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */ /* very high: > 1200 Mbps snoc/anoc: 200 Mhz */
<175000 3224000>, <175000 1600000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */ /* ultra high: DBS mode snoc/anoc: 200 Mhz */
<312500 3224000>, <312500 1600000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */ /* super high: DBS mode snoc/anoc: 403 Mhz */
<587500 4264000>, <587500 3224000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>, <7500 1600000>,
/** ICC Path 2 **/ /** ICC Path 2 **/
<0 0>, <0 0>,
/* idle: 0-18 Mbps ddr: 451.2 MHz */ /* idle: 0-18 Mbps ddr: 547 MHz */
<2250 2188800>, <2250 2500800>,
/* low: 18-60 Mbps ddr: 451.2 MHz */ /* low: 18-60 Mbps ddr: 547 MHz */
<7500 2188800>, <7500 2500800>,
/* medium: 60-240 Mbps ddr: 451.2 MHz */ /* medium: 60-240 Mbps ddr: 547 MHz */
<30000 2188800>, <30000 2500800>,
/* high: 240-1200 Mbps ddr: 451.2 MHz */ /* high: 240-1200 Mbps ddr: 547 MHz */
<100000 2188800>, <100000 2500800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */ /* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>, <175000 7108800>,
/* ultra high: DBS mode ddr: 2092 MHz */ /* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>, <312500 9566400>,
/* super high: DBS mode ddr: 3.2 GHz */ /* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>, <587500 14569200>,
/* low (latency critical): 18-60 Mbps ddr: 451.2 MHz */ /* low (latency critical): 18-60 Mbps ddr: 547 MHz */
<7500 2188800>; <7500 2500800>;
};
icnss_cdev_apss: qcom,icnss_cdev1 { /* ddr_type = 7(LPDDR4) */
ddr_cfg@1 {
ddr_type = <7>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 200 Mhz */
<175000 1600000>,
/* ultra high: DBS mode snoc/anoc: 200 Mhz */
<312500 1600000>,
/* super high: DBS mode snoc/anoc: 403 Mhz */
<587500 3224000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547 MHz */
<2250 2500800>,
/* low: 18-60 Mbps ddr: 547 MHz */
<7500 2500800>,
/* medium: 60-240 Mbps ddr: 547 MHz */
<30000 2500800>,
/* high: 240-1200 Mbps ddr: 547 MHz */
<100000 2500800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 7108800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 9566400>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 14569200>,
/* low (latency critical): 18-60 Mbps ddr: 547 MHz */
<7500 2500800>;
};
icnss_cdev_apss: icnss_cdev1 {
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
icnss_cdev_wpss: qcom,icnss_cdev2 { icnss_cdev_wpss: icnss_cdev2 {
#cooling-cells = <2>;
};
icnss_cdev_bw: icnss_cdev3 {
#cooling-cells = <2>; #cooling-cells = <2>;
}; };

11
tuna-wcn7750.dtsi
View File

@@ -139,6 +139,12 @@
qcom,icc-path-count = <2>; qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>; qcom,bus-bw-cfg-count = <9>;
/* ddr_type = 8(LPDDR5) */
ddr_cfg@0 {
ddr_type = <8>;
qcom,bus-bw-cfg = qcom,bus-bw-cfg =
/** ICC Path 1 **/ /** ICC Path 1 **/
<0 0>, /* no vote */ <0 0>, /* no vote */
@@ -177,12 +183,13 @@
<587500 14745600>, <587500 14745600>,
/* low (latency critical): 18-60 Mbps ddr: 2092 MHz */ /* low (latency critical): 18-60 Mbps ddr: 2092 MHz */
<7500 8371200>; <7500 8371200>;
};
icnss_cdev_apss: qcom,icnss_cdev1 { icnss_cdev_apss: icnss_cdev1 {
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
icnss_cdev_wpss: qcom,icnss_cdev2 { icnss_cdev_wpss: icnss_cdev2 {
#cooling-cells = <2>; #cooling-cells = <2>;
}; };