From dbe8ff2b614578ed864d9c5245e69801e3826221 Mon Sep 17 00:00:00 2001 From: Kartikey Arora Date: Tue, 11 Feb 2025 12:49:07 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Update cooling device node name in dtsi This change adds a new third cooling device node to support BW mitigation request and updates existing cooling device node name in dtsi to remove qcom, prefix so it is considered as single node and not two due to comma separated while parsing it in csv format. Change-Id: I341a2412159d2af6123a3bc4f2323a38b7955b62 --- kera-qca6750.dtsi | 8 ++++++-- kera-wcn7750.dtsi | 8 ++++++-- tuna-wcn7750.dtsi | 4 ++-- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/kera-qca6750.dtsi b/kera-qca6750.dtsi index fcbb278c..f291873a 100644 --- a/kera-qca6750.dtsi +++ b/kera-qca6750.dtsi @@ -125,11 +125,15 @@ qcom,qmp = <&aoss_qmp>; qcom,vreg_ol_cpr ="s3b"; - icnss_cdev_apss: qcom,icnss_cdev1 { + icnss_cdev_apss: icnss_cdev1 { #cooling-cells = <2>; }; - icnss_cdev_wpss: qcom,icnss_cdev2 { + icnss_cdev_wpss: icnss_cdev2 { + #cooling-cells = <2>; + }; + + icnss_cdev_bw: icnss_cdev3 { #cooling-cells = <2>; }; diff --git a/kera-wcn7750.dtsi b/kera-wcn7750.dtsi index e043257f..4e071bbe 100644 --- a/kera-wcn7750.dtsi +++ b/kera-wcn7750.dtsi @@ -185,11 +185,15 @@ /* low (latency critical): 18-60 Mbps ddr: 451.2 MHz */ <7500 2188800>; - icnss_cdev_apss: qcom,icnss_cdev1 { + icnss_cdev_apss: icnss_cdev1 { #cooling-cells = <2>; }; - icnss_cdev_wpss: qcom,icnss_cdev2 { + icnss_cdev_wpss: icnss_cdev2 { + #cooling-cells = <2>; + }; + + icnss_cdev_bw: icnss_cdev3 { #cooling-cells = <2>; }; diff --git a/tuna-wcn7750.dtsi b/tuna-wcn7750.dtsi index ba7a33f3..6b6069b7 100644 --- a/tuna-wcn7750.dtsi +++ b/tuna-wcn7750.dtsi @@ -178,11 +178,11 @@ /* low (latency critical): 18-60 Mbps ddr: 2092 MHz */ <7500 8371200>; - icnss_cdev_apss: qcom,icnss_cdev1 { + icnss_cdev_apss: icnss_cdev1 { #cooling-cells = <2>; }; - icnss_cdev_wpss: qcom,icnss_cdev2 { + icnss_cdev_wpss: icnss_cdev2 { #cooling-cells = <2>; }; From a168cc8b8132c203e1083e4919356fd0c5de8843 Mon Sep 17 00:00:00 2001 From: Prateek Patil Date: Mon, 10 Feb 2025 14:47:31 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Modify interconnect bus bw config based on DDR type Modify interconnect bus bw config based on DDR TYPE in tuna-wcn7750 kera-wcn7750 dtsi. Change-Id: I6be90ea224c6cd1872ec399cf709f4736aa156e9 CRs-Fixed: 4057869 --- kera-wcn7750.dtsi | 126 ++++++++++++++++++++++++++++++++-------------- tuna-wcn7750.dtsi | 81 +++++++++++++++-------------- 2 files changed, 133 insertions(+), 74 deletions(-) diff --git a/kera-wcn7750.dtsi b/kera-wcn7750.dtsi index e043257f..32053e9d 100644 --- a/kera-wcn7750.dtsi +++ b/kera-wcn7750.dtsi @@ -146,44 +146,96 @@ qcom,icc-path-count = <2>; qcom,bus-bw-cfg-count = <9>; - qcom,bus-bw-cfg = - /** ICC Path 1 **/ - <0 0>, /* no vote */ - /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ - <2250 1200000>, - /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ - <7500 1200000>, - /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ - <30000 1200000>, - /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ - <100000 1200000>, - /* very high: > 1200 Mbps snoc/anoc: 403 Mhz */ - <175000 3224000>, - /* ultra high: DBS mode snoc/anoc: 403 Mhz */ - <312500 3224000>, - /* super high: DBS mode snoc/anoc: 533 Mhz */ - <587500 4264000>, - /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ - <7500 1600000>, - /** ICC Path 2 **/ - <0 0>, - /* idle: 0-18 Mbps ddr: 451.2 MHz */ - <2250 2188800>, - /* low: 18-60 Mbps ddr: 451.2 MHz */ - <7500 2188800>, - /* medium: 60-240 Mbps ddr: 451.2 MHz */ - <30000 2188800>, - /* high: 240-1200 Mbps ddr: 451.2 MHz */ - <100000 2188800>, - /* very high: > 1200 Mbps ddr: 1555 MHz */ - <175000 6220800>, - /* ultra high: DBS mode ddr: 2092 MHz */ - <312500 8368000>, - /* super high: DBS mode ddr: 3.2 GHz */ - <587500 12800000>, - /* low (latency critical): 18-60 Mbps ddr: 451.2 MHz */ - <7500 2188800>; + /* ddr_type = 8(LPDDR5) */ + + ddr_cfg@0 { + ddr_type = <8>; + + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ + <2250 800000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ + <7500 800000>, + /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ + <30000 800000>, + /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ + <100000 800000>, + /* very high: > 1200 Mbps snoc/anoc: 200 Mhz */ + <175000 1600000>, + /* ultra high: DBS mode snoc/anoc: 200 Mhz */ + <312500 1600000>, + /* super high: DBS mode snoc/anoc: 403 Mhz */ + <587500 3224000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ + <7500 1600000>, + + /** ICC Path 2 **/ + <0 0>, + /* idle: 0-18 Mbps ddr: 547 MHz */ + <2250 2500800>, + /* low: 18-60 Mbps ddr: 547 MHz */ + <7500 2500800>, + /* medium: 60-240 Mbps ddr: 547 MHz */ + <30000 2500800>, + /* high: 240-1200 Mbps ddr: 547 MHz */ + <100000 2500800>, + /* very high: > 1200 Mbps ddr: 1555 MHz */ + <175000 7108800>, + /* ultra high: DBS mode ddr: 2092 MHz */ + <312500 9566400>, + /* super high: DBS mode ddr: 3.2 GHz */ + <587500 14569200>, + /* low (latency critical): 18-60 Mbps ddr: 547 MHz */ + <7500 2500800>; + }; + + /* ddr_type = 7(LPDDR4) */ + + ddr_cfg@1 { + ddr_type = <7>; + + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ + <2250 800000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ + <7500 800000>, + /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ + <30000 800000>, + /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ + <100000 800000>, + /* very high: > 1200 Mbps snoc/anoc: 200 Mhz */ + <175000 1600000>, + /* ultra high: DBS mode snoc/anoc: 200 Mhz */ + <312500 1600000>, + /* super high: DBS mode snoc/anoc: 403 Mhz */ + <587500 3224000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ + <7500 1600000>, + + /** ICC Path 2 **/ + <0 0>, + /* idle: 0-18 Mbps ddr: 547 MHz */ + <2250 2500800>, + /* low: 18-60 Mbps ddr: 547 MHz */ + <7500 2500800>, + /* medium: 60-240 Mbps ddr: 547 MHz */ + <30000 2500800>, + /* high: 240-1200 Mbps ddr: 547 MHz */ + <100000 2500800>, + /* very high: > 1200 Mbps ddr: 1555 MHz */ + <175000 7108800>, + /* ultra high: DBS mode ddr: 2092 MHz */ + <312500 9566400>, + /* super high: DBS mode ddr: 3.2 GHz */ + <587500 14569200>, + /* low (latency critical): 18-60 Mbps ddr: 547 MHz */ + <7500 2500800>; + }; icnss_cdev_apss: qcom,icnss_cdev1 { #cooling-cells = <2>; diff --git a/tuna-wcn7750.dtsi b/tuna-wcn7750.dtsi index ba7a33f3..4d103503 100644 --- a/tuna-wcn7750.dtsi +++ b/tuna-wcn7750.dtsi @@ -139,44 +139,51 @@ qcom,icc-path-count = <2>; qcom,bus-bw-cfg-count = <9>; - qcom,bus-bw-cfg = - /** ICC Path 1 **/ - <0 0>, /* no vote */ - /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ - <2250 400000>, - /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ - <7500 400000>, - /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ - <30000 400000>, - /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ - <100000 400000>, - /* very high: > 1200 Mbps snoc/anoc: 200 Mhz */ - <175000 800000>, - /* ultra high: DBS mode snoc/anoc: 200 Mhz */ - <312500 800000>, - /* super high: DBS mode snoc/anoc: 403 Mhz */ - <587500 1612000>, - /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ - <7500 800000>, - /** ICC Path 2 **/ - <0 0>, - /* idle: 0-18 Mbps ddr: 547 MHz */ - <2250 2188800>, - /* low: 18-60 Mbps ddr: 547 MHz */ - <7500 2188800>, - /* medium: 60-240 Mbps ddr: 547 MHz */ - <30000 2188800>, - /* high: 240-1200 Mbps ddr: 547 MHz */ - <100000 2188800>, - /* very high: > 1200 Mbps ddr: 1555 MHz */ - <175000 6220800>, - /* ultra high: DBS mode ddr: 2092 MHz */ - <312500 8371200>, - /* super high: DBS mode ddr: 3.2 GHz */ - <587500 14745600>, - /* low (latency critical): 18-60 Mbps ddr: 2092 MHz */ - <7500 8371200>; + /* ddr_type = 8(LPDDR5) */ + + ddr_cfg@0 { + ddr_type = <8>; + + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ + <2250 400000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ + <7500 400000>, + /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ + <30000 400000>, + /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ + <100000 400000>, + /* very high: > 1200 Mbps snoc/anoc: 200 Mhz */ + <175000 800000>, + /* ultra high: DBS mode snoc/anoc: 200 Mhz */ + <312500 800000>, + /* super high: DBS mode snoc/anoc: 403 Mhz */ + <587500 1612000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ + <7500 800000>, + + /** ICC Path 2 **/ + <0 0>, + /* idle: 0-18 Mbps ddr: 547 MHz */ + <2250 2188800>, + /* low: 18-60 Mbps ddr: 547 MHz */ + <7500 2188800>, + /* medium: 60-240 Mbps ddr: 547 MHz */ + <30000 2188800>, + /* high: 240-1200 Mbps ddr: 547 MHz */ + <100000 2188800>, + /* very high: > 1200 Mbps ddr: 1555 MHz */ + <175000 6220800>, + /* ultra high: DBS mode ddr: 2092 MHz */ + <312500 8371200>, + /* super high: DBS mode ddr: 3.2 GHz */ + <587500 14745600>, + /* low (latency critical): 18-60 Mbps ddr: 2092 MHz */ + <7500 8371200>; + }; icnss_cdev_apss: qcom,icnss_cdev1 { #cooling-cells = <2>;