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ARM: dts: msm: Add CPUCP/SCMI node for Tuna

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Add device nodes for the cpucp mailbox, cpucp logs,
and SCMI nodes for Tuna.

Change-Id: If028d941d4cb812402a6617908d1bfe7ffbb6108
Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
This commit is contained in:
Shivnandan Kumar
2024-09-05 20:19:44 +05:30
parent 218d7537b5
commit b1c4c22e5c
1 changed files with 58 additions and 0 deletions
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58
qcom/tuna.dtsi
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@@ -1641,6 +1641,64 @@
status = "disabled";
};
};
mmio_sram: mmio-sram@17D09400 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "mmio-sram";
reg = <0x0 0x17D09400 0x0 0x400>;
ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>;
cpu_scp_lpri: scmi-shmem@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x17D09400 0x0 0x400>;
};
};
cpucp: qcom,cpucp@17400000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,cpucp";
reg = <0x17d90000 0x2000>,
<0x17400000 0x10>;
reg-names = "rx", "tx";
#mbox-cells = <1>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
scmi: qcom,scmi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,scmi";
mboxes = <&cpucp 0>;
mbox-names = "tx";
shmem = <&cpu_scp_lpri>;
scmi_qcom: protocol@80 {
reg = <0x80>;
#clock-cells = <1>;
};
};
cpucp_log: qcom,cpucp_log@d8140000 {
compatible = "qcom,cpucp-log";
reg = <0x81200000 0x10000>, <0x81210000 0x10000>;
mboxes = <&cpucp 1>;
};
qcom_c1dcvs: qcom,c1dcvs {
compatible = "qcom,c1dcvs-v2";
};
qcom_dynpf: qcom,dynpf {
compatible = "qcom,dynpf";
};
qcom_cpufreq_stats: qcom,cpufreq_stats {
compatible = "qcom,cpufreq-stats-v2";
};
};
#include "tuna-gdsc.dtsi"