Add 'qcom/dsp/' from LA.VENDOR.15.4.0.r1-17000-pakala.0 of https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/dsp-devicetree
git-subtree-dir: qcom/dsp git-subtree-mainline:1d4a80d339git-subtree-split:bb472cc1cf
This commit is contained in:
kmiit
42
qcom/dsp/Kbuild
Executable file
42
qcom/dsp/Kbuild
Executable file
@@ -0,0 +1,42 @@
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ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
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ifeq ($(CONFIG_ARCH_QTI_VM), y)
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dtbo-y += pineapple/pineapple-dsp-trustedvm.dtbo
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else
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dtbo-y += pineapple/pineapple-dsp.dtbo
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endif
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endif
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ifeq ($(CONFIG_ARCH_BLAIR), y)
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dtbo-y += blair/blair-dsp.dtbo
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endif
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ifeq ($(CONFIG_ARCH_SUN), y)
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ifeq ($(CONFIG_ARCH_QTI_VM), y)
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dtbo-y += sun/sun-dsp-trustedvm.dtbo
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else
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dtbo-y += sun/sun-dsp.dtbo
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endif
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endif
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ifeq ($(CONFIG_ARCH_TUNA), y)
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dtbo-y += tuna/tuna-dsp.dtbo
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endif
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ifeq ($(CONFIG_ARCH_KERA), y)
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dtbo-y += kera/kera-dsp.dtbo
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endif
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ifeq ($(CONFIG_ARCH_MONACO), y)
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dtbo-y += monaco/monaco-dsp.dtbo
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endif
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ifeq ($(CONFIG_ARCH_PARROT), y)
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dtbo-y += parrot/parrot-dsp.dtbo
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endif
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ifeq ($(CONFIG_ARCH_RAVELIN), y)
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dtbo-y += ravelin/ravelin-dsp.dtbo
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endif
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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9
qcom/dsp/Makefile
Normal file
9
qcom/dsp/Makefile
Normal file
@@ -0,0 +1,9 @@
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KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
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all: dtbs
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
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%:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
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16
qcom/dsp/bindings/msm-cdsp-loader.txt
Normal file
16
qcom/dsp/bindings/msm-cdsp-loader.txt
Normal file
@@ -0,0 +1,16 @@
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Qualcomm Technologies, Inc. CDSP Loader Driver
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msm-cdsp-loader driver implements a mechanism to load the Compute DSP firmware images.
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Required properties:
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||||
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- compatible: This must be "qcom,msm-cdsp-loader".
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- qcom,proc-img-to-load: CDSP firmware name, must be "cdsp".
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Example:
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The following is an example:
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qcom,msm-cdsp-loader {
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compatible = "qcom,cdsp-loader";
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qcom,proc-img-to-load = "cdsp";
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};
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105
qcom/dsp/bindings/msm-fastrpc.txt
Normal file
105
qcom/dsp/bindings/msm-fastrpc.txt
Normal file
@@ -0,0 +1,105 @@
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Qualcomm Technologies, Inc. FastRPC Driver
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||||
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The MSM FastRPC driver implements an IPC (Inter-Processor Communication)
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mechanism that allows for clients to transparently make remote method
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invocations across DSP and APPS boundaries. This enables developers
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to offload tasks to the DSP and free up the application processor for
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other tasks.
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Required properties:
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- compatible : Must be one of "qcom,msm-fastrpc-adsp" or "qcom,msm-fastrpc-compute"
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Optional properties:
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- qcom,rpc-latency-us : FastRPC QoS latency vote
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- qcom,adsp-remoteheap-vmid : FastRPC remote heap VMID list
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- qcom,secure-context-bank : Bool indicating secure FastRPC context bank.
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- qcom,fastrpc-legacy-remote-heap : Bool indicating hypervisor is not supported.
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- qcom,fastrpc-adsp-audio-pdr : Flag to enable ADSP Audio PDR
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- qcom,secure-domains : FastRPC secure domain configuration
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- qcom,fastrpc-adsp-sensors-pdr : Flag to enable Sensors PDR
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- qcom,single-core-latency-vote : Limit FastRPC PM QoS to only vote for 1
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lowest capacity core
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||||
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Optional subnodes:
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- qcom,msm_fastrpc_compute_cb : Child nodes representing the compute context banks
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- qcom,msm-fastrpc-rpmsg : Child node for rpmsg instead of glink for IPC
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Subnode Required properties:
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- compatible : Must be "qcom,msm-fastrpc-compute-cb"
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- label : Label describing the channel this context bank belongs to
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- iommus : A list of phandle and IOMMU specifier pairs that describe the
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IOMMU master interfaces of the device
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- dma-coherent : A flag marking a context bank as I/O coherent
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- shared-cb : A value indicating how many fastrpc sessions can share a
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context bank
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- pd-type : A value indicating remote subsystem proess type
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- alloc-size-range: A pair values indicating the allocation size range
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of context bank
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Example:
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qcom,msm_fastrpc {
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compatible = "qcom,msm-fastrpc-compute";
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qcom,fastrpc-rpmsg;
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qcom,rpc-latency-us = <235>;
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qcom,adsp-remoteheap-vmid = <22 37>;
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qcom,fastrpc-adsp-sensors-pdr;
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qcom,msm_fastrpc_rpmsg {
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compatible = "qcom,msm-fastrpc-rpmsg";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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intents = <0x64 64>;
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};
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qcom,msm_fastrpc_compute_cb_1 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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qcom,secure-context-bank;
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iommus = <&apps_smmu 0x1401 0x0>;
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb_2 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "sdsprpc-smd";
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iommus = <&apps_smmu 0x1402 0x0>;
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shared-cb = <5>;
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};
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};
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Legacy SMMU v1/v2:
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Required properties:
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- compatible : Must be "qcom,msm-fastprc-legacy-compute-cb"
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Required subnode:
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- qcom,msm_fastrpc_compute_cb : Child nodes representing the compute context
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banks
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Required subnode properties:
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- qcom,adsp-shared-phandle : phandle that describe the context bank handle
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- qcom,adsp-shared-sids : A list of SID associated with the context bank
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- qcom,virtual-addr-pool : Virtual address range that the context bank
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will be using
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Example:
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qcom,adsprpc_domains {
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compatible = "qcom,msm-fastrpc-legacy-compute-cb";
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qcom,msm_fastrpc_compute_cb {
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qcom,adsp-shared-phandle = <&adsp_shared>;
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qcom,adsp-shared-sids = <0x8 0x9>;
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qcom,virtual-addr-pool = <0x80000000 0x7FFFFFFF>;
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};
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};
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Remote Heap:
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Required properties:
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- compatible : Must be "qcom,msm-adsprpc-mem-region"
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- memory-region : CMA region which is owned by this device
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- restrict-access : Blocking vote for hyp_assign_phys function call
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Example:
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qcom,adsprpc-mem {
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compatible = "qcom,msm-adsprpc-mem-region";
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memory-region = <&adsp_mem>;
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restrict-access;
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};
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11
qcom/dsp/blair/blair-dsp.dts
Normal file
11
qcom/dsp/blair/blair-dsp.dts
Normal file
@@ -0,0 +1,11 @@
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/dts-v1/;
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/plugin/;
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#include "blair-dsp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. blair v1 SoC";
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compatible = "qcom,blair";
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qcom,msm-id = <507 0x10000>, <578 0x10000>;
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qcom,board-id = <0 0>;
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};
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132
qcom/dsp/blair/blair-dsp.dtsi
Normal file
132
qcom/dsp/blair/blair-dsp.dtsi
Normal file
@@ -0,0 +1,132 @@
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&remoteproc_adsp_glink {
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qcom,fastrpc {
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compatible = "qcom,fastrpc";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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qcom,intents = <0x64 64>;
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label = "adsp";
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memory-region = <&adsp_mem_heap>;
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qcom,vmids = <22 37>;
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compute-cb@1 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <3>;
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iommus = <&apps_smmu 0x00A3 0x0000>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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compute-cb@2 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <4>;
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iommus = <&apps_smmu 0x00A4 0x0000>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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compute-cb@3 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <5>;
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iommus = <&apps_smmu 0x00A5 0x0000>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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qcom,nsessions = <8>;
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dma-coherent;
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};
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compute-cb@4 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <6>;
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iommus = <&apps_smmu 0x00A6 0x0000>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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compute-cb@5 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <7>;
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iommus = <&apps_smmu 0x00A7 0x0000>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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};
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};
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&remoteproc_cdsp_glink {
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qcom,fastrpc {
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compatible = "qcom,fastrpc";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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qcom,intents = <0x64 64>;
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label = "cdsp";
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qcom,fastrpc-gids = <2908>;
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qcom,rpc-latency-us = <611>;
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compute-cb@1 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <1>;
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iommus = <&apps_smmu 0x1001 0x0000>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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compute-cb@2 {
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compatible = "qcom,fastrpc-compute-cb";
|
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reg = <2>;
|
||||
iommus = <&apps_smmu 0x1002 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1003 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1004 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1005 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1006 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
compute-cb@9 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <9>;
|
||||
qcom,secure-context-bank;
|
||||
iommus = <&apps_smmu 0x1009 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
};
|
||||
16
qcom/dsp/kera/kera-dsp.dts
Normal file
16
qcom/dsp/kera/kera-dsp.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-dsp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera v1 SoC";
|
||||
compatible = "qcom,kera";
|
||||
qcom,msm-id = <659 0x10000>, <686 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
241
qcom/dsp/kera/kera-dsp.dtsi
Normal file
241
qcom/dsp/kera/kera-dsp.dtsi
Normal file
@@ -0,0 +1,241 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&remoteproc_adsp_glink {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x181 64>;
|
||||
qcom,ch-sched-rt;
|
||||
qcom,cb-irq;
|
||||
label = "adsp";
|
||||
memory-region = <&adsp_mem_heap>;
|
||||
qcom,vmids = <22 37>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1003 0x0080>,
|
||||
<&apps_smmu 0x1043 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1004 0x0080>,
|
||||
<&apps_smmu 0x1044 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,nsessions = <8>;
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <3>; /* SENSORS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1005 0x0080>,
|
||||
<&apps_smmu 0x1045 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <2>; /* AUDIO_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1006 0x0080>,
|
||||
<&apps_smmu 0x1046 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <5>; /* OIS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x1007 0x0040>,
|
||||
<&apps_smmu 0x1067 0x0000>,
|
||||
<&apps_smmu 0x1087 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x1008 0x0080>,
|
||||
<&apps_smmu 0x1048 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_cdsp_glink {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x3fA 64>;
|
||||
qcom,ch-sched-rt;
|
||||
qcom,cb-irq;
|
||||
label = "cdsp";
|
||||
qcom,fastrpc-gids = <2908>;
|
||||
qcom,rpc-latency-us = <235>;
|
||||
qcom,single-core-latency-vote;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&apps_smmu 0x0C01 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&apps_smmu 0x0C02 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x0C03 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x0C04 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x0C05 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x4000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x0C06 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x4000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x0C07 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x1000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x0C08 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x1000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@9 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <9>;
|
||||
qcom,secure-context-bank;
|
||||
iommus = <&apps_smmu 0x0C09 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
||||
qcom,nsessions = <3>;
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <6>; /* CPZ_USERPD */
|
||||
};
|
||||
|
||||
compute-cb@10 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <12>;
|
||||
iommus = <&apps_smmu 0x0C0C 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@11 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <13>;
|
||||
iommus = <&apps_smmu 0x0C0D 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@12 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <14>;
|
||||
iommus = <&apps_smmu 0x0C0E 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
};
|
||||
};
|
||||
15
qcom/dsp/monaco/monaco-dsp.dts
Normal file
15
qcom/dsp/monaco/monaco-dsp.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "monaco-dsp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Monaco SoC";
|
||||
compatible = "qcom,monaco";
|
||||
qcom,msm-id = <486 0x10000>, <517 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
60
qcom/dsp/monaco/monaco-dsp.dtsi
Normal file
60
qcom/dsp/monaco/monaco-dsp.dtsi
Normal file
@@ -0,0 +1,60 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&glink_edge {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
label = "adsp";
|
||||
memory-region = <&adsp_mem>;
|
||||
qcom,vmids = <22 37>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x01C3 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable";
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x01C4 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable";
|
||||
qcom,nsessions = <5>;
|
||||
pd-type = <3>; /* SENSORS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x01C5 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable";
|
||||
pd-type = <2>; /* AUDIO_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x01C6 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable";
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x01C7 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable";
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
};
|
||||
};
|
||||
15
qcom/dsp/parrot/parrot-dsp.dts
Normal file
15
qcom/dsp/parrot/parrot-dsp.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "parrot-dsp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. parrot v1 SoC";
|
||||
compatible = "qcom,parrot";
|
||||
qcom,msm-id = <537 0x10000>, <613 0x10000>, <663 0x10000>, <633 0x10000>, <583 0x10000>, <631 0x10000>, <634 0x10000>, <638 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
234
qcom/dsp/parrot/parrot-dsp.dtsi
Normal file
234
qcom/dsp/parrot/parrot-dsp.dtsi
Normal file
@@ -0,0 +1,234 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
&glink_edge {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
label = "adsp";
|
||||
memory-region = <&adsp_mem_heap>;
|
||||
qcom,vmids = <22 37>;
|
||||
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1803 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <1>;
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1804 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <2>;
|
||||
};
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1805 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,nsessions = <5>;
|
||||
pd-type = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_cdsp_glink {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
label = "cdsp";
|
||||
qcom,fastrpc-gids = <2908>;
|
||||
qcom,rpc-latency-us = <235>;
|
||||
|
||||
qcom,qos-cores = <0 1 2 3>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1401 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
pd-type = <1>;
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1402 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1403 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1404 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1405 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1406 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1407 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1408 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
};
|
||||
|
||||
compute-cb@9 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <9>;
|
||||
label = "cdsprpc-smd";
|
||||
qcom,secure-context-bank;
|
||||
iommus = <&apps_smmu 0x1409 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,iommu-vmid = <0xA>;
|
||||
dma-coherent;
|
||||
|
||||
pd-type = <6>;
|
||||
};
|
||||
|
||||
compute-cb@10 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <11>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x140B 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@11 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <12>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x140C 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@12 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <13>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x140D 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@13 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <14>;
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0x140E 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
|
||||
qcom,iova-max-align-shift = <9>;
|
||||
pd-type = <7>;
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
};
|
||||
};
|
||||
10
qcom/dsp/pineapple/pineapple-dsp-trustedvm.dts
Normal file
10
qcom/dsp/pineapple/pineapple-dsp-trustedvm.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-dsp-trustedvm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple - TrustedVM";
|
||||
compatible = "qcom,pineapple";
|
||||
qcom,msm-id = <557 0x10000>;
|
||||
};
|
||||
33
qcom/dsp/pineapple/pineapple-dsp-trustedvm.dtsi
Normal file
33
qcom/dsp/pineapple/pineapple-dsp-trustedvm.dtsi
Normal file
@@ -0,0 +1,33 @@
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
&soc {
|
||||
msm_fastrpc: qcom,msm_fastrpc {
|
||||
compatible = "qcom,msm-fastrpc-compute";
|
||||
qcom,rpc-latency-us = <235>;
|
||||
qcom,fastrpc-gids = <2908>;
|
||||
qcom,qos-cores = <0 1 2 3>;
|
||||
|
||||
fastrpc_compute_cb1: qcom,msm_fastrpc_compute_cb1 {
|
||||
compatible = "qcom,msm-fastrpc-compute-cb";
|
||||
label = "cdsprpc-smd";
|
||||
iommus = <&apps_smmu 0xC0B 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qrtr-gen-pool = <&fastrpc_compute_cb1>;
|
||||
frpc-gen-addr-pool = <0x8000 0x9000>;
|
||||
pd-type = <4>; /* SECURE_STATICPD */
|
||||
};
|
||||
};
|
||||
|
||||
qrtr-genpool {
|
||||
compatible = "qcom,qrtr-genpool";
|
||||
gen-pool = <&fastrpc_compute_cb1>;
|
||||
interrupt-parent = <&ipcc_mproc_ns1>;
|
||||
interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
|
||||
<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
|
||||
};
|
||||
};
|
||||
15
qcom/dsp/pineapple/pineapple-dsp.dts
Normal file
15
qcom/dsp/pineapple/pineapple-dsp.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
||||
#include "pineapple-dsp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. pineapple v1 SoC";
|
||||
compatible = "qcom,pineapple";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
225
qcom/dsp/pineapple/pineapple-dsp.dtsi
Normal file
225
qcom/dsp/pineapple/pineapple-dsp.dtsi
Normal file
@@ -0,0 +1,225 @@
|
||||
&glink_edge {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
label = "adsp";
|
||||
memory-region = <&adsp_mem_heap>;
|
||||
qcom,vmids = <22 37>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1003 0x0080>,
|
||||
<&apps_smmu 0x1043 0x0020>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1004 0x0080>,
|
||||
<&apps_smmu 0x1044 0x0020>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,nsessions = <8>;
|
||||
dma-coherent;
|
||||
pd-type = <3>; /* SENSORS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1005 0x0080>,
|
||||
<&apps_smmu 0x1045 0x0020>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <2>; /* AUDIO_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1006 0x0080>,
|
||||
<&apps_smmu 0x1046 0x0020>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x1007 0x0040>,
|
||||
<&apps_smmu 0x1067 0x0000>,
|
||||
<&apps_smmu 0x1087 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_cdsp_glink {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
label = "cdsp";
|
||||
qcom,fastrpc-gids = <2908>;
|
||||
qcom,rpc-latency-us = <235>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&apps_smmu 0x1961 0x0000>,
|
||||
<&apps_smmu 0x0C01 0x0020>,
|
||||
<&apps_smmu 0x19C1 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&apps_smmu 0x1962 0x0000>,
|
||||
<&apps_smmu 0x0C02 0x0020>,
|
||||
<&apps_smmu 0x19C2 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1963 0x0000>,
|
||||
<&apps_smmu 0x0C03 0x0020>,
|
||||
<&apps_smmu 0x19C3 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1964 0x0000>,
|
||||
<&apps_smmu 0x0C04 0x0020>,
|
||||
<&apps_smmu 0x19C4 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1965 0x0000>,
|
||||
<&apps_smmu 0x0C05 0x0020>,
|
||||
<&apps_smmu 0x19C5 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1966 0x0000>,
|
||||
<&apps_smmu 0x0C06 0x0020>,
|
||||
<&apps_smmu 0x19C6 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x1967 0x0000>,
|
||||
<&apps_smmu 0x0C07 0x0020>,
|
||||
<&apps_smmu 0x19C7 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x1968 0x0000>,
|
||||
<&apps_smmu 0x0C08 0x0020>,
|
||||
<&apps_smmu 0x19C8 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@9 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <9>;
|
||||
qcom,secure-context-bank;
|
||||
iommus = <&apps_smmu 0x1969 0x0000>,
|
||||
<&apps_smmu 0x0C09 0x0020>,
|
||||
<&apps_smmu 0x19C9 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
||||
qcom,nsessions = <3>;
|
||||
dma-coherent;
|
||||
pd-type = <6>; /* CPZ_USERPD */
|
||||
};
|
||||
|
||||
compute-cb@10 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <12>;
|
||||
iommus = <&apps_smmu 0x196C 0x0000>,
|
||||
<&apps_smmu 0x0C0C 0x0020>,
|
||||
<&apps_smmu 0x19CC 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@11 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <13>;
|
||||
iommus = <&apps_smmu 0x196D 0x0000>,
|
||||
<&apps_smmu 0x0C0D 0x0020>,
|
||||
<&apps_smmu 0x19CD 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@12 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <14>;
|
||||
iommus = <&apps_smmu 0x196E 0x0000>,
|
||||
<&apps_smmu 0x0C0E 0x0020>,
|
||||
<&apps_smmu 0x19CE 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
};
|
||||
};
|
||||
15
qcom/dsp/ravelin/ravelin-dsp.dts
Executable file
15
qcom/dsp/ravelin/ravelin-dsp.dts
Executable file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "ravelin-dsp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. ravelin v1 SoC";
|
||||
compatible = "qcom,ravelin";
|
||||
qcom,msm-id = <568 0x10000>, <602 0x10000>, <654 0x10000>, <653 0x10000>;
|
||||
qcom,board-id = <0 0>, <0x1000B 0>, <0x1000B 0x600>, <33 0>, <34 0>, <34 0x601>, <34 2>;
|
||||
};
|
||||
48
qcom/dsp/ravelin/ravelin-dsp.dtsi
Executable file
48
qcom/dsp/ravelin/ravelin-dsp.dtsi
Executable file
@@ -0,0 +1,48 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
&glink_edge {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
label = "adsp";
|
||||
memory-region = <&adsp_mem_heap>;
|
||||
qcom,vmids = <22 37>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1003 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1004 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,nsessions = <4>;
|
||||
pd-type = <3>; /* SENSORS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1005 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
pd-type = <2>; /* AUDIO_STATICPD */
|
||||
};
|
||||
};
|
||||
};
|
||||
18
qcom/dsp/sun/sun-dsp-trustedvm.dts
Normal file
18
qcom/dsp/sun/sun-dsp-trustedvm.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-dsp-trustedvm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun - TrustedVM";
|
||||
compatible = "qcom,sun";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>, <655 0x10000>,
|
||||
<681 0x10000>, <694 0x10000>,<659 0x10000>, <686 0x10000>;
|
||||
};
|
||||
32
qcom/dsp/sun/sun-dsp-trustedvm.dtsi
Normal file
32
qcom/dsp/sun/sun-dsp-trustedvm.dtsi
Normal file
@@ -0,0 +1,32 @@
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
&soc {
|
||||
fastrpc_gen_pool_region: fastrpc_gen_pool_region {
|
||||
iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>;
|
||||
};
|
||||
|
||||
fastrpc_compute_cb1: compute-cb@13 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <11>;
|
||||
iommus = <&apps_smmu 0xC0B 0x0>;
|
||||
memory-region = <&fastrpc_gen_pool_region>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
qrtr-gen-pool = <&fastrpc_compute_cb1>;
|
||||
frpc-gen-addr-pool = <0x8000 0x9000>;
|
||||
pd-type = <4>; /* SECURE_STATICPD */
|
||||
};
|
||||
|
||||
qrtr-genpool {
|
||||
compatible = "qcom,qrtr-genpool";
|
||||
gen-pool = <&fastrpc_compute_cb1>;
|
||||
interrupt-parent = <&ipcc_mproc_ns1>;
|
||||
interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
|
||||
<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
|
||||
};
|
||||
};
|
||||
13
qcom/dsp/sun/sun-dsp.dts
Normal file
13
qcom/dsp/sun/sun-dsp.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-dsp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. sun v1 SoC";
|
||||
compatible = "qcom,sun";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
267
qcom/dsp/sun/sun-dsp.dtsi
Normal file
267
qcom/dsp/sun/sun-dsp.dtsi
Normal file
@@ -0,0 +1,267 @@
|
||||
&remoteproc_adsp_glink {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x181 64>;
|
||||
label = "adsp";
|
||||
memory-region = <&adsp_mem_heap>;
|
||||
qcom,vmids = <22 37>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1003 0x0080>,
|
||||
<&apps_smmu 0x1043 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1004 0x0080>,
|
||||
<&apps_smmu 0x1044 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,nsessions = <8>;
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <3>; /* SENSORS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1005 0x0080>,
|
||||
<&apps_smmu 0x1045 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <2>; /* AUDIO_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1006 0x0080>,
|
||||
<&apps_smmu 0x1046 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <5>; /* OIS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x1007 0x0040>,
|
||||
<&apps_smmu 0x1067 0x0000>,
|
||||
<&apps_smmu 0x1087 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x1008 0x0080>,
|
||||
<&apps_smmu 0x1048 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_cdsp_glink {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x3fA 64>;
|
||||
label = "cdsp";
|
||||
qcom,fastrpc-gids = <2908>;
|
||||
qcom,rpc-latency-us = <235>;
|
||||
qcom,single-core-latency-vote;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&apps_smmu 0x19C1 0x0000>,
|
||||
<&apps_smmu 0x0C21 0x0000>,
|
||||
<&apps_smmu 0x0C01 0x0040>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&apps_smmu 0x1962 0x0000>,
|
||||
<&apps_smmu 0x0C02 0x0020>,
|
||||
<&apps_smmu 0x0C42 0x0000>,
|
||||
<&apps_smmu 0x19C2 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1963 0x0000>,
|
||||
<&apps_smmu 0x0C23 0x0000>,
|
||||
<&apps_smmu 0x0C03 0x0040>,
|
||||
<&apps_smmu 0x19C3 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1964 0x0000>,
|
||||
<&apps_smmu 0x0C24 0x0000>,
|
||||
<&apps_smmu 0x0C04 0x0040>,
|
||||
<&apps_smmu 0x19C4 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1965 0x0000>,
|
||||
<&apps_smmu 0x0C25 0x0000>,
|
||||
<&apps_smmu 0x0C05 0x0040>,
|
||||
<&apps_smmu 0x19C5 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x4000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1966 0x0000>,
|
||||
<&apps_smmu 0x0C06 0x0020>,
|
||||
<&apps_smmu 0x0C46 0x0000>,
|
||||
<&apps_smmu 0x19C6 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x4000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x1967 0x0000>,
|
||||
<&apps_smmu 0x0C27 0x0000>,
|
||||
<&apps_smmu 0x0C07 0x0040>,
|
||||
<&apps_smmu 0x19C7 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x1000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x1968 0x0000>,
|
||||
<&apps_smmu 0x0C08 0x0020>,
|
||||
<&apps_smmu 0x0C48 0x0000>,
|
||||
<&apps_smmu 0x19C8 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x1000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@9 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <9>;
|
||||
qcom,secure-context-bank;
|
||||
iommus = <&apps_smmu 0x1969 0x0000>,
|
||||
<&apps_smmu 0x0C29 0x0000>,
|
||||
<&apps_smmu 0x0C09 0x0040>,
|
||||
<&apps_smmu 0x19C9 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
||||
qcom,nsessions = <3>;
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <6>; /* CPZ_USERPD */
|
||||
};
|
||||
|
||||
compute-cb@10 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <12>;
|
||||
iommus = <&apps_smmu 0x196C 0x0000>,
|
||||
<&apps_smmu 0x0C2C 0x0000>,
|
||||
<&apps_smmu 0x0C0C 0x0040>,
|
||||
<&apps_smmu 0x19CC 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@11 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <13>;
|
||||
iommus = <&apps_smmu 0x196D 0x0000>,
|
||||
<&apps_smmu 0x0C0D 0x0020>,
|
||||
<&apps_smmu 0x0C2E 0x0000>,
|
||||
<&apps_smmu 0x0C4D 0x0000>,
|
||||
<&apps_smmu 0x19CD 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@12 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <14>;
|
||||
iommus = <&apps_smmu 0x196E 0x0000>,
|
||||
<&apps_smmu 0x0C0E 0x0040>,
|
||||
<&apps_smmu 0x19CE 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
};
|
||||
};
|
||||
16
qcom/dsp/tuna/tuna-dsp.dts
Normal file
16
qcom/dsp/tuna/tuna-dsp.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-dsp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna v1 SoC";
|
||||
compatible = "qcom,tuna";
|
||||
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
241
qcom/dsp/tuna/tuna-dsp.dtsi
Normal file
241
qcom/dsp/tuna/tuna-dsp.dtsi
Normal file
@@ -0,0 +1,241 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&remoteproc_adsp_glink {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x181 64>;
|
||||
qcom,ch-sched-rt;
|
||||
qcom,cb-irq;
|
||||
label = "adsp";
|
||||
memory-region = <&adsp_mem_heap>;
|
||||
qcom,vmids = <22 37>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1003 0x0080>,
|
||||
<&apps_smmu 0x1043 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1004 0x0080>,
|
||||
<&apps_smmu 0x1044 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,nsessions = <8>;
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <3>; /* SENSORS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1005 0x0080>,
|
||||
<&apps_smmu 0x1045 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <2>; /* AUDIO_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1006 0x0080>,
|
||||
<&apps_smmu 0x1046 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <5>; /* OIS_STATICPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x1007 0x0040>,
|
||||
<&apps_smmu 0x1067 0x0000>,
|
||||
<&apps_smmu 0x1087 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x1008 0x0080>,
|
||||
<&apps_smmu 0x1048 0x0020>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_cdsp_glink {
|
||||
qcom,fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x3fA 64>;
|
||||
qcom,ch-sched-rt;
|
||||
qcom,cb-irq;
|
||||
label = "cdsp";
|
||||
qcom,fastrpc-gids = <2908>;
|
||||
qcom,rpc-latency-us = <235>;
|
||||
qcom,single-core-latency-vote;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&apps_smmu 0x0C01 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <1>; /* ROOT_PD */
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&apps_smmu 0x0C02 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x0C03 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x0C04 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <7>; /* USERPD */
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x0C05 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x4000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x0C06 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x4000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x0C07 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x1000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x0C08 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x1000000 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@9 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <9>;
|
||||
qcom,secure-context-bank;
|
||||
iommus = <&apps_smmu 0x0C09 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
||||
qcom,nsessions = <3>;
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
pd-type = <6>; /* CPZ_USERPD */
|
||||
};
|
||||
|
||||
compute-cb@10 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <12>;
|
||||
iommus = <&apps_smmu 0x0C0C 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@11 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <13>;
|
||||
iommus = <&apps_smmu 0x0C0D 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
|
||||
compute-cb@12 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <14>;
|
||||
iommus = <&apps_smmu 0x0C0E 0x0000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
qcom,iova-best-fit;
|
||||
qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
|
||||
pd-type = <9>; /* USER_UNSIGNEDPD_POOL */
|
||||
alloc-size-range = <0x0 0xFFFFFFFF>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user