From 6f17fc6154307afde2b3223d7133c5ce6bf54336 Mon Sep 17 00:00:00 2001 From: Gerrit SelfHelp Service Account Date: Tue, 23 Jan 2024 23:34:08 -0800 Subject: [PATCH 01/41] Initial empty repository From 68b5b873640e7f30138bd46acffb5fb871fe7e75 Mon Sep 17 00:00:00 2001 From: Anirudh Raghavendra Date: Fri, 26 Jan 2024 16:59:41 -0800 Subject: [PATCH 02/41] arm64: dts: qcom: sun: Add devicetree files to opensource project dsp-devicetree files are currently a part of a proprietary project and there is a requirement to move them to an opensource project. This change adds the required files to opensource project with the compilation disabled until the files are merged. Change-Id: I9838c13afbcadec7c5a18bab1ccf867e32070cea Signed-off-by: Anirudh Raghavendra --- Kbuild | 15 +++ Makefile | 9 ++ bindings/msm-cdsp-loader.txt | 16 +++ bindings/msm-fastrpc.txt | 100 ++++++++++++++ niobe/niobe-dsp.dts | 11 ++ niobe/niobe-dsp.dtsi | 224 +++++++++++++++++++++++++++++++ sun/sun-dsp-trustedvm.dts | 10 ++ sun/sun-dsp-trustedvm.dtsi | 26 ++++ sun/sun-dsp.dts | 10 ++ sun/sun-dsp.dtsi | 248 +++++++++++++++++++++++++++++++++++ 10 files changed, 669 insertions(+) create mode 100644 Kbuild create mode 100644 Makefile create mode 100644 bindings/msm-cdsp-loader.txt create mode 100644 bindings/msm-fastrpc.txt create mode 100644 niobe/niobe-dsp.dts create mode 100644 niobe/niobe-dsp.dtsi create mode 100644 sun/sun-dsp-trustedvm.dts create mode 100644 sun/sun-dsp-trustedvm.dtsi create mode 100644 sun/sun-dsp.dts create mode 100644 sun/sun-dsp.dtsi diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..199cee42 --- /dev/null +++ b/Kbuild @@ -0,0 +1,15 @@ +#ifeq ($(CONFIG_ARCH_SUN), y) +#ifeq ($(CONFIG_ARCH_QTI_VM), y) +#dtbo-y += sun-dsp-trustedvm.dtbo +#else +#dtbo-y += sun-dsp.dtbo +#endif +#endif + +#ifeq ($(CONFIG_ARCH_NIOBE), y) +#dtbo-y += niobe-dsp.dtbo +#endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..b1e0dfe9 --- /dev/null +++ b/Makefile @@ -0,0 +1,9 @@ +KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/bindings/msm-cdsp-loader.txt b/bindings/msm-cdsp-loader.txt new file mode 100644 index 00000000..8e0d4f25 --- /dev/null +++ b/bindings/msm-cdsp-loader.txt @@ -0,0 +1,16 @@ +Qualcomm Technologies, Inc. CDSP Loader Driver + +msm-cdsp-loader driver implements a mechanism to load the Compute DSP firmware images. + +Required properties: + + - compatible: This must be "qcom,msm-cdsp-loader". + - qcom,proc-img-to-load: CDSP firmware name, must be "cdsp". + +Example: + The following is an example: + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; diff --git a/bindings/msm-fastrpc.txt b/bindings/msm-fastrpc.txt new file mode 100644 index 00000000..d839212b --- /dev/null +++ b/bindings/msm-fastrpc.txt @@ -0,0 +1,100 @@ +Qualcomm Technologies, Inc. FastRPC Driver + +The MSM FastRPC driver implements an IPC (Inter-Processor Communication) +mechanism that allows for clients to transparently make remote method +invocations across DSP and APPS boundaries. This enables developers +to offload tasks to the DSP and free up the application processor for +other tasks. + +Required properties: +- compatible : Must be one of "qcom,msm-fastrpc-adsp" or "qcom,msm-fastrpc-compute" + +Optional properties: +- qcom,rpc-latency-us : FastRPC QoS latency vote +- qcom,adsp-remoteheap-vmid : FastRPC remote heap VMID list +- qcom,secure-context-bank : Bool indicating secure FastRPC context bank. +- qcom,fastrpc-legacy-remote-heap : Bool indicating hypervisor is not supported. +- qcom,fastrpc-adsp-audio-pdr : Flag to enable ADSP Audio PDR +- qcom,secure-domains : FastRPC secure domain configuration +- qcom,fastrpc-adsp-sensors-pdr : Flag to enable Sensors PDR + +Optional subnodes: +- qcom,msm_fastrpc_compute_cb : Child nodes representing the compute context banks +- qcom,msm-fastrpc-rpmsg : Child node for rpmsg instead of glink for IPC + +Subnode Required properties: +- compatible : Must be "qcom,msm-fastrpc-compute-cb" +- label : Label describing the channel this context bank belongs to +- iommus : A list of phandle and IOMMU specifier pairs that describe the + IOMMU master interfaces of the device +- dma-coherent : A flag marking a context bank as I/O coherent +- shared-cb : A value indicating how many fastrpc sessions can share a + context bank + +Example: + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,fastrpc-rpmsg; + qcom,rpc-latency-us = <235>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + intents = <0x64 64>; + }; + + qcom,msm_fastrpc_compute_cb_1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1401 0x0>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb_2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x1402 0x0>; + shared-cb = <5>; + }; + }; + +Legacy SMMU v1/v2: + +Required properties: +- compatible : Must be "qcom,msm-fastprc-legacy-compute-cb" + +Required subnode: +- qcom,msm_fastrpc_compute_cb : Child nodes representing the compute context + banks + +Required subnode properties: +- qcom,adsp-shared-phandle : phandle that describe the context bank handle +- qcom,adsp-shared-sids : A list of SID associated with the context bank +- qcom,virtual-addr-pool : Virtual address range that the context bank + will be using + +Example: + qcom,adsprpc_domains { + compatible = "qcom,msm-fastrpc-legacy-compute-cb"; + qcom,msm_fastrpc_compute_cb { + qcom,adsp-shared-phandle = <&adsp_shared>; + qcom,adsp-shared-sids = <0x8 0x9>; + qcom,virtual-addr-pool = <0x80000000 0x7FFFFFFF>; + }; + }; + +Remote Heap: + +Required properties: +- compatible : Must be "qcom,msm-adsprpc-mem-region" +- memory-region : CMA region which is owned by this device +- restrict-access : Blocking vote for hyp_assign_phys function call + +Example: + qcom,adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; diff --git a/niobe/niobe-dsp.dts b/niobe/niobe-dsp.dts new file mode 100644 index 00000000..43e3be92 --- /dev/null +++ b/niobe/niobe-dsp.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "niobe-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Niobe SoC"; + compatible = "qcom,niobe"; + qcom,msm-id = <629 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/niobe/niobe-dsp.dtsi b/niobe/niobe-dsp.dtsi new file mode 100644 index 00000000..f061ca4f --- /dev/null +++ b/niobe/niobe-dsp.dtsi @@ -0,0 +1,224 @@ +&remoteproc_adsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem_heap>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0000>, + <&apps_smmu 0x1063 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0000>, + <&apps_smmu 0x1064 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <2>; /* AUDIO_STATICPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0000>, + <&apps_smmu 0x1065 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,nsessions = <8>; + dma-coherent; + pd-type = <3>; /* SENSORS_STATICPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0000>, + <&apps_smmu 0x1066 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x0000>, + <&apps_smmu 0x1067 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + }; +}; + +&remoteproc_cdsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "cdsp"; + qcom,fastrpc-gids = <2908>; + qcom,rpc-latency-us = <235>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0C01 0x0040>, + <&apps_smmu 0x0C21 0x0000>, + <&apps_smmu 0x0C41 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0C02 0x0040>, + <&apps_smmu 0x0C22 0x0000>, + <&apps_smmu 0x0C42 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0C03 0x0040>, + <&apps_smmu 0x0C23 0x0000>, + <&apps_smmu 0x0C43 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0C04 0x0040>, + <&apps_smmu 0x0C24 0x0000>, + <&apps_smmu 0x0C44 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0C05 0x0040>, + <&apps_smmu 0x0C25 0x0000>, + <&apps_smmu 0x0C45 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0C06 0x0040>, + <&apps_smmu 0x0C26 0x0000>, + <&apps_smmu 0x0C46 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x0C07 0x0040>, + <&apps_smmu 0x0C27 0x0000>, + <&apps_smmu 0x0C47 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x0C08 0x0040>, + <&apps_smmu 0x0C28 0x0000>, + <&apps_smmu 0x0C48 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x0C09 0x0040>, + <&apps_smmu 0x0C29 0x0000>, + <&apps_smmu 0x0C49 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,nsessions = <3>; + dma-coherent; + pd-type = <6>; /* CPZ_USERPD */ + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x0C0C 0x0040>, + <&apps_smmu 0x0C2C 0x0000>, + <&apps_smmu 0x0C4C 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x0C0D 0x0040>, + <&apps_smmu 0x0C2D 0x0000>, + <&apps_smmu 0x0C4D 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x0C0E 0x0040>, + <&apps_smmu 0x0C2E 0x0000>, + <&apps_smmu 0x0C4E 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + }; +}; \ No newline at end of file diff --git a/sun/sun-dsp-trustedvm.dts b/sun/sun-dsp-trustedvm.dts new file mode 100644 index 00000000..3304725f --- /dev/null +++ b/sun/sun-dsp-trustedvm.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "sun-dsp-trustedvm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun - TrustedVM"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>; +}; diff --git a/sun/sun-dsp-trustedvm.dtsi b/sun/sun-dsp-trustedvm.dtsi new file mode 100644 index 00000000..6f78bdf2 --- /dev/null +++ b/sun/sun-dsp-trustedvm.dtsi @@ -0,0 +1,26 @@ +#include +#include + +&soc { + fastrpc_compute_cb1: compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0xC0B 0x0>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qrtr-gen-pool = <&fastrpc_compute_cb1>; + frpc-gen-addr-pool = <0x8000 0x9000>; + pd-type = <4>; /* SECURE_STATICPD */ + }; + + qrtr-genpool { + compatible = "qcom,qrtr-genpool"; + gen-pool = <&fastrpc_compute_cb1>; + interrupt-parent = <&ipcc_mproc_ns1>; + interrupts = , + ; + mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, + <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; + }; +}; diff --git a/sun/sun-dsp.dts b/sun/sun-dsp.dts new file mode 100644 index 00000000..21b53118 --- /dev/null +++ b/sun/sun-dsp.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "sun-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sun v1 SoC"; + compatible = "qcom,sun"; + qcom,board-id = <0 0>; +}; diff --git a/sun/sun-dsp.dtsi b/sun/sun-dsp.dtsi new file mode 100644 index 00000000..53bbbac2 --- /dev/null +++ b/sun/sun-dsp.dtsi @@ -0,0 +1,248 @@ +&remoteproc_adsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem_heap>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0080>, + <&apps_smmu 0x1043 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0080>, + <&apps_smmu 0x1044 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,nsessions = <8>; + dma-coherent; + pd-type = <3>; /* SENSORS_STATICPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0080>, + <&apps_smmu 0x1045 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <2>; /* AUDIO_STATICPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0080>, + <&apps_smmu 0x1046 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <5>; /* OIS_STATICPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x0040>, + <&apps_smmu 0x1067 0x0000>, + <&apps_smmu 0x1087 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1008 0x0080>, + <&apps_smmu 0x1048 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + }; +}; + +&remoteproc_cdsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "cdsp"; + qcom,fastrpc-gids = <2908>; + qcom,rpc-latency-us = <235>; + qcom,single-core-latency-vote; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x19C1 0x0000>, + <&apps_smmu 0x0C21 0x0000>, + <&apps_smmu 0x0C01 0x0040>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1962 0x0000>, + <&apps_smmu 0x0C02 0x0020>, + <&apps_smmu 0x0C42 0x0000>, + <&apps_smmu 0x19C2 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1963 0x0000>, + <&apps_smmu 0x0C23 0x0000>, + <&apps_smmu 0x0C03 0x0040>, + <&apps_smmu 0x19C3 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1964 0x0000>, + <&apps_smmu 0x0C24 0x0000>, + <&apps_smmu 0x0C04 0x0040>, + <&apps_smmu 0x19C4 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1965 0x0000>, + <&apps_smmu 0x0C25 0x0000>, + <&apps_smmu 0x0C05 0x0040>, + <&apps_smmu 0x19C5 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1966 0x0000>, + <&apps_smmu 0x0C06 0x0020>, + <&apps_smmu 0x0C46 0x0000>, + <&apps_smmu 0x19C6 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1967 0x0000>, + <&apps_smmu 0x0C27 0x0000>, + <&apps_smmu 0x0C07 0x0040>, + <&apps_smmu 0x19C7 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1968 0x0000>, + <&apps_smmu 0x0C08 0x0020>, + <&apps_smmu 0x0C48 0x0000>, + <&apps_smmu 0x19C8 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1969 0x0000>, + <&apps_smmu 0x0C29 0x0000>, + <&apps_smmu 0x0C09 0x0040>, + <&apps_smmu 0x19C9 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,nsessions = <3>; + dma-coherent; + pd-type = <6>; /* CPZ_USERPD */ + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x196C 0x0000>, + <&apps_smmu 0x0C2C 0x0000>, + <&apps_smmu 0x0C0C 0x0040>, + <&apps_smmu 0x19CC 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x196D 0x0000>, + <&apps_smmu 0x0C0D 0x0020>, + <&apps_smmu 0x0C2E 0x0000>, + <&apps_smmu 0x0C4D 0x0000>, + <&apps_smmu 0x19CD 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x196E 0x0000>, + <&apps_smmu 0x0C0E 0x0040>, + <&apps_smmu 0x19CE 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + }; +}; \ No newline at end of file From 735781a8450b95e8e4be7ad9df38bc35d94ee04d Mon Sep 17 00:00:00 2001 From: Anirudh Raghavendra Date: Tue, 30 Jan 2024 12:16:33 -0800 Subject: [PATCH 03/41] arm64: dts: qcom: sun: Enable compilation of opensource dt project Enable compilation of devicetree files in opensource dsp-devicetree Change-Id: I399f8f8c09c9d2b4d537316e1dd8706be25d0681 Signed-off-by: Anirudh Raghavendra --- Kbuild | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/Kbuild b/Kbuild index 199cee42..da494fad 100644 --- a/Kbuild +++ b/Kbuild @@ -1,14 +1,14 @@ -#ifeq ($(CONFIG_ARCH_SUN), y) -#ifeq ($(CONFIG_ARCH_QTI_VM), y) -#dtbo-y += sun-dsp-trustedvm.dtbo -#else -#dtbo-y += sun-dsp.dtbo -#endif -#endif +ifeq ($(CONFIG_ARCH_SUN), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-y += sun/sun-dsp-trustedvm.dtbo +else +dtbo-y += sun/sun-dsp.dtbo +endif +endif -#ifeq ($(CONFIG_ARCH_NIOBE), y) -#dtbo-y += niobe-dsp.dtbo -#endif +ifeq ($(CONFIG_ARCH_NIOBE), y) +dtbo-y += niobe/niobe-dsp.dtbo +endif always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) From f96ec39484f03842eab87dde7d5b6b0d1c037f65 Mon Sep 17 00:00:00 2001 From: Anirudh Raghavendra Date: Thu, 22 Feb 2024 15:45:21 -0800 Subject: [PATCH 04/41] arm64: dts: qcom: sun: Add pineapple and blair DT files to opensource Add the removed DT files of pineapple and blair targets to opensource project. Change-Id: I20afed782c053c2899fd3f662278f6721ad2e2e6 Signed-off-by: Anirudh Raghavendra --- Kbuild | 12 ++ blair/blair-dsp.dts | 11 ++ blair/blair-dsp.dtsi | 132 +++++++++++++++ pineapple/pineapple-dsp-trustedvm.dts | 10 ++ pineapple/pineapple-dsp-trustedvm.dtsi | 33 ++++ pineapple/pineapple-dsp.dts | 15 ++ pineapple/pineapple-dsp.dtsi | 225 +++++++++++++++++++++++++ 7 files changed, 438 insertions(+) create mode 100644 blair/blair-dsp.dts create mode 100644 blair/blair-dsp.dtsi create mode 100644 pineapple/pineapple-dsp-trustedvm.dts create mode 100644 pineapple/pineapple-dsp-trustedvm.dtsi create mode 100644 pineapple/pineapple-dsp.dts create mode 100644 pineapple/pineapple-dsp.dtsi diff --git a/Kbuild b/Kbuild index da494fad..6efa2e2a 100644 --- a/Kbuild +++ b/Kbuild @@ -1,3 +1,15 @@ +ifeq ($(CONFIG_ARCH_PINEAPPLE), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-y += pineapple/pineapple-dsp-trustedvm.dtbo +else +dtbo-y += pineapple/pineapple-dsp.dtbo +endif +endif + +ifeq ($(CONFIG_ARCH_BLAIR), y) +dtbo-y += blair/blair-dsp.dtbo +endif + ifeq ($(CONFIG_ARCH_SUN), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) dtbo-y += sun/sun-dsp-trustedvm.dtbo diff --git a/blair/blair-dsp.dts b/blair/blair-dsp.dts new file mode 100644 index 00000000..c0a12e2d --- /dev/null +++ b/blair/blair-dsp.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "blair-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. blair v1 SoC"; + compatible = "qcom,blair"; + qcom,msm-id = <507 0x10000>, <578 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/blair/blair-dsp.dtsi b/blair/blair-dsp.dtsi new file mode 100644 index 00000000..31cf0215 --- /dev/null +++ b/blair/blair-dsp.dtsi @@ -0,0 +1,132 @@ +&remoteproc_adsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem_heap>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x00A3 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x00A4 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x00A5 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,nsessions = <8>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x00A6 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x00A7 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + }; +}; + +&remoteproc_cdsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "cdsp"; + qcom,fastrpc-gids = <2908>; + qcom,rpc-latency-us = <611>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1001 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1002 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1009 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + dma-coherent; + }; + }; +}; \ No newline at end of file diff --git a/pineapple/pineapple-dsp-trustedvm.dts b/pineapple/pineapple-dsp-trustedvm.dts new file mode 100644 index 00000000..46394d5c --- /dev/null +++ b/pineapple/pineapple-dsp-trustedvm.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "pineapple-dsp-trustedvm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple - TrustedVM"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>; +}; diff --git a/pineapple/pineapple-dsp-trustedvm.dtsi b/pineapple/pineapple-dsp-trustedvm.dtsi new file mode 100644 index 00000000..f157baf3 --- /dev/null +++ b/pineapple/pineapple-dsp-trustedvm.dtsi @@ -0,0 +1,33 @@ +#include +#include + +&soc { + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + qcom,qos-cores = <0 1 2 3>; + + fastrpc_compute_cb1: qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0xC0B 0x0>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qrtr-gen-pool = <&fastrpc_compute_cb1>; + frpc-gen-addr-pool = <0x8000 0x9000>; + pd-type = <4>; /* SECURE_STATICPD */ + }; + }; + + qrtr-genpool { + compatible = "qcom,qrtr-genpool"; + gen-pool = <&fastrpc_compute_cb1>; + interrupt-parent = <&ipcc_mproc_ns1>; + interrupts = , + ; + mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, + <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; + }; +}; diff --git a/pineapple/pineapple-dsp.dts b/pineapple/pineapple-dsp.dts new file mode 100644 index 00000000..45e58bd2 --- /dev/null +++ b/pineapple/pineapple-dsp.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include "pineapple-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. pineapple v1 SoC"; + compatible = "qcom,pineapple"; + qcom,board-id = <0 0>; +}; diff --git a/pineapple/pineapple-dsp.dtsi b/pineapple/pineapple-dsp.dtsi new file mode 100644 index 00000000..b532fffa --- /dev/null +++ b/pineapple/pineapple-dsp.dtsi @@ -0,0 +1,225 @@ +&glink_edge { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem_heap>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0080>, + <&apps_smmu 0x1043 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0080>, + <&apps_smmu 0x1044 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,nsessions = <8>; + dma-coherent; + pd-type = <3>; /* SENSORS_STATICPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0080>, + <&apps_smmu 0x1045 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <2>; /* AUDIO_STATICPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0080>, + <&apps_smmu 0x1046 0x0020>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x0040>, + <&apps_smmu 0x1067 0x0000>, + <&apps_smmu 0x1087 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + }; +}; + +&remoteproc_cdsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "cdsp"; + qcom,fastrpc-gids = <2908>; + qcom,rpc-latency-us = <235>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1961 0x0000>, + <&apps_smmu 0x0C01 0x0020>, + <&apps_smmu 0x19C1 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1962 0x0000>, + <&apps_smmu 0x0C02 0x0020>, + <&apps_smmu 0x19C2 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1963 0x0000>, + <&apps_smmu 0x0C03 0x0020>, + <&apps_smmu 0x19C3 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1964 0x0000>, + <&apps_smmu 0x0C04 0x0020>, + <&apps_smmu 0x19C4 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1965 0x0000>, + <&apps_smmu 0x0C05 0x0020>, + <&apps_smmu 0x19C5 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1966 0x0000>, + <&apps_smmu 0x0C06 0x0020>, + <&apps_smmu 0x19C6 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1967 0x0000>, + <&apps_smmu 0x0C07 0x0020>, + <&apps_smmu 0x19C7 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1968 0x0000>, + <&apps_smmu 0x0C08 0x0020>, + <&apps_smmu 0x19C8 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1969 0x0000>, + <&apps_smmu 0x0C09 0x0020>, + <&apps_smmu 0x19C9 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,nsessions = <3>; + dma-coherent; + pd-type = <6>; /* CPZ_USERPD */ + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x196C 0x0000>, + <&apps_smmu 0x0C0C 0x0020>, + <&apps_smmu 0x19CC 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x196D 0x0000>, + <&apps_smmu 0x0C0D 0x0020>, + <&apps_smmu 0x19CD 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x196E 0x0000>, + <&apps_smmu 0x0C0E 0x0020>, + <&apps_smmu 0x19CE 0x0000>; + qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + }; +}; \ No newline at end of file From a8c3e5c73839d353da0d21e8dd82b8beae552909 Mon Sep 17 00:00:00 2001 From: Anirudh Raghavendra Date: Mon, 26 Feb 2024 11:46:50 -0800 Subject: [PATCH 05/41] arm64: dts: msm: Propagate gerrits 5108976 and 5008443 to opensource branch Manually propagate gerrits to new opensource branch from older proprietary branch. Change-Id: I982aa22e173de607f1dc6be778b7887eb47dbcfe Signed-off-by: Anirudh Raghavendra --- bindings/msm-fastrpc.txt | 2 ++ sun/sun-dsp.dtsi | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/bindings/msm-fastrpc.txt b/bindings/msm-fastrpc.txt index d839212b..864db51f 100644 --- a/bindings/msm-fastrpc.txt +++ b/bindings/msm-fastrpc.txt @@ -17,6 +17,8 @@ Optional properties: - qcom,fastrpc-adsp-audio-pdr : Flag to enable ADSP Audio PDR - qcom,secure-domains : FastRPC secure domain configuration - qcom,fastrpc-adsp-sensors-pdr : Flag to enable Sensors PDR +- qcom,single-core-latency-vote : Limit FastRPC PM QoS to only vote for 1 + lowest capacity core Optional subnodes: - qcom,msm_fastrpc_compute_cb : Child nodes representing the compute context banks diff --git a/sun/sun-dsp.dtsi b/sun/sun-dsp.dtsi index 53bbbac2..c46da212 100644 --- a/sun/sun-dsp.dtsi +++ b/sun/sun-dsp.dtsi @@ -15,6 +15,7 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; pd-type = <1>; /* ROOT_PD */ }; @@ -27,6 +28,7 @@ qcom,iommu-faults = "stall-disable", "HUPCF"; qcom,nsessions = <8>; dma-coherent; + qcom,iova-best-fit; pd-type = <3>; /* SENSORS_STATICPD */ }; @@ -38,6 +40,7 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; pd-type = <2>; /* AUDIO_STATICPD */ }; @@ -49,6 +52,7 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; pd-type = <5>; /* OIS_STATICPD */ }; @@ -61,6 +65,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -72,6 +78,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; }; @@ -96,6 +104,7 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; pd-type = <1>; /* ROOT_PD */ }; @@ -109,6 +118,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -122,6 +133,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -135,6 +148,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -148,6 +163,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -161,6 +178,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -174,6 +193,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -187,6 +208,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -203,6 +226,7 @@ qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ qcom,nsessions = <3>; dma-coherent; + qcom,iova-best-fit; pd-type = <6>; /* CPZ_USERPD */ }; @@ -216,6 +240,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -230,6 +256,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; @@ -242,6 +270,8 @@ qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ pd-type = <7>; /* USERPD */ }; }; From d6c8f03029589f75c9f30425ef85dab91bb71056 Mon Sep 17 00:00:00 2001 From: Anirudh Raghavendra Date: Tue, 27 Feb 2024 15:15:44 -0800 Subject: [PATCH 06/41] arm64: dts: msm: Update iommu address field in DT Update DT to accomodate new devicetree property 'iommu-addresses' which describes the IOVA addresses that cannot be used. Update qcom,iommu-dma-addr-pool field to iommu-addresses to reflect this. Update PVM DT file to include all the addresses. Update TVM DT file accordingly. Signed-off-by: Anirudh Raghavendra Change-Id: I8fc25330c2db8d468c283c7c64136177031a8d9c --- sun/sun-dsp-trustedvm.dtsi | 6 +++++- sun/sun-dsp.dtsi | 18 ------------------ 2 files changed, 5 insertions(+), 19 deletions(-) diff --git a/sun/sun-dsp-trustedvm.dtsi b/sun/sun-dsp-trustedvm.dtsi index 6f78bdf2..d0cc2ac7 100644 --- a/sun/sun-dsp-trustedvm.dtsi +++ b/sun/sun-dsp-trustedvm.dtsi @@ -2,11 +2,15 @@ #include &soc { + fastrpc_gen_pool_region : fastrpc_gen_pool_region { + iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>; + }; + fastrpc_compute_cb1: compute-cb@13 { compatible = "qcom,fastrpc-compute-cb"; reg = <11>; iommus = <&apps_smmu 0xC0B 0x0>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; + memory-region = <&fastrpc_gen_pool_region>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; qrtr-gen-pool = <&fastrpc_compute_cb1>; diff --git a/sun/sun-dsp.dtsi b/sun/sun-dsp.dtsi index 53bbbac2..3969f8da 100644 --- a/sun/sun-dsp.dtsi +++ b/sun/sun-dsp.dtsi @@ -12,7 +12,6 @@ reg = <3>; iommus = <&apps_smmu 0x1003 0x0080>, <&apps_smmu 0x1043 0x0020>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <1>; /* ROOT_PD */ @@ -23,7 +22,6 @@ reg = <4>; iommus = <&apps_smmu 0x1004 0x0080>, <&apps_smmu 0x1044 0x0020>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; qcom,nsessions = <8>; dma-coherent; @@ -35,7 +33,6 @@ reg = <5>; iommus = <&apps_smmu 0x1005 0x0080>, <&apps_smmu 0x1045 0x0020>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <2>; /* AUDIO_STATICPD */ @@ -46,7 +43,6 @@ reg = <6>; iommus = <&apps_smmu 0x1006 0x0080>, <&apps_smmu 0x1046 0x0020>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <5>; /* OIS_STATICPD */ @@ -58,7 +54,6 @@ iommus = <&apps_smmu 0x1007 0x0040>, <&apps_smmu 0x1067 0x0000>, <&apps_smmu 0x1087 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -69,7 +64,6 @@ reg = <8>; iommus = <&apps_smmu 0x1008 0x0080>, <&apps_smmu 0x1048 0x0020>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -93,7 +87,6 @@ iommus = <&apps_smmu 0x19C1 0x0000>, <&apps_smmu 0x0C21 0x0000>, <&apps_smmu 0x0C01 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <1>; /* ROOT_PD */ @@ -106,7 +99,6 @@ <&apps_smmu 0x0C02 0x0020>, <&apps_smmu 0x0C42 0x0000>, <&apps_smmu 0x19C2 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -119,7 +111,6 @@ <&apps_smmu 0x0C23 0x0000>, <&apps_smmu 0x0C03 0x0040>, <&apps_smmu 0x19C3 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -132,7 +123,6 @@ <&apps_smmu 0x0C24 0x0000>, <&apps_smmu 0x0C04 0x0040>, <&apps_smmu 0x19C4 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -145,7 +135,6 @@ <&apps_smmu 0x0C25 0x0000>, <&apps_smmu 0x0C05 0x0040>, <&apps_smmu 0x19C5 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -158,7 +147,6 @@ <&apps_smmu 0x0C06 0x0020>, <&apps_smmu 0x0C46 0x0000>, <&apps_smmu 0x19C6 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -171,7 +159,6 @@ <&apps_smmu 0x0C27 0x0000>, <&apps_smmu 0x0C07 0x0040>, <&apps_smmu 0x19C7 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -184,7 +171,6 @@ <&apps_smmu 0x0C08 0x0020>, <&apps_smmu 0x0C48 0x0000>, <&apps_smmu 0x19C8 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -198,7 +184,6 @@ <&apps_smmu 0x0C29 0x0000>, <&apps_smmu 0x0C09 0x0040>, <&apps_smmu 0x19C9 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ qcom,nsessions = <3>; @@ -213,7 +198,6 @@ <&apps_smmu 0x0C2C 0x0000>, <&apps_smmu 0x0C0C 0x0040>, <&apps_smmu 0x19CC 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -227,7 +211,6 @@ <&apps_smmu 0x0C2E 0x0000>, <&apps_smmu 0x0C4D 0x0000>, <&apps_smmu 0x19CD 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ @@ -239,7 +222,6 @@ iommus = <&apps_smmu 0x196E 0x0000>, <&apps_smmu 0x0C0E 0x0040>, <&apps_smmu 0x19CE 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; pd-type = <7>; /* USERPD */ From 3969e073bd0a29cd81775caac3ed7ac24edbdd38 Mon Sep 17 00:00:00 2001 From: Edgar Flores Date: Mon, 4 Mar 2024 17:31:48 -0800 Subject: [PATCH 07/41] ARM: dts: Fix compilation of fastrpc device tree Add Pakala msm-id to fastrpc trusted drivers's dts file. Change-Id: I01069d942a4901a1bef35fbddbee357926fad3e1 --- sun/sun-dsp-trustedvm.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/sun/sun-dsp-trustedvm.dts b/sun/sun-dsp-trustedvm.dts index 3304725f..68cb4c5f 100644 --- a/sun/sun-dsp-trustedvm.dts +++ b/sun/sun-dsp-trustedvm.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; @@ -6,5 +11,5 @@ / { model = "Qualcomm Technologies, Inc. Sun - TrustedVM"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; }; From 0470248d10717d3a9cd9b59916ea55f53b5b4e9f Mon Sep 17 00:00:00 2001 From: Edgar Flores Date: Wed, 27 Mar 2024 13:32:46 -0700 Subject: [PATCH 08/41] ARM: dts: qcom: Add new msm-ids for sun SoC Add new msm-ids for fastrpc dts to support different thermal profiles. Change-Id: I09dca4a363d70a35dd5d7860b6f4f5580184b4e1 --- sun/sun-dsp-trustedvm.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sun/sun-dsp-trustedvm.dts b/sun/sun-dsp-trustedvm.dts index 68cb4c5f..06901008 100644 --- a/sun/sun-dsp-trustedvm.dts +++ b/sun/sun-dsp-trustedvm.dts @@ -11,5 +11,7 @@ / { model = "Qualcomm Technologies, Inc. Sun - TrustedVM"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; }; From 4fa97ee67b5f0316c7091334a17f91f898ee7e2e Mon Sep 17 00:00:00 2001 From: Edgar Flores Date: Thu, 28 Mar 2024 16:49:10 -0700 Subject: [PATCH 09/41] arm64: dts: msm: Fix sun's trusted dtsi compilation Update dtsi syntax to fix compilation. Change-Id: I18d2b4960dfdcdc325abf78b57f3f289b2b10ffe --- sun/sun-dsp-trustedvm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sun/sun-dsp-trustedvm.dtsi b/sun/sun-dsp-trustedvm.dtsi index d0cc2ac7..e1c5db54 100644 --- a/sun/sun-dsp-trustedvm.dtsi +++ b/sun/sun-dsp-trustedvm.dtsi @@ -2,7 +2,7 @@ #include &soc { - fastrpc_gen_pool_region : fastrpc_gen_pool_region { + fastrpc_gen_pool_region: fastrpc_gen_pool_region { iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>; }; From b18a9fc602def14c3fc4d96fcd155e809dcbead4 Mon Sep 17 00:00:00 2001 From: Abhinav Parihar Date: Sun, 31 Mar 2024 15:47:00 +0530 Subject: [PATCH 10/41] ARM: dts: qcom: Add new msm-ids for niobe SoC Add new msm-ids for fastrpc dts to support different msm profiles. Change-Id: Iaadf6d39bc76fc685d42fb985de558501dae37d5 --- niobe/niobe-dsp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/niobe/niobe-dsp.dts b/niobe/niobe-dsp.dts index 43e3be92..702b3ce0 100644 --- a/niobe/niobe-dsp.dts +++ b/niobe/niobe-dsp.dts @@ -6,6 +6,6 @@ / { model = "Qualcomm Technologies, Inc. Niobe SoC"; compatible = "qcom,niobe"; - qcom,msm-id = <629 0x10000>; + qcom,msm-id = <629 0x10000>, <652 0x10000>; qcom,board-id = <0 0>; }; From fbe37c58a9d1375a183d776f4c9937f0d559e7be Mon Sep 17 00:00:00 2001 From: Himateja Reddy Date: Tue, 2 Apr 2024 09:03:29 -0700 Subject: [PATCH 11/41] arm64: dts: msm: Add SOC info for sun targets Currently SOC info is not part of DT. Add SOC info to support sun targets Change-Id: I5f22bea964a9b9a561a4ddd1299d34c49f7d0954 Signed-off-by: Himateja Reddy --- sun/sun-dsp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/sun/sun-dsp.dts b/sun/sun-dsp.dts index 21b53118..37f20626 100644 --- a/sun/sun-dsp.dts +++ b/sun/sun-dsp.dts @@ -6,5 +6,6 @@ / { model = "Qualcomm Technologies, Inc. sun v1 SoC"; compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0 0>; }; From 6cbb8a3adf3ccbf23cffb3b0338c0df48fbab8ab Mon Sep 17 00:00:00 2001 From: Abhinav Parihar Date: Fri, 19 Apr 2024 16:43:50 +0530 Subject: [PATCH 12/41] arm64: dts: qcom: niobe: Disable niobe devicetree files This change removes niobe related dsp-devicetree files. As kernel devicetree is proprietary removing niobe devicetree from opensource. Change-Id: If7a080918924a99673b42532164742bfdf5c1d11 Signed-off-by: Abhinav Parihar --- Kbuild | 4 - niobe/niobe-dsp.dts | 11 --- niobe/niobe-dsp.dtsi | 224 ------------------------------------------- 3 files changed, 239 deletions(-) delete mode 100644 niobe/niobe-dsp.dts delete mode 100644 niobe/niobe-dsp.dtsi diff --git a/Kbuild b/Kbuild index 6efa2e2a..7d2ad2c1 100644 --- a/Kbuild +++ b/Kbuild @@ -18,10 +18,6 @@ dtbo-y += sun/sun-dsp.dtbo endif endif -ifeq ($(CONFIG_ARCH_NIOBE), y) -dtbo-y += niobe/niobe-dsp.dtbo -endif - always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/niobe/niobe-dsp.dts b/niobe/niobe-dsp.dts deleted file mode 100644 index 702b3ce0..00000000 --- a/niobe/niobe-dsp.dts +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; -/plugin/; - -#include "niobe-dsp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Niobe SoC"; - compatible = "qcom,niobe"; - qcom,msm-id = <629 0x10000>, <652 0x10000>; - qcom,board-id = <0 0>; -}; diff --git a/niobe/niobe-dsp.dtsi b/niobe/niobe-dsp.dtsi deleted file mode 100644 index f061ca4f..00000000 --- a/niobe/niobe-dsp.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -&remoteproc_adsp_glink { - qcom,fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; - label = "adsp"; - memory-region = <&adsp_mem_heap>; - qcom,vmids = <22 37>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1003 0x0000>, - <&apps_smmu 0x1063 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <1>; /* ROOT_PD */ - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1004 0x0000>, - <&apps_smmu 0x1064 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <2>; /* AUDIO_STATICPD */ - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1005 0x0000>, - <&apps_smmu 0x1065 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - qcom,nsessions = <8>; - dma-coherent; - pd-type = <3>; /* SENSORS_STATICPD */ - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x1006 0x0000>, - <&apps_smmu 0x1066 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x1007 0x0000>, - <&apps_smmu 0x1067 0x0000>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - }; -}; - -&remoteproc_cdsp_glink { - qcom,fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; - label = "cdsp"; - qcom,fastrpc-gids = <2908>; - qcom,rpc-latency-us = <235>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0C01 0x0040>, - <&apps_smmu 0x0C21 0x0000>, - <&apps_smmu 0x0C41 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <1>; /* ROOT_PD */ - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0C02 0x0040>, - <&apps_smmu 0x0C22 0x0000>, - <&apps_smmu 0x0C42 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0C03 0x0040>, - <&apps_smmu 0x0C23 0x0000>, - <&apps_smmu 0x0C43 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x0C04 0x0040>, - <&apps_smmu 0x0C24 0x0000>, - <&apps_smmu 0x0C44 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x0C05 0x0040>, - <&apps_smmu 0x0C25 0x0000>, - <&apps_smmu 0x0C45 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x0C06 0x0040>, - <&apps_smmu 0x0C26 0x0000>, - <&apps_smmu 0x0C46 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x0C07 0x0040>, - <&apps_smmu 0x0C27 0x0000>, - <&apps_smmu 0x0C47 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x0C08 0x0040>, - <&apps_smmu 0x0C28 0x0000>, - <&apps_smmu 0x0C48 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@9 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <9>; - qcom,secure-context-bank; - iommus = <&apps_smmu 0x0C09 0x0040>, - <&apps_smmu 0x0C29 0x0000>, - <&apps_smmu 0x0C49 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ - qcom,nsessions = <3>; - dma-coherent; - pd-type = <6>; /* CPZ_USERPD */ - }; - - compute-cb@10 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <12>; - iommus = <&apps_smmu 0x0C0C 0x0040>, - <&apps_smmu 0x0C2C 0x0000>, - <&apps_smmu 0x0C4C 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@11 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <13>; - iommus = <&apps_smmu 0x0C0D 0x0040>, - <&apps_smmu 0x0C2D 0x0000>, - <&apps_smmu 0x0C4D 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - - compute-cb@12 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <14>; - iommus = <&apps_smmu 0x0C0E 0x0040>, - <&apps_smmu 0x0C2E 0x0000>, - <&apps_smmu 0x0C4E 0x0040>; - qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - pd-type = <7>; /* USERPD */ - }; - }; -}; \ No newline at end of file From c6c5a4d0004f72d083d8ce96967b1cbec599d119 Mon Sep 17 00:00:00 2001 From: Vivekanand Tryambake Date: Thu, 2 May 2024 14:19:42 -0700 Subject: [PATCH 13/41] ARM: dts: msm: new MSM-ID to support for different packagings Add new MSM-ID for SUN target Change-Id: I6690c1ee67e18e272b8eaba26dc8f37e95c4b1e5 --- sun/sun-dsp.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sun/sun-dsp.dts b/sun/sun-dsp.dts index 37f20626..9b4b8993 100644 --- a/sun/sun-dsp.dts +++ b/sun/sun-dsp.dts @@ -6,6 +6,8 @@ / { model = "Qualcomm Technologies, Inc. sun v1 SoC"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0 0>; }; From 48f365b6cf50cbc464b6bad7965c95cc52563441 Mon Sep 17 00:00:00 2001 From: Anand Kulkarni Date: Mon, 6 May 2024 17:03:59 +0530 Subject: [PATCH 14/41] arm64: dts: qcom: monaco: Add devicetree files for monaco Add devicetree files with fastrpc property and context banks information for monaco target. Change-Id: Id98c632698dfcd0d33b5c6346ce940a726ee7067 Signed-off-by: Anand Kulkarni --- Kbuild | 4 +++ monaco/monaco-dsp.dts | 15 ++++++++++ monaco/monaco-dsp.dtsi | 65 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+) create mode 100644 monaco/monaco-dsp.dts create mode 100644 monaco/monaco-dsp.dtsi diff --git a/Kbuild b/Kbuild index 7d2ad2c1..58612c39 100644 --- a/Kbuild +++ b/Kbuild @@ -18,6 +18,10 @@ dtbo-y += sun/sun-dsp.dtbo endif endif +ifeq ($(CONFIG_ARCH_MONACO), y) +dtbo-y += monaco/monaco-dsp.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/monaco/monaco-dsp.dts b/monaco/monaco-dsp.dts new file mode 100644 index 00000000..9f088884 --- /dev/null +++ b/monaco/monaco-dsp.dts @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "monaco-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco SoC"; + compatible = "qcom,monaco"; + qcom,msm-id = <486 0x10000>, <517 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/monaco/monaco-dsp.dtsi b/monaco/monaco-dsp.dtsi new file mode 100644 index 00000000..7bef63cf --- /dev/null +++ b/monaco/monaco-dsp.dtsi @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&glink_edge { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x01C3 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x01C4 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + qcom,nsessions = <5>; + dma-coherent; + pd-type = <3>; /* SENSORS_STATICPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x01C5 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + pd-type = <2>; /* AUDIO_STATICPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x01C6 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x01C7 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + }; +}; \ No newline at end of file From b8de1292e9f2773026dfe103fd614e28a4cac3a3 Mon Sep 17 00:00:00 2001 From: Himateja Reddy Date: Thu, 16 May 2024 16:45:29 -0700 Subject: [PATCH 15/41] arm64: dts: qcom: sun: Add SMMU pool configuration Add Unsigned PD pool configuration and allocation ranges property, used to pool multiple SMMU context banks with a fixed allocation ranges. This pool can be used by multiple Unsigned applications to offload to remote DSP subsystem and this removes the limitation of only allowing fixed number of Unsigned applications to offload to remote DSP subsystem. Change-Id: I3dc4309f4423aae7e68c743d129f9671a1ed96ca Signed-off-by: Himateja Reddy --- bindings/msm-fastrpc.txt | 3 +++ sun/sun-dsp.dtsi | 21 ++++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/bindings/msm-fastrpc.txt b/bindings/msm-fastrpc.txt index 864db51f..f6f31c56 100644 --- a/bindings/msm-fastrpc.txt +++ b/bindings/msm-fastrpc.txt @@ -32,6 +32,9 @@ Subnode Required properties: - dma-coherent : A flag marking a context bank as I/O coherent - shared-cb : A value indicating how many fastrpc sessions can share a context bank +- pd-type : A value indicating remote subsystem proess type +- alloc-size-range: A pair values indicating the allocation size range + of context bank Example: qcom,msm_fastrpc { diff --git a/sun/sun-dsp.dtsi b/sun/sun-dsp.dtsi index 514ccc4f..d4cbd384 100644 --- a/sun/sun-dsp.dtsi +++ b/sun/sun-dsp.dtsi @@ -154,7 +154,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x4000000 0xFFFFFFFF>; }; compute-cb@6 { @@ -168,7 +169,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x4000000 0xFFFFFFFF>; }; compute-cb@7 { @@ -182,7 +184,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x1000000 0xFFFFFFFF>; }; compute-cb@8 { @@ -196,7 +199,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x1000000 0xFFFFFFFF>; }; compute-cb@9 { @@ -226,7 +230,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; }; compute-cb@11 { @@ -241,7 +246,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; }; compute-cb@12 { @@ -254,7 +260,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; }; }; }; \ No newline at end of file From 5ccc2af5ed713f1ef2739bcdb33a04da154de809 Mon Sep 17 00:00:00 2001 From: Edgar Flores Date: Tue, 28 May 2024 15:00:48 -0700 Subject: [PATCH 16/41] arm64: dts: msm: Add iova alignment flags for trusted dtsi Add iova-max-align-shift and iova-best-fit flags to maximize smmu allocation and minimize smmu fragmentation. Change-Id: Iaaab351ca5498a26243ecccd8392ec0bd1c9572c --- sun/sun-dsp-trustedvm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sun/sun-dsp-trustedvm.dtsi b/sun/sun-dsp-trustedvm.dtsi index e1c5db54..381f88c7 100644 --- a/sun/sun-dsp-trustedvm.dtsi +++ b/sun/sun-dsp-trustedvm.dtsi @@ -13,6 +13,8 @@ memory-region = <&fastrpc_gen_pool_region>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ qrtr-gen-pool = <&fastrpc_compute_cb1>; frpc-gen-addr-pool = <0x8000 0x9000>; pd-type = <4>; /* SECURE_STATICPD */ From 8a8c40f33a1fa0d25ee6dd0d282213c9ca178ea6 Mon Sep 17 00:00:00 2001 From: Abhinav Parihar Date: Tue, 9 Jul 2024 14:24:33 +0530 Subject: [PATCH 17/41] arm64: dts: qcom: monaco: Remove coherent property for monaco Remove coherent proeprty for fastrpc smmu context banks in monaco target. Monaco target doesn't support IO coherency hence coherent property is not applicable for monaco. Change-Id: I9d1f46825b264c48dc519cf6be3cb1edb6241d70 Signed-off-by: Abhinav Parihar --- monaco/monaco-dsp.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/monaco/monaco-dsp.dtsi b/monaco/monaco-dsp.dtsi index 7bef63cf..a6589ed8 100644 --- a/monaco/monaco-dsp.dtsi +++ b/monaco/monaco-dsp.dtsi @@ -17,7 +17,6 @@ iommus = <&apps_smmu 0x01C3 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; pd-type = <1>; /* ROOT_PD */ }; @@ -28,7 +27,6 @@ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; qcom,nsessions = <5>; - dma-coherent; pd-type = <3>; /* SENSORS_STATICPD */ }; @@ -38,7 +36,6 @@ iommus = <&apps_smmu 0x01C5 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; pd-type = <2>; /* AUDIO_STATICPD */ }; @@ -48,7 +45,6 @@ iommus = <&apps_smmu 0x01C6 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; pd-type = <7>; /* USERPD */ }; @@ -58,7 +54,6 @@ iommus = <&apps_smmu 0x01C7 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; pd-type = <7>; /* USERPD */ }; }; From fa64779d37f9c812b62520dc1b1df4051bc6aa26 Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Fri, 3 May 2024 16:01:45 +0530 Subject: [PATCH 18/41] ARM: dts: msm: Add parrot dts and dtsi files Add context banks support for parrot Change-Id: Iec07cdee087f72762d278ac4c9015497c22ec007 --- Kbuild | 3 + parrot/parrot-dsp.dts | 14 +++ parrot/parrot-dsp.dtsi | 234 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 251 insertions(+) create mode 100644 parrot/parrot-dsp.dts create mode 100644 parrot/parrot-dsp.dtsi diff --git a/Kbuild b/Kbuild index 58612c39..7a752447 100644 --- a/Kbuild +++ b/Kbuild @@ -22,6 +22,9 @@ ifeq ($(CONFIG_ARCH_MONACO), y) dtbo-y += monaco/monaco-dsp.dtbo endif +ifeq ($(CONFIG_ARCH_PARROT), y) +dtbo-y += parrot/parrot-dsp.dtbo +endif always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/parrot/parrot-dsp.dts b/parrot/parrot-dsp.dts new file mode 100644 index 00000000..8aeb6e31 --- /dev/null +++ b/parrot/parrot-dsp.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; +/plugin/; + +#include "parrot-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. parrot v1 SoC"; + compatible = "qcom,parrot"; + qcom,board-id = <0 0>; +}; diff --git a/parrot/parrot-dsp.dtsi b/parrot/parrot-dsp.dtsi new file mode 100644 index 00000000..a7eac1aa --- /dev/null +++ b/parrot/parrot-dsp.dtsi @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +&glink_edge { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem_heap>; + qcom,vmids = <22 37>; + + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1803 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <1>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1804 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <2>; + }; + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1805 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,nsessions = <5>; + pd-type = <3>; + }; + }; +}; + +&remoteproc_cdsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "cdsp"; + qcom,fastrpc-gids = <2908>; + qcom,rpc-latency-us = <235>; + + qcom,qos-cores = <0 1 2 3>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1401 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + pd-type = <1>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1402 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <7>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1403 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <7>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1404 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <7>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1405 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <7>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1406 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <7>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1407 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <7>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1408 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <7>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1409 0x0400>; + qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; + dma-coherent; + + pd-type = <6>; + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x140B 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; + pd-type = <7>; + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x140C 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <9>; + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x140D 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <9>; + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x140E 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + + qcom,iova-max-align-shift = <9>; + pd-type = <9>; + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + }; +}; From 17ebcbb45d460640c09a22ffa85794f7fedd3e3e Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Fri, 3 May 2024 16:07:57 +0530 Subject: [PATCH 19/41] ARM: dts: msm: Add parrot soc id's Add parrot soc id's Change-Id: I33f2f6e8402cf4f1dd3dd102579be58bc5446f40 --- parrot/parrot-dsp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/parrot/parrot-dsp.dts b/parrot/parrot-dsp.dts index 8aeb6e31..2f4b059d 100644 --- a/parrot/parrot-dsp.dts +++ b/parrot/parrot-dsp.dts @@ -10,5 +10,6 @@ / { model = "Qualcomm Technologies, Inc. parrot v1 SoC"; compatible = "qcom,parrot"; + qcom,msm-id = <537 0x10000>, <613 0x10000>, <663 0x10000>; qcom,board-id = <0 0>; }; From af02293fd94dc99d550cd6de8e72b0714e4e0e58 Mon Sep 17 00:00:00 2001 From: Himanshu Agrawal Date: Wed, 10 Jul 2024 09:28:11 +0530 Subject: [PATCH 20/41] ARM: dts: msm: Add ravelin dts and dtsi files Add ADSP context banks support for ravelin Change-Id: I5654b66740165e8646ef0503ecedff6b6c1661a2 (cherry picked from commit 0aa9cc2941e7b541b3207186d250794ec8d790a8) --- Kbuild | 4 ++++ ravelin/ravelin-dsp.dts | 15 +++++++++++++ ravelin/ravelin-dsp.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) mode change 100644 => 100755 Kbuild create mode 100755 ravelin/ravelin-dsp.dts create mode 100755 ravelin/ravelin-dsp.dtsi diff --git a/Kbuild b/Kbuild old mode 100644 new mode 100755 index 7a752447..935d4f5b --- a/Kbuild +++ b/Kbuild @@ -25,6 +25,10 @@ endif ifeq ($(CONFIG_ARCH_PARROT), y) dtbo-y += parrot/parrot-dsp.dtbo endif + +ifeq ($(CONFIG_ARCH_RAVELIN), y) +dtbo-y += ravelin/ravelin-dsp.dtbo +endif always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/ravelin/ravelin-dsp.dts b/ravelin/ravelin-dsp.dts new file mode 100755 index 00000000..ea175f58 --- /dev/null +++ b/ravelin/ravelin-dsp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; +/plugin/; + +#include "ravelin-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ravelin v1 SoC"; + compatible = "qcom,ravelin"; + qcom,msm-id = <568 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/ravelin/ravelin-dsp.dtsi b/ravelin/ravelin-dsp.dtsi new file mode 100755 index 00000000..70d0c74a --- /dev/null +++ b/ravelin/ravelin-dsp.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +&glink_edge { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem_heap>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1003 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1004 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,nsessions = <4>; + pd-type = <3>; /* SENSORS_STATICPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1005 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + pd-type = <2>; /* AUDIO_STATICPD */ + }; + }; +}; From 9c36971c2405ae5390ff48e4039c68effc8ac140 Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Tue, 16 Jul 2024 15:06:15 +0530 Subject: [PATCH 21/41] ARM: dts: msm: Add parrot soc id's Add parrot soc id's for supporting variants Change-Id: I4ff04da42fb4a4b95599c7d7ee787d2d30a7e1ea --- parrot/parrot-dsp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/parrot/parrot-dsp.dts b/parrot/parrot-dsp.dts index 2f4b059d..b3bb4c4f 100644 --- a/parrot/parrot-dsp.dts +++ b/parrot/parrot-dsp.dts @@ -10,6 +10,6 @@ / { model = "Qualcomm Technologies, Inc. parrot v1 SoC"; compatible = "qcom,parrot"; - qcom,msm-id = <537 0x10000>, <613 0x10000>, <663 0x10000>; + qcom,msm-id = <537 0x10000>, <613 0x10000>, <663 0x10000>, <633 0x10000>, <583 0x10000>, <631 0x10000>, <634 0x10000>, <638 0x10000>; qcom,board-id = <0 0>; }; From 7ae32dc19fad220a4207318f9b87171f29dc414a Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Tue, 30 Jul 2024 13:04:35 +0530 Subject: [PATCH 22/41] ARM: dts: msm: Add ravelin soc id's Add ravelin soc id's for supporting variants Change-Id: I04927bbc4bc6f3a338ca2d2864b759a10907e10b --- ravelin/ravelin-dsp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ravelin/ravelin-dsp.dts b/ravelin/ravelin-dsp.dts index ea175f58..f01619a5 100755 --- a/ravelin/ravelin-dsp.dts +++ b/ravelin/ravelin-dsp.dts @@ -10,6 +10,6 @@ / { model = "Qualcomm Technologies, Inc. ravelin v1 SoC"; compatible = "qcom,ravelin"; - qcom,msm-id = <568 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <654 0x10000>, <653 0x10000>; qcom,board-id = <0 0>; }; From 9a258f7e6f67d26e0f25108a4a9e18de4055ddba Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Tue, 6 Aug 2024 13:57:27 +0530 Subject: [PATCH 23/41] ARM: dts: msm: Add kera dts and dtsi files Add context banks support for kera Change-Id: I84be824b5cca9b40f781a201963c9c0541bf67ed Signed-off-by: Patan Saddam --- kera/kera-dsp-trustedvm.dts | 15 +++ kera/kera-dsp-trustedvm.dtsi | 37 ++++++ kera/kera-dsp.dts | 16 +++ kera/kera-dsp.dtsi | 237 +++++++++++++++++++++++++++++++++++ 4 files changed, 305 insertions(+) create mode 100644 kera/kera-dsp-trustedvm.dts create mode 100644 kera/kera-dsp-trustedvm.dtsi create mode 100644 kera/kera-dsp.dts create mode 100644 kera/kera-dsp.dtsi diff --git a/kera/kera-dsp-trustedvm.dts b/kera/kera-dsp-trustedvm.dts new file mode 100644 index 00000000..2f3bbc0b --- /dev/null +++ b/kera/kera-dsp-trustedvm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-dsp-trustedvm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera - TrustedVM"; + compatible = "qcom,kera"; + qcom,msm-id = <659 0x10000>; +}; diff --git a/kera/kera-dsp-trustedvm.dtsi b/kera/kera-dsp-trustedvm.dtsi new file mode 100644 index 00000000..3bcb133b --- /dev/null +++ b/kera/kera-dsp-trustedvm.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + fastrpc_gen_pool_region: fastrpc_gen_pool_region { + iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>; + }; + + fastrpc_compute_cb1: compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0xC0B 0x0>; + memory-region = <&fastrpc_gen_pool_region>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + qrtr-gen-pool = <&fastrpc_compute_cb1>; + frpc-gen-addr-pool = <0x8000 0x9000>; + pd-type = <4>; /* SECURE_STATICPD */ + }; + + qrtr-genpool { + compatible = "qcom,qrtr-genpool"; + gen-pool = <&fastrpc_compute_cb1>; + interrupt-parent = <&ipcc_mproc_ns1>; + interrupts = , + ; + mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, + <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; + }; +}; diff --git a/kera/kera-dsp.dts b/kera/kera-dsp.dts new file mode 100644 index 00000000..7bbabb5a --- /dev/null +++ b/kera/kera-dsp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera v1 SoC"; + compatible = "qcom,kera"; + qcom,msm-id = <659 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/kera/kera-dsp.dtsi b/kera/kera-dsp.dtsi new file mode 100644 index 00000000..d6604715 --- /dev/null +++ b/kera/kera-dsp.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&remoteproc_adsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem_heap>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0080>, + <&apps_smmu 0x1043 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0080>, + <&apps_smmu 0x1044 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,nsessions = <8>; + dma-coherent; + qcom,iova-best-fit; + pd-type = <3>; /* SENSORS_STATICPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0080>, + <&apps_smmu 0x1045 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + pd-type = <2>; /* AUDIO_STATICPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0080>, + <&apps_smmu 0x1046 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + pd-type = <5>; /* OIS_STATICPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x0040>, + <&apps_smmu 0x1067 0x0000>, + <&apps_smmu 0x1087 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1008 0x0080>, + <&apps_smmu 0x1048 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + }; +}; + +&remoteproc_cdsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "cdsp"; + qcom,fastrpc-gids = <2908>; + qcom,rpc-latency-us = <235>; + qcom,single-core-latency-vote; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0C01 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0C02 0x0000>, + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0C03 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0C04 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0C05 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x4000000 0xFFFFFFFF>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0C06 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x4000000 0xFFFFFFFF>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x0C07 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x1000000 0xFFFFFFFF>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x0C08 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x1000000 0xFFFFFFFF>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x0C09 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,nsessions = <3>; + dma-coherent; + qcom,iova-best-fit; + pd-type = <6>; /* CPZ_USERPD */ + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x0C0C 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x0C0D 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x0C0E 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + }; +}; \ No newline at end of file From 50032b556d329bdef170268134118dcff38983f3 Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Tue, 6 Aug 2024 14:04:38 +0530 Subject: [PATCH 24/41] ARM: dts: msm: Add tuna dts and dtsi files Add context banks support for tuna Change-Id: Ib5a68c71da8211a8a6eaf17d72b46d4449d608f4 Signed-off-by: Patan Saddam --- tuna/tuna-dsp-trustedvm.dts | 15 +++ tuna/tuna-dsp-trustedvm.dtsi | 37 ++++++ tuna/tuna-dsp.dts | 16 +++ tuna/tuna-dsp.dtsi | 237 +++++++++++++++++++++++++++++++++++ 4 files changed, 305 insertions(+) create mode 100644 tuna/tuna-dsp-trustedvm.dts create mode 100644 tuna/tuna-dsp-trustedvm.dtsi create mode 100644 tuna/tuna-dsp.dts create mode 100644 tuna/tuna-dsp.dtsi diff --git a/tuna/tuna-dsp-trustedvm.dts b/tuna/tuna-dsp-trustedvm.dts new file mode 100644 index 00000000..e94e4c31 --- /dev/null +++ b/tuna/tuna-dsp-trustedvm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-dsp-trustedvm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna - TrustedVM"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>; +}; diff --git a/tuna/tuna-dsp-trustedvm.dtsi b/tuna/tuna-dsp-trustedvm.dtsi new file mode 100644 index 00000000..3bcb133b --- /dev/null +++ b/tuna/tuna-dsp-trustedvm.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + fastrpc_gen_pool_region: fastrpc_gen_pool_region { + iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>; + }; + + fastrpc_compute_cb1: compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0xC0B 0x0>; + memory-region = <&fastrpc_gen_pool_region>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + qrtr-gen-pool = <&fastrpc_compute_cb1>; + frpc-gen-addr-pool = <0x8000 0x9000>; + pd-type = <4>; /* SECURE_STATICPD */ + }; + + qrtr-genpool { + compatible = "qcom,qrtr-genpool"; + gen-pool = <&fastrpc_compute_cb1>; + interrupt-parent = <&ipcc_mproc_ns1>; + interrupts = , + ; + mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, + <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; + }; +}; diff --git a/tuna/tuna-dsp.dts b/tuna/tuna-dsp.dts new file mode 100644 index 00000000..42944b9e --- /dev/null +++ b/tuna/tuna-dsp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna v1 SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/tuna/tuna-dsp.dtsi b/tuna/tuna-dsp.dtsi new file mode 100644 index 00000000..d6604715 --- /dev/null +++ b/tuna/tuna-dsp.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&remoteproc_adsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem_heap>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0080>, + <&apps_smmu 0x1043 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0080>, + <&apps_smmu 0x1044 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,nsessions = <8>; + dma-coherent; + qcom,iova-best-fit; + pd-type = <3>; /* SENSORS_STATICPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0080>, + <&apps_smmu 0x1045 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + pd-type = <2>; /* AUDIO_STATICPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0080>, + <&apps_smmu 0x1046 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + pd-type = <5>; /* OIS_STATICPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x0040>, + <&apps_smmu 0x1067 0x0000>, + <&apps_smmu 0x1087 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1008 0x0080>, + <&apps_smmu 0x1048 0x0020>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + }; +}; + +&remoteproc_cdsp_glink { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "cdsp"; + qcom,fastrpc-gids = <2908>; + qcom,rpc-latency-us = <235>; + qcom,single-core-latency-vote; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0C01 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0C02 0x0000>, + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0C03 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0C04 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0C05 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x4000000 0xFFFFFFFF>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0C06 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x4000000 0xFFFFFFFF>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x0C07 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x1000000 0xFFFFFFFF>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x0C08 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x1000000 0xFFFFFFFF>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x0C09 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,nsessions = <3>; + dma-coherent; + qcom,iova-best-fit; + pd-type = <6>; /* CPZ_USERPD */ + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x0C0C 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x0C0D 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x0C0E 0x0000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; + }; + }; +}; \ No newline at end of file From b254cecddd4322b521c8eae17170cf80f12a4072 Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Fri, 16 Aug 2024 11:37:56 +0530 Subject: [PATCH 25/41] ARM: dts: msm: Fix compilation error Add semicolon to fix compilation error. Change-Id: I351917a718ce5526787b7040c5c3b8d9d3a274ae Signed-off-by: Patan Saddam --- kera/kera-dsp.dtsi | 2 +- tuna/tuna-dsp.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/kera/kera-dsp.dtsi b/kera/kera-dsp.dtsi index d6604715..3bd28a86 100644 --- a/kera/kera-dsp.dtsi +++ b/kera/kera-dsp.dtsi @@ -107,7 +107,7 @@ compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; - iommus = <&apps_smmu 0x0C02 0x0000>, + iommus = <&apps_smmu 0x0C02 0x0000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; qcom,iova-best-fit; diff --git a/tuna/tuna-dsp.dtsi b/tuna/tuna-dsp.dtsi index d6604715..3bd28a86 100644 --- a/tuna/tuna-dsp.dtsi +++ b/tuna/tuna-dsp.dtsi @@ -107,7 +107,7 @@ compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; - iommus = <&apps_smmu 0x0C02 0x0000>, + iommus = <&apps_smmu 0x0C02 0x0000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; qcom,iova-best-fit; From 826a016e5bf899aacc4e3ec3c4ac92d2fa796c65 Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Mon, 2 Sep 2024 13:59:03 +0530 Subject: [PATCH 26/41] ARM: dts: msm: Add supported board-id's for ravelin Add supported board-id's for ravelin Change-Id: Ice7a66a17e3b68d9e666cb5453b344ec70eb5263 --- ravelin/ravelin-dsp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ravelin/ravelin-dsp.dts b/ravelin/ravelin-dsp.dts index f01619a5..12974332 100755 --- a/ravelin/ravelin-dsp.dts +++ b/ravelin/ravelin-dsp.dts @@ -11,5 +11,5 @@ model = "Qualcomm Technologies, Inc. ravelin v1 SoC"; compatible = "qcom,ravelin"; qcom,msm-id = <568 0x10000>, <602 0x10000>, <654 0x10000>, <653 0x10000>; - qcom,board-id = <0 0>; + qcom,board-id = <0 0>, <0x1000B 0>, <0x1000B 0x600>, <33 0>, <34 0>, <34 0x601>, <34 2>; }; From bf73e49e40a49b75eb49d4b5e777c45a3be4de55 Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Tue, 1 Oct 2024 00:25:12 +0530 Subject: [PATCH 27/41] ARM: dts: msm: Add tuna7 soc id Add tuna7 soc id. Change-Id: I14c8196bde03eaf683d7eb4bae3f1ef15caf76d3 Signed-off-by: Patan Saddam --- tuna/tuna-dsp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tuna/tuna-dsp.dts b/tuna/tuna-dsp.dts index 42944b9e..16e2dc3e 100644 --- a/tuna/tuna-dsp.dts +++ b/tuna/tuna-dsp.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna v1 SoC"; compatible = "qcom,tuna"; - qcom,msm-id = <655 0x10000>; + qcom,msm-id = <655 0x10000>, <681 0x10000>; qcom,board-id = <0 0>; }; From a575778002e6a175c798f7dfc554ae850300ffd9 Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Mon, 12 Aug 2024 12:35:39 +0530 Subject: [PATCH 28/41] arm64: dts: msm: Enable compilation of dt project for tuna Enable compilation of devicetree files in opensource dsp-devicetree. Change-Id: I03ca15806692389a3e28c4c1c64756fe872f2c79 Signed-off-by: Patan Saddam --- Kbuild | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Kbuild b/Kbuild index 935d4f5b..7e40c673 100755 --- a/Kbuild +++ b/Kbuild @@ -18,6 +18,14 @@ dtbo-y += sun/sun-dsp.dtbo endif endif +ifeq ($(CONFIG_ARCH_TUNA), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-y += tuna/tuna-dsp-trustedvm.dtbo +else +dtbo-y += tuna/tuna-dsp.dtbo +endif +endif + ifeq ($(CONFIG_ARCH_MONACO), y) dtbo-y += monaco/monaco-dsp.dtbo endif From 2f90bc992d4f162b223d7e2f200e5593532a17a8 Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Tue, 15 Oct 2024 13:23:55 +0530 Subject: [PATCH 29/41] ARM: dts: msm: Add kera APQ SKU soc id Add kera APQ SKU soc id. Change-Id: I513d88531287e93a4e1c66fa6415275b8001a974 Signed-off-by: Patan Saddam --- kera/kera-dsp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kera/kera-dsp.dts b/kera/kera-dsp.dts index 7bbabb5a..c5985ddc 100644 --- a/kera/kera-dsp.dts +++ b/kera/kera-dsp.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Kera v1 SoC"; compatible = "qcom,kera"; - qcom,msm-id = <659 0x10000>; + qcom,msm-id = <659 0x10000>, <686 0x10000>; qcom,board-id = <0 0>; }; From daad2c1ce53e8614e74c3f5170f1fef41e7e9cff Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Tue, 15 Oct 2024 14:22:09 +0530 Subject: [PATCH 30/41] arm64: dts: msm: Enable compilation of dt project for kera Enable compilation of devicetree files in opensource dsp-devicetree. Change-Id: I0ffdd35cb09c8b3e953faae511c438e3002f2024 Signed-off-by: Patan Saddam --- Kbuild | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Kbuild b/Kbuild index 7e40c673..29f9fa35 100755 --- a/Kbuild +++ b/Kbuild @@ -26,6 +26,14 @@ dtbo-y += tuna/tuna-dsp.dtbo endif endif +ifeq ($(CONFIG_ARCH_KERA), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-y += kera/kera-dsp-trustedvm.dtbo +else +dtbo-y += kera/kera-dsp.dtbo +endif +endif + ifeq ($(CONFIG_ARCH_MONACO), y) dtbo-y += monaco/monaco-dsp.dtbo endif From 357167c25c81fbc3dcd2e214f40a7b94653e7417 Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Mon, 28 Oct 2024 10:24:13 +0530 Subject: [PATCH 31/41] ARM: dts: msm: Add tuna APQ SKU soc id Add tuna APQ SKU soc id. Change-Id: If7b7f1271f49776b205a8f2044eb5202d4ba4dea Signed-off-by: Patan Saddam --- tuna/tuna-dsp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tuna/tuna-dsp.dts b/tuna/tuna-dsp.dts index 16e2dc3e..e3132278 100644 --- a/tuna/tuna-dsp.dts +++ b/tuna/tuna-dsp.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna v1 SoC"; compatible = "qcom,tuna"; - qcom,msm-id = <655 0x10000>, <681 0x10000>; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; qcom,board-id = <0 0>; }; From a1df76367c92dbd9c7f5ed07ce84ec36e78884c3 Mon Sep 17 00:00:00 2001 From: Liam Mark Date: Thu, 14 Nov 2024 16:29:30 -0800 Subject: [PATCH 32/41] arm64: dts: msm: Increase GLINK intents There is currently a potential for a deadlock in the DSP when it wants to send a GLINK message but is waiting for an intent. Increase the number of intents to 1 more than the number of DSP supported threads so that the DSP won't have to wait for intents. Signed-off-by: Liam Mark Change-Id: I8503886606027df45d6bcd2f4492a484cdc84696 --- sun/sun-dsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sun/sun-dsp.dtsi b/sun/sun-dsp.dtsi index d4cbd384..95f193ae 100644 --- a/sun/sun-dsp.dtsi +++ b/sun/sun-dsp.dtsi @@ -2,7 +2,7 @@ qcom,fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; + qcom,intents = <0x181 64>; label = "adsp"; memory-region = <&adsp_mem_heap>; qcom,vmids = <22 37>; @@ -83,7 +83,7 @@ qcom,fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; + qcom,intents = <0x3fA 64>; label = "cdsp"; qcom,fastrpc-gids = <2908>; qcom,rpc-latency-us = <235>; @@ -264,4 +264,4 @@ alloc-size-range = <0x0 0xFFFFFFFF>; }; }; -}; \ No newline at end of file +}; From 1b0cf025ed92cdbda45502e239185d04011d8aad Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Thu, 28 Nov 2024 19:41:05 +0530 Subject: [PATCH 33/41] arm64: dts: msm: Enable compilation of trusted-vm dt project for kera and tuna Enable compilation of trusted-vm dt files in opensource dsp-devicetree. Change-Id: I41929b0ac907efb3610bc1c4da91dc95b73bee4a Signed-off-by: Patan Saddam --- Kbuild | 8 -------- kera/kera-dsp-trustedvm.dts | 15 --------------- kera/kera-dsp-trustedvm.dtsi | 37 ------------------------------------ sun/sun-dsp-trustedvm.dts | 3 ++- tuna/tuna-dsp-trustedvm.dts | 15 --------------- tuna/tuna-dsp-trustedvm.dtsi | 37 ------------------------------------ 6 files changed, 2 insertions(+), 113 deletions(-) delete mode 100644 kera/kera-dsp-trustedvm.dts delete mode 100644 kera/kera-dsp-trustedvm.dtsi delete mode 100644 tuna/tuna-dsp-trustedvm.dts delete mode 100644 tuna/tuna-dsp-trustedvm.dtsi diff --git a/Kbuild b/Kbuild index 29f9fa35..feca9c76 100755 --- a/Kbuild +++ b/Kbuild @@ -19,20 +19,12 @@ endif endif ifeq ($(CONFIG_ARCH_TUNA), y) -ifeq ($(CONFIG_ARCH_QTI_VM), y) -dtbo-y += tuna/tuna-dsp-trustedvm.dtbo -else dtbo-y += tuna/tuna-dsp.dtbo endif -endif ifeq ($(CONFIG_ARCH_KERA), y) -ifeq ($(CONFIG_ARCH_QTI_VM), y) -dtbo-y += kera/kera-dsp-trustedvm.dtbo -else dtbo-y += kera/kera-dsp.dtbo endif -endif ifeq ($(CONFIG_ARCH_MONACO), y) dtbo-y += monaco/monaco-dsp.dtbo diff --git a/kera/kera-dsp-trustedvm.dts b/kera/kera-dsp-trustedvm.dts deleted file mode 100644 index 2f3bbc0b..00000000 --- a/kera/kera-dsp-trustedvm.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "kera-dsp-trustedvm.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Kera - TrustedVM"; - compatible = "qcom,kera"; - qcom,msm-id = <659 0x10000>; -}; diff --git a/kera/kera-dsp-trustedvm.dtsi b/kera/kera-dsp-trustedvm.dtsi deleted file mode 100644 index 3bcb133b..00000000 --- a/kera/kera-dsp-trustedvm.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include -#include - -&soc { - fastrpc_gen_pool_region: fastrpc_gen_pool_region { - iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>; - }; - - fastrpc_compute_cb1: compute-cb@13 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <11>; - iommus = <&apps_smmu 0xC0B 0x0>; - memory-region = <&fastrpc_gen_pool_region>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - qcom,iova-best-fit; - qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - qrtr-gen-pool = <&fastrpc_compute_cb1>; - frpc-gen-addr-pool = <0x8000 0x9000>; - pd-type = <4>; /* SECURE_STATICPD */ - }; - - qrtr-genpool { - compatible = "qcom,qrtr-genpool"; - gen-pool = <&fastrpc_compute_cb1>; - interrupt-parent = <&ipcc_mproc_ns1>; - interrupts = , - ; - mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, - <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; - }; -}; diff --git a/sun/sun-dsp-trustedvm.dts b/sun/sun-dsp-trustedvm.dts index 06901008..6b35c0ea 100644 --- a/sun/sun-dsp-trustedvm.dts +++ b/sun/sun-dsp-trustedvm.dts @@ -13,5 +13,6 @@ compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>, - <0x100027f 0x10000>, <0x100027f 0x20000>; + <0x100027f 0x10000>, <0x100027f 0x20000>, <655 0x10000>, + <681 0x10000>, <694 0x10000>,<659 0x10000>, <686 0x10000>; }; diff --git a/tuna/tuna-dsp-trustedvm.dts b/tuna/tuna-dsp-trustedvm.dts deleted file mode 100644 index e94e4c31..00000000 --- a/tuna/tuna-dsp-trustedvm.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "tuna-dsp-trustedvm.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Tuna - TrustedVM"; - compatible = "qcom,tuna"; - qcom,msm-id = <655 0x10000>; -}; diff --git a/tuna/tuna-dsp-trustedvm.dtsi b/tuna/tuna-dsp-trustedvm.dtsi deleted file mode 100644 index 3bcb133b..00000000 --- a/tuna/tuna-dsp-trustedvm.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include -#include - -&soc { - fastrpc_gen_pool_region: fastrpc_gen_pool_region { - iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>; - }; - - fastrpc_compute_cb1: compute-cb@13 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <11>; - iommus = <&apps_smmu 0xC0B 0x0>; - memory-region = <&fastrpc_gen_pool_region>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - qcom,iova-best-fit; - qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - qrtr-gen-pool = <&fastrpc_compute_cb1>; - frpc-gen-addr-pool = <0x8000 0x9000>; - pd-type = <4>; /* SECURE_STATICPD */ - }; - - qrtr-genpool { - compatible = "qcom,qrtr-genpool"; - gen-pool = <&fastrpc_compute_cb1>; - interrupt-parent = <&ipcc_mproc_ns1>; - interrupts = , - ; - mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, - <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; - }; -}; From 0cfcbcd2d6b40be7e235702e0aab36edf37f5ded Mon Sep 17 00:00:00 2001 From: Patan Saddam Date: Thu, 28 Nov 2024 19:41:05 +0530 Subject: [PATCH 34/41] arm64: dts: msm: Enable compilation of trusted-vm dt project for kera and tuna Enable compilation of trusted-vm dt files in opensource dsp-devicetree. Change-Id: I41929b0ac907efb3610bc1c4da91dc95b73bee4a Signed-off-by: Patan Saddam (cherry picked from commit 1b0cf025ed92cdbda45502e239185d04011d8aad) --- Kbuild | 8 -------- kera/kera-dsp-trustedvm.dts | 15 --------------- kera/kera-dsp-trustedvm.dtsi | 37 ------------------------------------ sun/sun-dsp-trustedvm.dts | 3 ++- tuna/tuna-dsp-trustedvm.dts | 15 --------------- tuna/tuna-dsp-trustedvm.dtsi | 37 ------------------------------------ 6 files changed, 2 insertions(+), 113 deletions(-) delete mode 100644 kera/kera-dsp-trustedvm.dts delete mode 100644 kera/kera-dsp-trustedvm.dtsi delete mode 100644 tuna/tuna-dsp-trustedvm.dts delete mode 100644 tuna/tuna-dsp-trustedvm.dtsi diff --git a/Kbuild b/Kbuild index 29f9fa35..feca9c76 100755 --- a/Kbuild +++ b/Kbuild @@ -19,20 +19,12 @@ endif endif ifeq ($(CONFIG_ARCH_TUNA), y) -ifeq ($(CONFIG_ARCH_QTI_VM), y) -dtbo-y += tuna/tuna-dsp-trustedvm.dtbo -else dtbo-y += tuna/tuna-dsp.dtbo endif -endif ifeq ($(CONFIG_ARCH_KERA), y) -ifeq ($(CONFIG_ARCH_QTI_VM), y) -dtbo-y += kera/kera-dsp-trustedvm.dtbo -else dtbo-y += kera/kera-dsp.dtbo endif -endif ifeq ($(CONFIG_ARCH_MONACO), y) dtbo-y += monaco/monaco-dsp.dtbo diff --git a/kera/kera-dsp-trustedvm.dts b/kera/kera-dsp-trustedvm.dts deleted file mode 100644 index 2f3bbc0b..00000000 --- a/kera/kera-dsp-trustedvm.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "kera-dsp-trustedvm.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Kera - TrustedVM"; - compatible = "qcom,kera"; - qcom,msm-id = <659 0x10000>; -}; diff --git a/kera/kera-dsp-trustedvm.dtsi b/kera/kera-dsp-trustedvm.dtsi deleted file mode 100644 index 3bcb133b..00000000 --- a/kera/kera-dsp-trustedvm.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include -#include - -&soc { - fastrpc_gen_pool_region: fastrpc_gen_pool_region { - iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>; - }; - - fastrpc_compute_cb1: compute-cb@13 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <11>; - iommus = <&apps_smmu 0xC0B 0x0>; - memory-region = <&fastrpc_gen_pool_region>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - qcom,iova-best-fit; - qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - qrtr-gen-pool = <&fastrpc_compute_cb1>; - frpc-gen-addr-pool = <0x8000 0x9000>; - pd-type = <4>; /* SECURE_STATICPD */ - }; - - qrtr-genpool { - compatible = "qcom,qrtr-genpool"; - gen-pool = <&fastrpc_compute_cb1>; - interrupt-parent = <&ipcc_mproc_ns1>; - interrupts = , - ; - mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, - <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; - }; -}; diff --git a/sun/sun-dsp-trustedvm.dts b/sun/sun-dsp-trustedvm.dts index 06901008..6b35c0ea 100644 --- a/sun/sun-dsp-trustedvm.dts +++ b/sun/sun-dsp-trustedvm.dts @@ -13,5 +13,6 @@ compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>, - <0x100027f 0x10000>, <0x100027f 0x20000>; + <0x100027f 0x10000>, <0x100027f 0x20000>, <655 0x10000>, + <681 0x10000>, <694 0x10000>,<659 0x10000>, <686 0x10000>; }; diff --git a/tuna/tuna-dsp-trustedvm.dts b/tuna/tuna-dsp-trustedvm.dts deleted file mode 100644 index e94e4c31..00000000 --- a/tuna/tuna-dsp-trustedvm.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "tuna-dsp-trustedvm.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Tuna - TrustedVM"; - compatible = "qcom,tuna"; - qcom,msm-id = <655 0x10000>; -}; diff --git a/tuna/tuna-dsp-trustedvm.dtsi b/tuna/tuna-dsp-trustedvm.dtsi deleted file mode 100644 index 3bcb133b..00000000 --- a/tuna/tuna-dsp-trustedvm.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include -#include - -&soc { - fastrpc_gen_pool_region: fastrpc_gen_pool_region { - iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>; - }; - - fastrpc_compute_cb1: compute-cb@13 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <11>; - iommus = <&apps_smmu 0xC0B 0x0>; - memory-region = <&fastrpc_gen_pool_region>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - qcom,iova-best-fit; - qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - qrtr-gen-pool = <&fastrpc_compute_cb1>; - frpc-gen-addr-pool = <0x8000 0x9000>; - pd-type = <4>; /* SECURE_STATICPD */ - }; - - qrtr-genpool { - compatible = "qcom,qrtr-genpool"; - gen-pool = <&fastrpc_compute_cb1>; - interrupt-parent = <&ipcc_mproc_ns1>; - interrupts = , - ; - mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, - <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; - }; -}; From 08061321521b851468d7d559c9eaa6c9dd2417c5 Mon Sep 17 00:00:00 2001 From: Santosh Date: Fri, 20 Dec 2024 13:46:07 +0530 Subject: [PATCH 35/41] ARM: dts: msm: Update PD type from the unsigned PD pool to user PD For the Parrot target DSP, the QURT kernel does not support multiple unsigned sessions with the same SID, resulting in spawn failures for subsequent unsigned sessions. To address this, update the PD type property from the unsigned PD pool to user PD. Change-Id: Ic8afce3b318e4ccbbd5d682d4c14006d52920e97 Signed-off-by: Santosh --- parrot/parrot-dsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/parrot/parrot-dsp.dtsi b/parrot/parrot-dsp.dtsi index a7eac1aa..150a6ea5 100644 --- a/parrot/parrot-dsp.dtsi +++ b/parrot/parrot-dsp.dtsi @@ -199,7 +199,7 @@ dma-coherent; qcom,iova-max-align-shift = <9>; - pd-type = <9>; + pd-type = <7>; alloc-size-range = <0x0 0xFFFFFFFF>; }; @@ -213,7 +213,7 @@ dma-coherent; qcom,iova-max-align-shift = <9>; - pd-type = <9>; + pd-type = <7>; alloc-size-range = <0x0 0xFFFFFFFF>; }; @@ -227,7 +227,7 @@ dma-coherent; qcom,iova-max-align-shift = <9>; - pd-type = <9>; + pd-type = <7>; alloc-size-range = <0x0 0xFFFFFFFF>; }; }; From ba3cccd0be106170642f18cf33995b6eb6ad79e4 Mon Sep 17 00:00:00 2001 From: Om Deore Date: Fri, 10 Jan 2025 17:05:41 +0530 Subject: [PATCH 36/41] arm64: dts: msm: Increase GLINK intents There is currently a potential for a deadlock in the DSP when it wants to send a GLINK message but is waiting for an intent. Increase the number of intents to 1 more than the number of DSP supported threads so that the DSP won't have to wait for intents. Change-Id: I6fa6239573926fb8cef3ce56b8c8a7833435e8ba Signed-off-by: Om Deore --- tuna/tuna-dsp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tuna/tuna-dsp.dtsi b/tuna/tuna-dsp.dtsi index 3bd28a86..ddf2f69f 100644 --- a/tuna/tuna-dsp.dtsi +++ b/tuna/tuna-dsp.dtsi @@ -7,7 +7,7 @@ qcom,fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; + qcom,intents = <0x181 64>; label = "adsp"; memory-region = <&adsp_mem_heap>; qcom,vmids = <22 37>; @@ -88,7 +88,7 @@ qcom,fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; + qcom,intents = <0x3fA 64>; label = "cdsp"; qcom,fastrpc-gids = <2908>; qcom,rpc-latency-us = <235>; From a2a0bc1cd8efb58f684e95355da518fe3ad4efb2 Mon Sep 17 00:00:00 2001 From: Om Deore Date: Wed, 15 Jan 2025 10:39:56 +0530 Subject: [PATCH 37/41] arm64: dts: msm: Enable GLINK RT callback handling GLINK changed to using a non-RT priority when handling channel callbacks. For FastRPC configure GLINK to use RT priority when handling channel callbacks to avoid any performance regression. Change-Id: Ie6e04caceb8ca4fcd9688975c3335ef5d6c7b1c8 Signed-off-by: Om Deore --- tuna/tuna-dsp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tuna/tuna-dsp.dtsi b/tuna/tuna-dsp.dtsi index ddf2f69f..d4a41047 100644 --- a/tuna/tuna-dsp.dtsi +++ b/tuna/tuna-dsp.dtsi @@ -8,6 +8,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x181 64>; + qcom,ch-sched-rt; label = "adsp"; memory-region = <&adsp_mem_heap>; qcom,vmids = <22 37>; @@ -89,6 +90,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x3fA 64>; + qcom,ch-sched-rt; label = "cdsp"; qcom,fastrpc-gids = <2908>; qcom,rpc-latency-us = <235>; From ca5254fe54f1c03e902157172946a47ed2d0514a Mon Sep 17 00:00:00 2001 From: Om Deore Date: Wed, 15 Jan 2025 10:32:11 +0530 Subject: [PATCH 38/41] arm64: dts: msm: Enable cb handing in irq context GLINK changed their default handling of channel callbacks from the irq context to a callback thread. This change impacted FastRPC performance. Configure FastRPC to use irq context to handle channel callbacks to fix the performance regression. Change-Id: I8ab7a69127e66e046d10f5bd226cfb74e6ba2318 Signed-off-by: Om Deore --- tuna/tuna-dsp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tuna/tuna-dsp.dtsi b/tuna/tuna-dsp.dtsi index d4a41047..34cd57ea 100644 --- a/tuna/tuna-dsp.dtsi +++ b/tuna/tuna-dsp.dtsi @@ -9,6 +9,7 @@ qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x181 64>; qcom,ch-sched-rt; + qcom,cb-irq; label = "adsp"; memory-region = <&adsp_mem_heap>; qcom,vmids = <22 37>; @@ -91,6 +92,7 @@ qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x3fA 64>; qcom,ch-sched-rt; + qcom,cb-irq; label = "cdsp"; qcom,fastrpc-gids = <2908>; qcom,rpc-latency-us = <235>; From c82525e3219af5527ce0a9d40aa0d35327f452a2 Mon Sep 17 00:00:00 2001 From: Om Deore Date: Thu, 27 Feb 2025 15:01:04 +0530 Subject: [PATCH 39/41] arm64: dts: msm: Increase GLINK intents There is currently a potential for a deadlock in the DSP when it wants to send a GLINK message but is waiting for an intent. Increase the number of intents to 1 more than the number of DSP supported threads so that the DSP won't have to wait for intents. Change-Id: I31edbebe06738bb56a8305957fde74388c4a5154 Signed-off-by: Om Deore --- kera/kera-dsp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kera/kera-dsp.dtsi b/kera/kera-dsp.dtsi index 3bd28a86..ddf2f69f 100644 --- a/kera/kera-dsp.dtsi +++ b/kera/kera-dsp.dtsi @@ -7,7 +7,7 @@ qcom,fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; + qcom,intents = <0x181 64>; label = "adsp"; memory-region = <&adsp_mem_heap>; qcom,vmids = <22 37>; @@ -88,7 +88,7 @@ qcom,fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; + qcom,intents = <0x3fA 64>; label = "cdsp"; qcom,fastrpc-gids = <2908>; qcom,rpc-latency-us = <235>; From bcd55c2a7bf01eef24cbe8d3ee1d0e6d57ee334e Mon Sep 17 00:00:00 2001 From: Om Deore Date: Thu, 27 Feb 2025 15:04:26 +0530 Subject: [PATCH 40/41] arm64: dts: msm: Enable GLINK RT callback handling GLINK changed to using a non-RT priority when handling channel callbacks. For FastRPC configure GLINK to use RT priority when handling channel callbacks to avoid any performance regression. Change-Id: Ia1b0a105b79fb450d1fe3437ad88b3ce5d9fd943 Signed-off-by: Om Deore --- kera/kera-dsp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kera/kera-dsp.dtsi b/kera/kera-dsp.dtsi index ddf2f69f..d4a41047 100644 --- a/kera/kera-dsp.dtsi +++ b/kera/kera-dsp.dtsi @@ -8,6 +8,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x181 64>; + qcom,ch-sched-rt; label = "adsp"; memory-region = <&adsp_mem_heap>; qcom,vmids = <22 37>; @@ -89,6 +90,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x3fA 64>; + qcom,ch-sched-rt; label = "cdsp"; qcom,fastrpc-gids = <2908>; qcom,rpc-latency-us = <235>; From e0847f2bb351627dc60272883f48b5be7404f1d6 Mon Sep 17 00:00:00 2001 From: Om Deore Date: Thu, 27 Feb 2025 15:07:20 +0530 Subject: [PATCH 41/41] arm64: dts: msm: Enable cb handing in irq context GLINK changed their default handling of channel callbacks from the irq context to a callback thread. This change impacted FastRPC performance. Configure FastRPC to use irq context to handle channel callbacks to fix the performance regression. Change-Id: I59b2611e2ebe3f5d33650666a8ad7912d79cc1d1 Signed-off-by: Om Deore --- kera/kera-dsp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kera/kera-dsp.dtsi b/kera/kera-dsp.dtsi index d4a41047..34cd57ea 100644 --- a/kera/kera-dsp.dtsi +++ b/kera/kera-dsp.dtsi @@ -9,6 +9,7 @@ qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x181 64>; qcom,ch-sched-rt; + qcom,cb-irq; label = "adsp"; memory-region = <&adsp_mem_heap>; qcom,vmids = <22 37>; @@ -91,6 +92,7 @@ qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x3fA 64>; qcom,ch-sched-rt; + qcom,cb-irq; label = "cdsp"; qcom,fastrpc-gids = <2908>; qcom,rpc-latency-us = <235>;