ARM: dts: qcom: Correct CPU masks for sun platforms
Correct the prime and silver cores mapping. Enable the smmu's iommu-dma-addr-pool to reduce memory usage. Enable the smmu's dma-coherent. Change-Id: I4c28c48b59cc8cf4159969f89d7983d574921a4f Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
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@@ -1520,6 +1520,9 @@
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phy-names = "ufsphy";
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phy-names = "ufsphy";
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#reset-cells = <1>;
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#reset-cells = <1>;
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qcom,prime-mask = <0xc0>;
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qcom,silver-mask = <0x3f>;
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lanes-per-direction = <2>;
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lanes-per-direction = <2>;
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dev-ref-clk-freq = <0>; /* 19.2 MHz */
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dev-ref-clk-freq = <0>; /* 19.2 MHz */
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clock-names =
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clock-names =
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@@ -1620,22 +1623,26 @@
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iommus = <&apps_smmu 0x60 0x0>;
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iommus = <&apps_smmu 0x60 0x0>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-dma = "fastmap";
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qcom,iommu-dma-addr-pool = <0x1000 0xFFFFF000>;
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shared-ice-cfg = <&ice_cfg>;
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shared-ice-cfg = <&ice_cfg>;
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dma-coherent;
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qcom,bypass-pbl-rst-wa;
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qcom,bypass-pbl-rst-wa;
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status = "disabled";
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status = "disabled";
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qos0 {
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qos0 {
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mask = <0xfc>;
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mask = <0xc0>;
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vote = <44>;
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vote = <44>;
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perf;
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perf;
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cpu_freq_vote = <2 5 7>;
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/* Set CPU6 to fmax, and CPU[6-7] will run at fmax */
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cpu_freq_vote = <6>;
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};
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};
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qos1 {
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qos1 {
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mask = <0x03>;
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mask = <0x3f>;
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vote = <44>;
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vote = <44>;
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/* Set CPU0 to fmax, and CPU[0-5] will run at fmax */
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cpu_freq_vote = <0>;
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cpu_freq_vote = <0>;
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};
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};
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};
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};
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