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ARM: dts: msm: Increase pipe clock toggles during L1SS entry

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Increase the number of pipe clock toggles that will occur after
phystatus goes high at the output of the PHY during L1SS/P2 entry
in PCS_PCIE_POWER_STATE_CONFIG6 register, so that if the phy and
controller goes out of sync this may help us. The number of pipe
clock toggles is equal to (4*value)+1.

Change-Id: I7a31882f18879ef990825aa2d978fc7f39233472
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
This commit is contained in:
Vivek Pernamitta
2025-01-16 11:33:09 +05:30
committed by Krishna Chaitanya Chundru
parent 2e1aa4f45f
commit a3a111ed95
1 changed files with 2 additions and 1 deletions
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3
qcom/sun-pcie.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-sun.h>
@@ -214,6 +214,7 @@
0x0814 0x07 0x0
0x0820 0xc1 0x0
0x0894 0x00 0x0
0x08f8 0x1f 0x0
0x05d0 0x8c 0x0
0x0568 0x17 0x0
0x0570 0x2e 0x0