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Add 'qcom/wlan/' from WLAN.LA.1.0.r1-08000-pakala.0 of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/wlan-devicetree

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git-subtree-dir: qcom/wlan
git-subtree-mainline: cc9d84727a
git-subtree-split: 551f3bbb6a
This commit is contained in:
kmiit
2025-06-12 16:45:10 +08:00
parent cc9d84727a 551f3bbb6a
commit a1131dac0f
64 changed files with 5069 additions and 0 deletions
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68
qcom/wlan/Kbuild Normal file
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ifeq ($(CONFIG_ARCH_CANOE),y)
dtbo-y += canoe-kiwi-cnss.dtbo
dtbo-y += canoe-peach-cnss.dtbo
endif
ifeq ($(CONFIG_ARCH_SUN),y)
dtbo-y += sun-kiwi-cnss.dtbo
dtbo-y += sun-kiwi-cnss-v8.dtbo
dtbo-y += sun-peach-cnss.dtbo
dtbo-y += sun-peach-cnss-v8.dtbo
dtbo-y += sunp-hdk-peach-cnss-v8.dtbo
endif
ifeq ($(CONFIG_ARCH_PINEAPPLE),y)
dtbo-y += pineapple-kiwi-cnss.dtbo
dtbo-y += pineapplep-hdk-kiwi-cnss.dtbo
endif
ifeq ($(CONFIG_ARCH_X1E80100),y)
dtbo-y += x1e80100-kiwi-cnss.dtbo
endif
ifeq ($(CONFIG_ARCH_RAVELIN),y)
dtbo-y += ravelin-idp-adrastea.dtbo
dtbo-y += ravelin-qrd-adrastea.dtbo
dtbo-y += ravelin-atp-adrastea.dtbo
endif
ifeq ($(CONFIG_ARCH_PARROT),y)
dtbo-y += parrot-idp-wcn3990.dtbo
dtbo-y += parrot-idp-wcn6750.dtbo
dtbo-y += parrot-qrd-wcn3990.dtbo
dtbo-y += parrot-qrd-wcn6750.dtbo
dtbo-y += parrot-atp-wcn3990.dtbo
dtbo-y += parrot-rumi-wcn3990.dtbo
dtbo-y += parrot-idp-wcn6755.dtbo
dtbo-y += parrot-qrd-wcn6755.dtbo
endif
ifeq ($(CONFIG_ARCH_VOLCANO),y)
dtbo-y += volcano-qca6750.dtbo
dtbo-y += volcano6i-peach-cnss.dtbo
endif
ifeq ($(CONFIG_ARCH_TUNA),y)
dtbo-y += tuna-rcm-wcn7750.dtbo
dtbo-y += tuna-cdp-wcn7750.dtbo
dtbo-y += tuna-mtp-wcn7750.dtbo
dtbo-y += tuna-mtp-qmp1000-wcn7750.dtbo
dtbo-y += tuna-qrd-wcn7750.dtbo
dtbo-y += tuna-mtp-kiwi.dtbo
dtbo-y += tuna-rcm-kiwi.dtbo
dtbo-y += tuna-atp-kiwi.dtbo
endif
ifeq ($(CONFIG_ARCH_KERA),y)
dtbo-y += kera-atp-qca6750.dtbo
dtbo-y += kera-cdp-qca6750.dtbo
dtbo-y += kera-mtp-qca6750.dtbo
dtbo-y += kera-rcm-qca6750.dtbo
dtbo-y += kera-mtp-wcn7750.dtbo
dtbo-y += kera-qrd-wcn7750.dtbo
dtbo-y += kera-rcm-wcn7750.dtbo
endif
always-y := $(dtb-y) $(dtbo-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb *.dtbo

10
qcom/wlan/Makefile Normal file
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# SPDX-License-Identifier: GPL-2.0
KBUILD_OPTIONS += KBUILD_EXTMOD_DTS=.
all: dtbs
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
%:
$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)

148
qcom/wlan/alor-kiwi-cnss.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,alor.h>
&wlan_msa_mem {
status = "disabled";
};
&wpss_mem {
status = "disabled";
};
&wpss_pas {
status = "disabled";
};
&pcie0 {
status = "ok";
};
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio18";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio19";
function = "wcn_sw";
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0x0 0xb0000000 0x0 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&pm8550ve_d_gpios 3 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
//TODO REGULATORS VOTING
//TODO BUS-BW
//TODO PMU-VREG-PDC mapping for ol_cpr
//TODO PDC AOP cmd for hmt
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
};
};
&pcie_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <2>;
#size-cells = <2>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from alor-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-geometry = <0x0 0x98000000 0x0 0x18010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF",
"non-fatal";
};
};
};

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qcom/wlan/alor-wcn7750.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,alor.h>
&tlmm {
icnss_sw_ctrl: icnss_sw_ctrl {
mux {
pins = "gpio18";
function = "wcn_sw_ctrl";
};
};
};
&soc {
qcom,smp2p-wpss {
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
qcom,entry-name = "wlan";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
qcom,entry-name = "wlan";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
qcom,entry-name = "wlan_soc_wake";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
qcom,entry-name = "wlan_soc_wake";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
qcom,entry-name = "wlan_ep_power_save";
#qcom,smem-state-cells = <1>;
};
};
icnss2_direct_link_iommu_group0: icnss2_direct_link_iommu_group0 {
qcom,iommu-dma-addr-pool = <0x0 0xb0000000 0x0 0x10000000>;
qcom,iommu-geometry = <0x0 0xb0000000 0x0 0x10010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
};
icnss2: qcom,wcn7750 {
compatible = "qcom,wcn7750";
reg = <0x0 0x17010040 0x0 0x0>,
<0x0 0xc0000000 0x0 0x10000>;
reg-names = "msi_addr", "smmu_iova_ipa";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x1400 0x1>;
wlan-en-gpio =<35>;
host-sol-gpio =<95>;
dev-sol-gpio =<17>;
sw-ctrl-gpio =<18>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18>;
pinctrl-names = "sw_ctrl";
pinctrl-0 = <&icnss_sw_ctrl>;
interrupts = <GIC_SPI 896 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 897 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 898 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 899 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 900 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 901 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 902 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 903 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 904 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 905 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 906 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 907 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 908 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 909 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 910 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 911 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 912 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 913 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 914 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 915 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 916 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 917 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 918 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 919 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 920 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 921 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 923 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 924 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 925 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 926 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 927 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 928 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-group = <&icnss2_direct_link_iommu_group0>;
dma-coherent;
pin-ctrl-support;
qcom,fw-prefix;
qcom,wlan;
tsens = "sys-therm-3";//TODO VERIFY from thermal team
wcn-hw-version = "wcn7750";
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
//TODO REGULATOR VOTING
qcom,smem-states = <&smp2p_wlan_1_out 0>,
<&smp2p_wlan_2_out 0>,
<&smp2p_wlan_3_out 0>;
qcom,smem-state-names = "wlan-smp2p-out",
"wlan-soc-wake-smp2p-out",
"wlan-ep-powersave-smp2p-out";
qcom,qmp = <&aoss_qmp>;
qcom,vreg_ol_cpr ="s2d";
//TODO BUS BW
icnss_cdev_apss: icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: icnss_cdev2 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
qcom,smp2p_map_wlan_2_in {
interrupts-extended = <&smp2p_wlan_2_in 0 0>;
interrupt-names = "qcom,smp2p-soc-wake-ack";
};
};
wlan_direct_link: qcom,icnss-direct-link {
compatible = "qcom,icnss-direct-link";
iommus = <&apps_smmu 0x100f 0x0>;
qcom,iommu-group = <&icnss2_direct_link_iommu_group0>;
dma-coherent;
};
};

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qcom/wlan/bindings/cnss-wlan.yaml Normal file
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# Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
title: Connectivity SubSystem Platform Driver
description:
Connectivity SubSystem platform driver adds support for the CNSS subsystem
used for PCIe based Wi-Fi devices. It also adds support to integrate PCIe
WLAN module to subsystem restart framework. Apart from that, it also manages
the 3.3V voltage regulator, WLAN Enable GPIO signal and PCIe link dynamically
with support for suspend and resume by retaining the PCI config space
states when PCIe link is shutdown. The main purpose of this device tree
entry below is to invoke the CNSS platform driver and provide handle to
the WLAN enable GPIO, 3.3V fixed voltage regulator resources. It also
provides the reserved RAM dump memory location and size.
properties:
compatible:
enum:
- qcom,cnss #for QCA6174 device
- qcom,cnss-qca6290 #for QCA6290 device
- qcom,cnss-qca6390 #for QCA6390 device
- qcom,cnss-qca6490 #for QCA6490 device
- qcom,cnss-kiwi #for KIWI device
- qcom,cnss-qca-converged #for converged QCA devices
wlan-en-gpio:
description: WLAN_EN GPIO signal specified by the chip specifications.
vdd-wlan-supply:
description: phandle to the regulator device tree node.
pinctrl-names:
description: Names corresponding to the numbered pinctrl states.
pinctrl-<n>:
description: |
Pinctrl states as described in
bindings/pinctrl/pinctrl-bindings.txt.
qcom,wlan-rc-num:
description: |
List of PCIe root complex numbers which WLAN device may
attach to.
qcom,wlan:
description: |
Signature string for WLAN devices which all CNSS family drivers
are able to search for.
mpm_wake_set_gpios:
description: |
U32 array of GPIOs which need to be setup for
interrupt wakeup capable.
qcom,notify-modem-status:
description: |
Boolean property to decide whether modem
notification should be enabled or not in this
platform.
wlan-soc-swreg-supply:
description: phandle to the external 1.15V regulator for QCA6174.
wlan-ant-switch-supply:
description: |
phandle to the 2.7V regulator for the antenna
switch of QCA6174.
qcom,wlan-uart-access:
description: |
Boolean property to decide whether QCA6174
has exclusive access to UART.
vdd-wlan-io-supply:
description: phandle to the 1.8V IO regulator for QCA6174.
vdd-wlan-io12-supply:
description: phandle to the 1.2V IO regulator for Kiwi.
vdd-wlan-ant-share-supply:
description: phandle to the Antenna Sharing regulator.
vdd-wlan-xtal-supply:
description: phandle to the 1.8V XTAL regulator for QCA6174.
vdd-wlan-xtal-aon-supply:
description: |
phandle to the LDO-4 regulator. This is needed
on platforms where XTAL regulator depends on
always on regulator in VDDmin.
vdd-wlan-ctrl1-supply:
description: |
phandle to the DBU1 - 1.8V for QCA6595 or 3.3V for
QCA6174 on auto platform.
vdd-wlan-ctrl2-supply:
description: |
phandle to the DBU4 - 2.2V for QCA6595 or 3.85V for
QCA6696 on auto platform.
vdd-wlan-core-supply:
description: phandle to the 1.3V CORE regulator for QCA6174.
vdd-wlan-sp2t-supply:
description: phandle to the 2.7V SP2T regulator for QCA6174.
<supply-name>-supply:
description: |
phandle to the regulator device tree node.
optional "supply-name" is "vdd-wlan-rfa".
qcom,<supply>-config:
description: |
Specifies voltage levels for supply. Should specified
in pairs (min, max), units uV. There can be optional
load in uA and Regulator settle delay in us.
qcom,smmu-s1-enable:
description: |
Boolean property to decide whether to enable SMMU
S1 stage or not.
qcom,wlan-smmu-iova-address:
description: |
I/O virtual address range as <start length>
format to be used for allocations associated
between WLAN/PCIe and SMMU.
qcom,wlan-ramdump-dynamic:
description: |
To enable CNSS RAMDUMP collection
by providing the size of CNSS DUMP.
qcom,cmd_db_name:
description: |
CommandDB name indicating the PMIC rail used for open
loop CPR.
reg:
description: Memory regions defined as starting address and size.
reg-names:
description: Names of the memory regions defined in reg entry.
wlan-bootstrap-gpio:
description: |
WLAN_BOOTSTRAP GPIO signal specified by QCA6174
which should be drived depending on platforms.
qcom,is-dual-wifi-enabled:
description: |
Boolean property to control wlan enable(wlan-en)
gpio on dual-wifi platforms.
vdd-wlan-en-supply:
description: |
WLAN_EN fixed regulator specified by QCA6174
specifications.
qcom,wlan-en-vreg-support:
description: |
Boolean property to decide the whether the
WLAN_EN pin is a gpio or fixed regulator.
qcom,mhi:
description: phandle to indicate the device which needs MHI support.
qcom,cap-tsf-gpio:
description: |
WLAN_TSF_CAPTURED GPIO signal specified by the chip
specifications, should be drived depending on products.
cnss-daemon-support:
description: |
Boolean property to decide whether cnss_daemon
userspace QMI client is supported.
use-nv-mac:
description: Boolean property to indicate whether NV MAC is used or not.
qcom,set-wlaon-pwr-ctrl:
description: |
Boolean property to indicate if set
WLAON_QFPROM_PWR_CTRL_REG register during power on
and off sequences.
use-pm-domain:
description: |
Boolean property to indicate if driver needs to use PM
domain or not.
qcom,wlan-cbc-enabled:
description: boolean property to control cold boot calibration.
interconnects:
description: Interconnect framework setup for bus configuration.
interconnect-names:
description: Interconnect path names as strings.
qcom,icc-path-count:
description: Number of Interconnect paths for this platform.
qcom,bus-bw-cfg-count:
description: Number of bus bandwidth voting cases.
qcom,bus-bw-cfg:
description: Bus bandwidth voting data.
wlan-txrx-intr-cpumask:
description: cpumask for wlan tx rx interrupt affinity
qcom,tcs_offset_int_pow_amp_vreg:
description: |
TCS CMD register offset for Voltage
regulator used in internal power amplifier for QCA6490.
cnss-enable-self-recovery:
description: |
Boolean property to enable self recovery when
recovery is trigeered with reason link down.
qcom,bt-en-gpio:
description: |
QCA6490 requires synchronization for BT and WLAN GPIO
enable to resolve PMU power up issues. Provide BT GPIO using
this config param.
qcom,same-dt-multi-dev:
description: |
Boolean property to decide whether it supports
multiple WLAN devices using the same DT node
without sub-nodes.
qcom,converged-dt:
description: |
Boolean property to decide whether it supports multiple
WLAN devices using the same DT node with sub-nodes.
mboxes:
description: Specifies mbox channel data for AOP messaging.
qcom,vreg_ipa:
description: |
Specifies voltage regulator used for WLAN device internal
power amp config.
qcom,xo-clk-gpio:
description: Added for QCA6490 XO CLK selection leakage prevention.
platform-name-required:
description: |
Boolean property to decide whether
platform name required.
chip_cfg@X:
description: represent chip specific configurations
enum:
-supported-ids #U32 array to decide which device ids are supported by sub node.
required:
- compatible
- wlan-en-gpio
- vdd-wlan-supply
- pinctrl-names
- pinctrl-<n>
- qcom,wlan-rc-num
- qcom,wlan
examples:
- |
qcom,cnss@0d400000 {
compatible = "qcom,cnss";
reg = <0x0d400000 0x200000>;
reg-names = "ramdump";
qcom,wlan-ramdump-dynamic = <0x200000>;
wlan-en-gpio = <&msmgpio 82 0>;
vdd-wlan-supply = <&wlan_vreg>;
qcom,notify-modem-status;
wlan-soc-swreg-supply = <&pma8084_l27>;
pinctrl-names = "default";
pinctrl-0 = <&cnss_default>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-smmu-iova-address = <0 0x10000000>;
qcom,mhi = <&mhi_wlan>;
qcom,cap-tsf-gpio = <&tlmm 126 1>;
};
wlan: qcom,cnss-qca6490@b0000000 {
compatible = "qcom,cnss-qca6490";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
wlan-en-gpio = <&tlmm 80 0>;
qcom,bt-en-gpio = <&tlmm 81 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x420000>;
qcom,wlan-cbc-enabled;
use-pm-domain;
cnss-enable-self-recovery;
qcom,same-dt-multi-dev;
mboxes = <&qmp_aop 0>;
qcom,vreg_ipa="s3e";
qcom,xo-clk-gpio = <&tlmm 204 0>;
vdd-wlan-aon-supply = <&S2E>;
qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 1>;
vdd-wlan-dig-supply = <&S11B>;
qcom,vdd-wlan-dig-config = <966000 966000 0 0 1>;
vdd-wlan-io-supply = <&S10B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
vdd-wlan-rfa1-supply = <&S1C>;
qcom,vdd-wlan-rfa1-config = <1900000 2100000 0 0 1>;
vdd-wlan-rfa2-supply = <&S12B>;
qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
wlan-ant-switch-supply = <&L7E>;
qcom,wlan-ant-switch-config = <2800000 2800000 0 0 1>;
};
wlan: qcom,cnss-qca-converged {
compatible = "qcom,cnss-qca-converged";
qcom,converged-dt;
qcom,wlan-sw-ctrl-gpio = <&tlmm 83 0>;
chip_cfg@0 {
supported-ids = <0x1103>;
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
wlan-en-gpio = <&tlmm 80 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
qcom,wlan-cbc-enabled;
use-pm-domain;
mboxes = <&qmp_aop 0>;
vdd-wlan-io-supply = <&L15B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
vdd-wlan-supply = <&S5G>;
qcom,vdd-wlan-config = <1000000 1000000 0 0 1>;
vdd-wlan-aon-supply = <&S2G>;
qcom,vdd-wlan-aon-config = <980000 980000 0 0 1>;
vdd-wlan-dig-supply = <&S4E>;
qcom,vdd-wlan-dig-config = <950000 950000 0 0 1>;
vdd-wlan-rfa1-supply = <&S6G>;
qcom,vdd-wlan-rfa1-config = <1900000 1900000 0 0 1>;
vdd-wlan-rfa2-supply = <&S4G>;
qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
};
};
...

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# Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
title: Integrated connectivity Platform Driver
description:
Integrated connectivity platform driver adds support for the Integrated WLAN
that runs on Q6 based platforms. WLAN FW on these architecture runs on Q6. This
platform driver communicates with WLAN FW over QMI, WLAN on/off messages
to FW are communicated thru this interface. This driver also listens to
WLAN PD restart notifications.
properties:
compatible:
enum:
- qcom,icnss #for ADRASTEA architecture
- qcom,wcn6750 #for iWCN architecture
- qcom,wcn6450 #for evros architecture
- qcom,wcn7750 #for wcn7750 architecture
reg:
description: Memory regions defined as starting address and size.
reg-names:
description: Names of the memory regions defined in reg entry.
interrupts:
description: Copy engine interrupt table.
qcom,wlan-msa-memory:
description: MSA memory size.
clocks:
description: List of clock phandles.
clock-names:
description: List of clock names corresponding to the "clocks" property.
iommus:
description: SMMUs and corresponding Stream IDs needed by WLAN.
qcom,wlan-smmu-iova-address:
description: |
I/O virtual address range as <start length>
format to be used for allocations associated between WLAN and SMMU.
qcom,wlan:
description: |
Signature string for WLAN devices which all CNSS family drivers
are able to search for.
<supply-name>-supply:
description: |
phandle to the regulator device tree node
optional "supply-name" is "vdd-0.8-cx-mx".
qcom,<supply>-config:
description: |
Specifies voltage levels for supply. Should be
specified in pairs (min, max), units uV. There can
be optional load in uA and Regulator settle delay in
uS.
qcom,icnss-vadc:
description: VADC handle for vph_pwr read APIs.
qcom,icnss-adc_tm:
description: VADC handle for vph_pwr notification APIs.
io-channels:
description: IIO channel to monitor for vph_pwr power.
io-channel-names:
description: IIO channel name as per the client name.
qcom,smmu-s1-bypass:
description: Boolean context flag to set SMMU to S1 bypass.
qcom,wlan-msa-fixed-region:
description: phandle, specifier pairs to children of /reserved-memory.
qcom,hyp_disabled:
description: Boolean context flag to disable hyperviser.
qcom,smp2p_map_wlan_1_in:
description: Represents the in smp2p to wlan driver from modem.
pin-ctrl-support:
description: Represents pin_ctrl support is present or not.
required:
- compatible
- reg
- reg-names
- interrupts
- qcom,wlan-msa-memory
- clocks
- clock-names
- iommus
- qcom,wlan-smmu-iova-address
- qcom,wlan
examples:
- |
qcom,icnss@0a000000 {
compatible = "qcom,icnss";
reg = <0x0a000000 0x1000000>;
reg-names = "membase";
clocks = <&clock_gcc clk_aggre2_noc_clk>;
clock-names = "smmu_aggre2_noc_clk";
iommus = <&anoc2_smmu 0x1900>,
<&anoc2_smmu 0x1901>;
qcom,wlan-smmu-iova-address = <0 0x10000000>;
qcom,wlan;
interrupts = <0 130 0 /* CE0 */ >,
<0 131 0 /* CE1 */ >,
<0 132 0 /* CE2 */ >,
<0 133 0 /* CE3 */ >,
<0 134 0 /* CE4 */ >,
<0 135 0 /* CE5 */ >,
<0 136 0 /* CE6 */ >,
<0 137 0 /* CE7 */ >,
<0 138 0 /* CE8 */ >,
<0 139 0 /* CE9 */ >,
<0 140 0 /* CE10 */ >,
<0 141 0 /* CE11 */ >;
qcom,wlan-msa-memory = <0x200000>;
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
qcom,smmu-s1-bypass;
vdd-0.8-cx-mx-supply = <&pm8998_l5>;
qcom,vdd-0.8-cx-mx-config = <800000 800000 2400 1000>;
qcom,hyp_disabled;
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
};
...

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "canoe-kiwi-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Canoe SoCs";
compatible = "qcom,canoe", "qcom,canoep", "qcom,canoe-mtp", "qcom,canoe-cdp";
qcom,msm-id = <0x294 0x10000>, <0x294 0x20000>, <0x295 0x10000>, <0x295 0x20000>,
<0x1000294 0x10000>, <0x1000294 0x20000>,
<0x1000295 0x10000>, <0x1000295 0x20000>,
<704 0x10000>, <704 0x20000>,
<0x10002C0 0x10000>, <0x10002C0 0x20000>;
qcom,board-id = <0x30001 0>, <0x20008 0>, <0x30015 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,canoe.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio18";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio19";
function = "wcn_sw";
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0x0 0xb0000000 0x0 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&pmh0104_gpios 5 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
platform-name-required;
vdd-wlan-aon-supply = <&L2G>;
qcom,vdd-wlan-aon-config = <1800000 1800000 30000 0 1>;
vdd-wlan-io12-supply = <&L3G>;
qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
vdd-wlan-cx-supply = <&S1J>;
qcom,vdd-wlan-cx-config = <968000 1000000 0 0 1>;
vdd-wlan-dig-supply = <&S2J>;
qcom,vdd-wlan-dig-config = <1012000 1100000 0 0 1>;
vdd-wlan-rfa1-supply = <&S8F>;
qcom,vdd-wlan-rfa1-config = <1900000 2000000 0 0 1>;
vdd-wlan-rfa2-supply = <&S7F>;
qcom,vdd-wlan-rfa2-config = <1352000 1400000 0 0 1>;
vdd-wlan-ant-share-supply = <&L3K>;
qcom,vdd-wlan-ant-share-config = <1200000 1200000 25 0 1>;
vdd-wlan-supply = <&S7G>;
qcom,vdd-wlan-config = <952000 1100000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 308000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 308000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 308000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 308000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3210000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3210000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 6450000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1610000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"S2J1", "bb",
"S1J1", "bb",
"S8F0", "rf",
"S7F0", "rf",
"S7G0", "rf";
qcom,pmu_vreg_map =
"VDD095_MX_PMU", "S2J1",
"VDD095_PMU", "S1J1",
"VDD_PMU_AON_I", "S7G0",
"VDD095_PMU_BT", "S7G0",
"VDD09_PMU_RFA_I", "S7G0",
"VDD13_PMU_PCIE_I", "S7F0",
"VDD13_PMU_RFA_I", "S7F0",
"VDD19_PMU_PCIE_I", "S8F0",
"VDD19_PMU_RFA_I", "S8F0";
qcom,pdc_init_table =
" {class: wlan_pdc, ss: rf, res: S8F0.v, upval: 1900}",
" {class: wlan_pdc, ss: rf, res: S8F0.v, dwnval: 1860}",
" {class: wlan_pdc, ss: rf, res: S7F0.v, upval: 1352}",
" {class: wlan_pdc, ss: rf, res: S7F0.v, dwnval: 988}",
" {class: wlan_pdc, ss: bb, res: S1J1.v, upval: 968}",
" {class: wlan_pdc, ss: bb, res: S1J1.v, dwnval: 460}",
" {class: wlan_pdc, ss: bb, res: S2J1.m, enable: 1}",
" {class: wlan_pdc, ss: bb, res: S2J1.v, enable: 1}",
" {class: wlan_pdc, ss: rf, res: S7G0.m, enable: 1}",
" {class: wlan_pdc, ss: rf, res: S7G0.v, enable: 1}";
qcom,pdc_mode_vote_table =
" {class: wlan_pdc, ss: rf, res: L3K1.m, enable: 1}",
" {class: wlan_pdc, ss: rf, res: L3K1.m, dwnval: 2}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
};
};
&pcie_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <2>;
#size-cells = <2>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from canoe-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-geometry = <0x0 0x98000000 0x0 0x18010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF",
"non-fatal";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "canoe-peach-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Canoe SoCs";
compatible = "qcom,canoe", "qcom,canoep";
qcom,msm-id = <0x294 0x10000>, <0x294 0x20000>, <0x295 0x10000>, <0x295 0x20000>,
<0x1000294 0x10000>, <0x1000294 0x20000>, <0x1000295 0x10000>,
<0x1000295 0x20000>, <704 0x10000>, <704 0x20000>,
<0x10002C0 0x10000>, <0x10002C0 0x20000>;
qcom,board-id = <1 0>, <0x20001 0>, <8 0>, <0x30008 0>, <0x40008 0>,
<0x50008 0>, <0x60008 0>, <0x21 0>, <11 0>, <0x2000B 0>,
<0x15 0>, <0x20015 0>, <0x30015 0>, <0x80008 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,canoe.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio18";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio19";
function = "wcn_sw";
};
};
cnss_host_sol_default: cnss_host_sol_default {
mux {
pins = "gpio204";
function = "gpio";
};
config {
pins = "gpio204";
drive-strength = <4>;
bias-pull-down;
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_peach: qcom,cnss-peach@b0000000 {
compatible = "qcom,cnss-peach";
reg = <0x0 0xb0000000 0x0 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x110E>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&pmh0104_gpios 5 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
wlan-host-sol-gpio = <&tlmm 204 0>;
wlan-dev-sol-gpio = <&tlmm 205 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx", "sol_default";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
pinctrl-4 = <&cnss_host_sol_default>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
msix-match-addr = <0x3000>;
platform-name-required;
vdd-wlan-aon-supply = <&L2G>;
qcom,vdd-wlan-aon-config = <1800000 1800000 30000 0 1>;
vdd-wlan-io12-supply = <&L3G>;
qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
vdd-wlan-cx-supply = <&S1J>;
qcom,vdd-wlan-cx-config = <892000 1000000 0 0 1>;
vdd-wlan-dig-supply = <&S2J>;
qcom,vdd-wlan-dig-config = <892000 1000000 0 0 1>;
vdd-wlan-rfa1-supply = <&S8F>;
qcom,vdd-wlan-rfa1-config = <1876000 2000000 0 0 1>;
vdd-wlan-rfa2-supply = <&S7F>;
qcom,vdd-wlan-rfa2-config = <1328000 1340000 0 0 1>;
vdd-wlan-ant-share-supply = <&L3K>;
qcom,vdd-wlan-ant-share-config = <1200000 1200000 25 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 308000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 308000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 308000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 308000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3210000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3210000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 6450000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1610000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"S1J1", "bb",
"S2J1", "rf",
"S7F0", "rf",
"S8F0", "rf";
qcom,pmu_vreg_map =
"VDDD_AON_0P9", "S2J1",
"VDDA_RFA_0P9", "S2J1",
"VDDA_RFA_1P9", "S8F0",
"VDDA_RFA_1P3", "S7F0",
"VDDD_WLMX_0P9", "S2J1",
"VDDD_WLCX_0P9", "S1J1",
"VDDD_BTCX_0P9", "S2J1",
"VDDD_BTCMX_0P9", "S2J1",
"VDDA_PCIE_0P9", "S7F0",
"VDDA_PCIE_1P2", "S7F0";
qcom,pdc_mode_vote_table =
" {class: wlan_pdc, ss: rf, res: L3K1.m, enable: 1}",
" {class: wlan_pdc, ss: rf, res: L3K1.m, dwnval: 2}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
};
wlan_direct_link: qcom,cnss-direct-link {
compatible = "qcom,cnss-direct-link";
iommus = <&apps_smmu 0x100f 0x0>;
qcom,iommu-group = <&cnss_audio_iommu_group0>;
memory-region = <&direct_link_iommu_region_partition>;
dma-coherent;
direct_link_iommu_region_partition: direct_link_iommu_region_partition {
iommu-addresses = <&wlan_direct_link 0x0 0x0 0x0 0x18000000>,
<&wlan_direct_link 0x0 0xb0000000 0x0 0x50000000>;
};
};
};
&pcie_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_audio_iommu_group0>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from canoe-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x18000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-qca6750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera ATP + MSL WLAN";
compatible = "qcom,kera-atp", "qcom,kera", "qcom,atp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x000021 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-qca6750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera CDP";
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,cdp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x010001 0>, <0x020001 0>, <0x030001 0>, <0x040001 0>, <0x50001 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-qca6750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera MTP";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,mtp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x010008 0>, <0x020008 0>, <0x030008 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-wcn7750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera MTP";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,mtp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x010008 1>, <0x020008 1>, <0x030008 1>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&tlmm {
icnss_sw_ctrl: icnss_sw_ctrl {
mux {
pins = "gpio81";
function = "wcn_sw_ctrl";
};
};
};
&soc {
qcom,smp2p-wpss {
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
qcom,entry-name = "wlan";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
qcom,entry-name = "wlan";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
qcom,entry-name = "wlan_soc_wake";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
qcom,entry-name = "wlan_soc_wake";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
qcom,entry-name = "wlan_ep_power_save";
#qcom,smem-state-cells = <1>;
};
};
icnss2: qcom,wcn6750 {
compatible = "qcom,wcn6750";
reg = <0x17110040 0x0>,
<0xc0000000 0x10000>;
reg-names = "msi_addr", "smmu_iova_ipa";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x1480 0x1>;
wlan-en-gpio = <35>;
host-sol-gpio = <33>;
dev-sol-gpio = <32>;
sw-ctrl-gpio = <81>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <81>;
pinctrl-names = "sw_ctrl";
pinctrl-0 = <&icnss_sw_ctrl>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,iommu-dma-addr-pool = <0xb0000000 0x10000000>;
qcom,iommu-geometry = <0xb0000000 0x10010000>;
dma-coherent;
pin-ctrl-support;
qcom,fw-prefix;
qcom,wlan;
tsens = "sys-therm-3";
wcn-hw-version = "qca6750";
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
vdd-cx-mx-supply = <&S3B>;
qcom,vdd-cx-mx-config = <920000 1040000 0 0 0>;
vdd-1.8-xo-supply = <&S1B>;
qcom,vdd-1.8-xo-config = <1856000 2040000 0 0 0>;
vdd-1.3-rfa-supply = <&S2B>;
qcom,vdd-1.3-rfa-config = <1256000 1408000 0 0 0>;
vdd-1.8-io-supply = <&L11B>;
qcom,vdd-1.8-io-config = <1800000 1800000 0 0 0>;
qcom,smem-states = <&smp2p_wlan_1_out 0>,
<&smp2p_wlan_2_out 0>,
<&smp2p_wlan_3_out 0>;
qcom,smem-state-names = "wlan-smp2p-out",
"wlan-soc-wake-smp2p-out",
"wlan-ep-powersave-smp2p-out";
qcom,qmp = <&aoss_qmp>;
qcom,vreg_ol_cpr ="s3b";
icnss_cdev_apss: icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: icnss_cdev2 {
#cooling-cells = <2>;
};
icnss_cdev_bw: icnss_cdev3 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
qcom,smp2p_map_wlan_2_in {
interrupts-extended = <&smp2p_wlan_2_in 0 0>;
interrupt-names = "qcom,smp2p-soc-wake-ack";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-wcn7750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera QRD";
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,qrd";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x01000B 0>, <0x02000B 0>, <0x03000B 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-qca6750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera RCM";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,rcm";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x010015 0>, <0x020015 0>, <0x030015 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-wcn7750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera RCM";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,rcm";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x010015 1>, <0x020015 1>, <0x030015 1>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,kera.h>
&tlmm {
icnss_sw_ctrl: icnss_sw_ctrl {
mux {
pins = "gpio81";
function = "wcn_sw_ctrl";
};
};
icnss_wlan_en_active: icnss_wlan_en_active {
mux {
pins = "gpio35";
function = "gpio";
};
config {
pins = "gpio35";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
icnss_wlan_en_sleep: icnss_wlan_en_sleep {
mux {
pins = "gpio35";
function = "gpio";
};
config {
pins = "gpio35";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
};
&soc {
qcom,smp2p-wpss {
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
qcom,entry-name = "wlan";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
qcom,entry-name = "wlan";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
qcom,entry-name = "wlan_soc_wake";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
qcom,entry-name = "wlan_soc_wake";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
qcom,entry-name = "wlan_ep_power_save";
#qcom,smem-state-cells = <1>;
};
};
wpss_pas: remoteproc-wpss@97000000 {
firmware-name = "wcn7750/wpss.mdt";
};
icnss2_direct_link_iommu_group0: icnss2_direct_link_iommu_group0 {
qcom,iommu-dma-addr-pool = <0xb0000000 0x10000000>;
qcom,iommu-geometry = <0xb0000000 0x10010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
};
icnss2: qcom,wcn7750 {
compatible = "qcom,wcn7750";
reg = <0x17110040 0x0>,
<0xc0000000 0x10000>;
reg-names = "msi_addr", "smmu_iova_ipa";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x1480 0x1>;
wlan-en-gpio = <35>;
host-sol-gpio = <33>;
dev-sol-gpio = <32>;
sw-ctrl-gpio = <81>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <81>;
pin_wlan-en-gpio = <&tlmm 35 0>;
pin_sw-ctrl-gpio = <&tlmm 81 0>;
pinctrl-names = "sw_ctrl", "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&icnss_sw_ctrl>;
pinctrl-1 = <&icnss_wlan_en_active>;
pinctrl-2 = <&icnss_wlan_en_sleep>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-group = <&icnss2_direct_link_iommu_group0>;
dma-coherent;
pin-ctrl-support;
qcom,fw-prefix;
qcom,wlan;
tsens = "sys-therm-3";
wcn-hw-version = "wcn7750";
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
vdd-cx-mx-supply = <&S3B>;
qcom,vdd-cx-mx-config = <880000 1040000 0 0 0>;
vdd-1.8-xo-supply = <&S1B>;
qcom,vdd-1.8-xo-config = <1856000 2040000 0 0 0>;
vdd-1.3-rfa-supply = <&S2B>;
qcom,vdd-1.3-rfa-config = <1256000 1408000 0 0 0>;
vdd-1.8-io-supply = <&L11B>;
qcom,vdd-1.8-io-config = <1800000 1800000 0 0 0>;
qcom,smem-states = <&smp2p_wlan_1_out 0>,
<&smp2p_wlan_2_out 0>,
<&smp2p_wlan_3_out 0>;
qcom,smem-state-names = "wlan-smp2p-out",
"wlan-soc-wake-smp2p-out",
"wlan-ep-powersave-smp2p-out";
qcom,pdc_init_table =
" {class: wlan_pdc, ss: rf, res: s3b.v, dwnval: 696}",
" {class: wlan_pdc, ss: rf, res: s1b.v, upval: 1864}",
" {class: wlan_pdc, ss: rf, res: s2b.v, upval: 1316}",
" {class: wlan_pdc, ss: rf, res: s4b.e, enable: 0}";
qcom,qmp = <&aoss_qmp>;
qcom,vreg_ol_cpr ="s3b";
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
/* ddr_type = 8(LPDDR5) */
ddr_cfg@0 {
ddr_type = <8>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 200 Mhz */
<175000 1600000>,
/* ultra high: DBS mode snoc/anoc: 200 Mhz */
<312500 1600000>,
/* super high: DBS mode snoc/anoc: 403 Mhz */
<587500 3224000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547 MHz */
<2250 2500800>,
/* low: 18-60 Mbps ddr: 547 MHz */
<7500 2500800>,
/* medium: 60-240 Mbps ddr: 547 MHz */
<30000 2500800>,
/* high: 240-1200 Mbps ddr: 547 MHz */
<100000 2500800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 7108800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 9566400>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 14569200>,
/* low (latency critical): 18-60 Mbps ddr: 547 MHz */
<7500 2500800>;
};
/* ddr_type = 7(LPDDR4) */
ddr_cfg@1 {
ddr_type = <7>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 200 Mhz */
<175000 1600000>,
/* ultra high: DBS mode snoc/anoc: 200 Mhz */
<312500 1600000>,
/* super high: DBS mode snoc/anoc: 403 Mhz */
<587500 3224000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547 MHz */
<2250 2500800>,
/* low: 18-60 Mbps ddr: 547 MHz */
<7500 2500800>,
/* medium: 60-240 Mbps ddr: 547 MHz */
<30000 2500800>,
/* high: 240-1200 Mbps ddr: 547 MHz */
<100000 2500800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 7108800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 9566400>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 14569200>,
/* low (latency critical): 18-60 Mbps ddr: 547 MHz */
<7500 2500800>;
};
icnss_cdev_apss: icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: icnss_cdev2 {
#cooling-cells = <2>;
};
icnss_cdev_bw: icnss_cdev3 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
qcom,smp2p_map_wlan_2_in {
interrupts-extended = <&smp2p_wlan_2_in 0 0>;
interrupt-names = "qcom,smp2p-soc-wake-ack";
};
};
wlan_direct_link: qcom,icnss-direct-link {
compatible = "qcom,icnss-direct-link";
iommus = <&apps_smmu 0x100f 0x0>;
qcom,iommu-group = <&icnss2_direct_link_iommu_group0>;
dma-coherent;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "parrot-wcn3990.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot ATP";
compatible = "qcom,parrot", "qcom,parrot-atp", "qcom,atp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>,
<713 0x10000>, <714 0x10000>;
qcom,board-id = <33 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "parrot-wcn3990.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot IDP";
compatible = "qcom,parrot", "qcom,parrot-idp", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>,
<713 0x10000>, <714 0x10000>;
qcom,board-id = <34 1>, <34 3>, <34 0x601>, <34 0x603>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "parrot-wcn6750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot IDP";
compatible = "qcom,parrot", "qcom,parrot-idp", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>,
<713 0x10000>, <714 0x10000>;
qcom,board-id = <34 0>, <34 2>, <34 4>, <34 0x600>, <34 0x602>, <34 0x604>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "parrot-wcn6755.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6755 IDP";
compatible = "qcom,parrot", "qcom,parrot-idp", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>,
<713 0x10000>, <714 0x10000>;
qcom,board-id = <34 5>, <34 6>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "parrot-wcn3990.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot QRD";
compatible = "qcom,parrot", "qcom,parrot-qrd", "qcom,qrd";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>,
<713 0x10000>, <714 0x10000>;
qcom,board-id = <0x1000B 0>, <0x1000B 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "parrot-wcn6750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot QRD";
compatible = "qcom,parrot", "qcom,parrot-qrd", "qcom,qrd";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>,
<713 0x10000>, <714 0x10000>;
qcom,board-id = <0x1000B 1>, <0x1000B 0x601>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "parrot-wcn6755.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6755 QRD";
compatible = "qcom,parrot", "qcom,parrot-qrd", "qcom,qrd";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>,
<713 0x10000>, <714 0x10000>;
qcom,board-id = <0x1000B 2>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "parrot-wcn3990.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot RUMI";
compatible = "qcom,parrot", "qcom,parrot-rumi", "qcom,rumi";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, <633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>;
qcom,board-id = <0x1000F 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
&reserved_memory {
wlan_fw_mem: wlan_fw_region@82a00000 {
no-map;
reg = <0x0 0x82a00000 0x0 0x300000>;
};
};
&soc {
wpss_pas: remoteproc-wpss@8a00000 {
firmware-name = "adrastea/wpss.mdt";
};
icnss: qcom,icnss@22800000 {
compatible = "qcom,icnss";
reg = <0x22800000 0x800000>;
reg-names = "membase";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x4c0 0x1>;
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10000000>;
qcom,fw-prefix;
qcom,wlan;
bdf-download-support;
wpss-support-enable;
qcom,wlan-msa-fixed-region = <&wlan_fw_mem>;
vdd-cx-mx-supply = <&L11B>;
vdd-1.8-xo-supply = <&L1E>;
vdd-1.3-rfa-supply = <&L14B>;
vdd-3.3-ch1-supply = <&L11E>;
vdd-3.3-ch0-supply = <&L10E>;
qcom,vdd-cx-mx-config = <0 0>;
qcom,vdd-3.3-ch1-config = <3000000 3312000>;
qcom,vdd-3.3-ch0-config = <3000000 3312000>;
qcom,smem-states = <&smp2p_wlan_1_out 0>;
qcom,smem-state-names = "wlan-smp2p-out";
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
qcom,smp2p-wpss {
smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
qcom,entry-name = "wlan_soc_wake";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
qcom,entry-name = "wlan_soc_wake";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
qcom,entry-name = "wlan_ep_power_save";
#qcom,smem-state-cells = <1>;
};
};
wpss_pas: remoteproc-wpss@8a00000 {
firmware-name = "qca6750/wpss.mdt";
};
icnss2: qcom,wcn6750 {
compatible = "qcom,wcn6750";
reg = <0x17210040 0x0>,
<0xb0000000 0x10000>;
reg-names = "msi_addr", "smmu_iova_ipa";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x1c00 0x1>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
dma-coherent;
qcom,fw-prefix;
qcom,wlan;
tsens = "quiet-therm";
qcom,wlan-msa-fixed-region = <&wlan_fw_mem>;
vdd-cx-mx-supply = <&S7B>;
qcom,vdd-cx-mx-config = <880000 1120000 0 0 1>;
vdd-1.8-xo-supply = <&S8E>;
qcom,vdd-1.8-xo-config = <1872000 2040000 0 0 0>;
vdd-1.3-rfa-supply = <&S8B>;
qcom,vdd-1.3-rfa-config = <1256000 1500000 0 0 0>;
qcom,smem-states = <&smp2p_wlan_1_out 0>,
<&smp2p_wlan_2_out 0>,
<&smp2p_wlan_3_out 0>;
qcom,smem-state-names = "wlan-smp2p-out",
"wlan-soc-wake-smp2p-out",
"wlan-ep-powersave-smp2p-out";
mboxes = <&qmp_aop 0>;
qcom,vreg_ol_cpr ="s7b";
icnss_cdev_apss: qcom,icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: qcom,icnss_cdev2 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
qcom,smp2p_map_wlan_2_in {
interrupts-extended = <&smp2p_wlan_2_in 0 0>;
interrupt-names = "qcom,smp2p-soc-wake-ack";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
qcom,smp2p-wpss {
smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
qcom,entry-name = "wlan_soc_wake";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
qcom,entry-name = "wlan_soc_wake";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
qcom,entry-name = "wlan_ep_power_save";
#qcom,smem-state-cells = <1>;
};
};
wpss_pas: remoteproc-wpss@8a00000 {
firmware-name = "qca6755/wpss.mdt";
};
icnss2: qcom,wcn6750 {
compatible = "qcom,wcn6750";
reg = <0x17210040 0x0>,
<0xb0000000 0x10000>;
reg-names = "msi_addr", "smmu_iova_ipa";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x1c00 0x1>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
dma-coherent;
qcom,fw-prefix;
qcom,wlan;
tsens = "quiet-therm";
wcn-hw-version = "qca6755";
qcom,wlan-msa-fixed-region = <&wlan_fw_mem>;
vdd-cx-mx-supply = <&S7B>;
qcom,vdd-cx-mx-config = <880000 1120000 0 0 1>;
vdd-1.8-xo-supply = <&S8E>;
qcom,vdd-1.8-xo-config = <1872000 2040000 0 0 0>;
vdd-1.3-rfa-supply = <&S8B>;
qcom,vdd-1.3-rfa-config = <1256000 1500000 0 0 0>;
qcom,smem-states = <&smp2p_wlan_1_out 0>,
<&smp2p_wlan_2_out 0>,
<&smp2p_wlan_3_out 0>;
qcom,smem-state-names = "wlan-smp2p-out",
"wlan-soc-wake-smp2p-out",
"wlan-ep-powersave-smp2p-out";
mboxes = <&qmp_aop 0>;
qcom,vreg_ol_cpr ="s7b";
icnss_cdev_apss: qcom,icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: qcom,icnss_cdev2 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
qcom,smp2p_map_wlan_2_in {
interrupts-extended = <&smp2p_wlan_2_in 0 0>;
interrupt-names = "qcom,smp2p-soc-wake-ack";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-kiwi-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple SoCs";
compatible = "qcom,pineapple", "qcom,pineapplep";
qcom,msm-id = <557 0x10000>, <577 0x10000>, <557 0x20000>, <577 0x20000>;
qcom,board-id = <1 0>, <8 0>, <11 0>, <0x15 0>, <0x1000B 0>, <0x10021 0>, <0x50001 0>, <0x50008 0>, <0x5000B 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,pineapple.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&tlmm 17 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
qcom,wlan-cbc-enabled;
cnss-enable-self-recovery;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
vdd-wlan-io-supply = <&L15B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
vdd-wlan-io12-supply = <&L3C>;
qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>;
vdd-wlan-supply = <&S4I>;
qcom,vdd-wlan-config = <940000 940000 0 0 1>;
vdd-wlan-aon-supply = <&S2C>;
qcom,vdd-wlan-aon-config = <976000 976000 0 0 1>;
vdd-wlan-dig-supply = <&S3C>;
qcom,vdd-wlan-dig-config = <916000 916000 0 0 1>;
vdd-wlan-rfa1-supply = <&S6C>;
qcom,vdd-wlan-rfa1-config = <1864000 1864000 0 0 1>;
vdd-wlan-rfa2-supply = <&S1C>;
qcom,vdd-wlan-rfa2-config = <1316000 1316000 0 0 1>;
vdd-wlan-ant-share-supply = <&L6K>;
qcom,vdd-wlan-ant-share-config = <1800000 1800000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 1600000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 1600000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 1600000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 1600000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 6448000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 6448000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 8528000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 3200000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s3c", "rf",
"l15B", "rf",
"l3c", "rf",
"s1c", "rf",
"s6c", "rf",
"s2c", "bb",
"s4i", "bb";
qcom,pmu_vreg_map =
"VDD095_MX_PMU", "s2c",
"VDD095_PMU", "s4i",
"VDD_PMU_AON_I", "s3c",
"VDD095_PMU_BT", "s3c",
"VDD09_PMU_RFA_I", "s3c",
"VDD13_PMU_PCIE_I", "s1c",
"VDD13_PMU_RFA_I", "s1c",
"VDD19_PMU_PCIE_I", "s6c",
"VDD19_PMU_RFA_I", "s6c";
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}",
"{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}",
"{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}",
"{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}",
"{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}",
"{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}",
"{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}",
"{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}",
"{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}",
"{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}";
};
};
&pcie0_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from pineapple-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-geometry = <0x98000000 0x18010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF",
"non-fatal";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapplep-hdk-kiwi-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. PineappleP HDK";
compatible = "qcom,pineapplep-hdk", "qcom,pineapplep", "qcom,hdk";
qcom,msm-id = <577 0x10000>, <577 0x20000>;
qcom,board-id = <0x1f 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,pineapple.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&tlmm 17 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
qcom,wlan-cbc-enabled;
cnss-enable-self-recovery;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
vdd-wlan-io-supply = <&L15B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
vdd-wlan-io12-supply = <&L3C>;
qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>;
vdd-wlan-supply = <&S4I>;
qcom,vdd-wlan-config = <940000 940000 0 0 1>;
vdd-wlan-aon-supply = <&S2C>;
qcom,vdd-wlan-aon-config = <976000 976000 0 0 1>;
vdd-wlan-dig-supply = <&S3C>;
qcom,vdd-wlan-dig-config = <916000 916000 0 0 1>;
vdd-wlan-rfa1-supply = <&S6C>;
qcom,vdd-wlan-rfa1-config = <1864000 1864000 0 0 1>;
vdd-wlan-rfa2-supply = <&S1C>;
qcom,vdd-wlan-rfa2-config = <1316000 1316000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 1600000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 1600000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 1600000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 1600000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 6448000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 6448000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 8528000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 3200000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s3c", "rf",
"l15B", "rf",
"l3c", "rf",
"s1c", "rf",
"s6c", "rf",
"s2c", "bb",
"s4i", "bb";
qcom,pmu_vreg_map =
"VDD095_MX_PMU", "s2c",
"VDD095_PMU", "s4i",
"VDD_PMU_AON_I", "s3c",
"VDD095_PMU_BT", "s3c",
"VDD09_PMU_RFA_I", "s3c",
"VDD13_PMU_PCIE_I", "s1c",
"VDD13_PMU_RFA_I", "s1c",
"VDD19_PMU_PCIE_I", "s6c",
"VDD19_PMU_RFA_I", "s6c";
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}",
"{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}",
"{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}",
"{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}",
"{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}",
"{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}",
"{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}",
"{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}",
"{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}",
"{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}";
};
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
"non-fatal";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
&reserved_memory {
wlan_msa_mem: wlan_msa_mem_region@82a00000 {
no-map;
reg = <0x0 0x82a00000 0x0 0x300000>;
};
};
&soc {
wpss_pas: remoteproc-wpss@8a00000 {
firmware-name = "adrastea/wpss.mdt";
};
icnss: qcom,icnss@22800000 {
compatible = "qcom,icnss";
reg = <0x22800000 0x800000>;
reg-names = "membase";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x4c0 0x1>;
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10000000>;
qcom,fw-prefix;
qcom,wlan;
bdf-download-support;
wpss-support-enable;
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
vdd-cx-mx-supply = <&L11B>;
vdd-1.8-xo-supply = <&L23B>;
vdd-1.3-rfa-supply = <&L14B>;
vdd-3.3-ch0-supply = <&L7E>;
qcom,vdd-cx-mx-config = <0 0>;
qcom,vdd-3.3-ch0-config = <3000000 3312000>;
qcom,smem-states = <&smp2p_wlan_1_out 0>;
qcom,smem-state-names = "wlan-smp2p-out";
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-adrastea.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin ATP";
compatible = "qcom,ravelin", "qcom,ravelin-atp", "qcom,atp";
qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>;
qcom,board-id = <33 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-adrastea.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>;
qcom,board-id = <34 0>, <34 0x601>, <34 2>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-adrastea.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,msm-id = <568 0x10000>, <581 0x10000>, <582 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>;
qcom,board-id = <0x1000B 0>, <0x1000B 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "sun-kiwi-cnss-v8.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp";
qcom,msm-id = <618 0x10000>, <618 0x20000>,
<639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x60001 0>, <0x50008 0>, <0x20015 0>, <0x60108 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,sun.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio18";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio19";
function = "wcn_sw";
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&pm8550ve_f_gpios 3 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
vdd-wlan-io-supply = <&L3F>;
qcom,vdd-wlan-io-config = <1800000 1800000 30000 0 1>;
vdd-wlan-io12-supply = <&L2F>;
qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
vdd-wlan-supply = <&S5F>;
qcom,vdd-wlan-config = <932000 1000000 0 0 1>;
vdd-wlan-aon-supply = <&S4D>;
qcom,vdd-wlan-aon-config = <976000 1036000 0 0 1>;
vdd-wlan-dig-supply = <&S1D>;
qcom,vdd-wlan-dig-config = <916000 1100000 0 0 1>;
vdd-wlan-rfa1-supply = <&S3G>;
qcom,vdd-wlan-rfa1-config = <1864000 2000000 0 0 1>;
vdd-wlan-rfa2-supply = <&S7I>;
qcom,vdd-wlan-rfa2-config = <1316000 1340000 0 0 1>;
vdd-wlan-ant-share-supply = <&L6K>;
qcom,vdd-wlan-ant-share-config = <1800000 1800000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3224000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3224000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 4264000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s5f", "bb",
"s4d", "bb",
"s3g", "rf",
"s7i", "rf",
"s1d", "rf";
qcom,pmu_vreg_map =
"VDD095_MX_PMU", "s4d",
"VDD095_PMU", "s5f",
"VDD_PMU_AON_I", "s1d",
"VDD095_PMU_BT", "s1d",
"VDD09_PMU_RFA_I", "s1d",
"VDD13_PMU_PCIE_I", "s7i",
"VDD13_PMU_RFA_I", "s7i",
"VDD19_PMU_PCIE_I", "s3g",
"VDD19_PMU_RFA_I", "s3g";
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s3g.v, upval: 1856}",
"{class: wlan_pdc, ss: rf, res: s3g.v, dwnval: 1844}",
"{class: wlan_pdc, ss: rf, res: s7i.v, upval: 1316}",
"{class: wlan_pdc, ss: rf, res: s7i.v, dwnval: 972}",
"{class: wlan_pdc, ss: rf, res: s1d.m, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s1d.v, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s1d.v, upval: 916}",
"{class: wlan_pdc, ss: rf, res: s1d.v, dwnval: 880}",
"{class: wlan_pdc, ss: bb, res: s4d.v, upval: 976}",
"{class: wlan_pdc, ss: bb, res: s4d.v, dwnval: 536}",
"{class: wlan_pdc, ss: bb, res: s5f.m, enable: 1}",
"{class: wlan_pdc, ss: bb, res: s5f.v, enable: 1}",
"{class: wlan_pdc, ss: bb, res: s5f.v, upval: 932}",
"{class: wlan_pdc, ss: bb, res: s5f.v, dwnval: 444}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
};
};
&pcie0_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-geometry = <0x98000000 0x18010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF",
"non-fatal";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "sun-kiwi-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp", "qcom,sun-mtp", "qcom,sun-cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x20001 0>, <0x20008 0>, <0x40015 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,sun.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio18";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio19";
function = "wcn_sw";
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&pm8550vs_f_gpios 3 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
vdd-wlan-io-supply = <&L3F>;
qcom,vdd-wlan-io-config = <1800000 1800000 30000 0 1>;
vdd-wlan-io12-supply = <&L2F>;
qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
vdd-wlan-supply = <&S4J>;
qcom,vdd-wlan-config = <932000 1000000 0 0 1>;
vdd-wlan-aon-supply = <&S4D>;
qcom,vdd-wlan-aon-config = <976000 1036000 0 0 1>;
vdd-wlan-dig-supply = <&S1D>;
qcom,vdd-wlan-dig-config = <916000 1100000 0 0 1>;
vdd-wlan-rfa1-supply = <&S3G>;
qcom,vdd-wlan-rfa1-config = <1864000 2000000 0 0 1>;
vdd-wlan-rfa2-supply = <&S7I>;
qcom,vdd-wlan-rfa2-config = <1316000 1340000 0 0 1>;
vdd-wlan-ant-share-supply = <&L6K>;
qcom,vdd-wlan-ant-share-config = <1800000 1800000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3224000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3224000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 4264000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s4j", "bb",
"s4d", "bb",
"s3g", "rf",
"s7i", "rf",
"s1d", "rf";
qcom,pmu_vreg_map =
"VDD095_MX_PMU", "s4d",
"VDD095_PMU", "s4j",
"VDD_PMU_AON_I", "s1d",
"VDD095_PMU_BT", "s1d",
"VDD09_PMU_RFA_I", "s1d",
"VDD13_PMU_PCIE_I", "s7i",
"VDD13_PMU_RFA_I", "s7i",
"VDD19_PMU_PCIE_I", "s3g",
"VDD19_PMU_RFA_I", "s3g";
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s3g.v, upval: 1856}",
"{class: wlan_pdc, ss: rf, res: s3g.v, dwnval: 1844}",
"{class: wlan_pdc, ss: rf, res: s7i.v, upval: 1316}",
"{class: wlan_pdc, ss: rf, res: s7i.v, dwnval: 972}",
"{class: wlan_pdc, ss: rf, res: s1d.m, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s1d.v, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s1d.v, upval: 916}",
"{class: wlan_pdc, ss: rf, res: s1d.v, dwnval: 880}",
"{class: wlan_pdc, ss: rf, res: s4j.m, enable: 0}",
"{class: wlan_pdc, ss: rf, res: s4j.v, enable: 0}",
"{class: wlan_pdc, ss: bb, res: s4d.v, upval: 976}",
"{class: wlan_pdc, ss: bb, res: s4d.v, dwnval: 536}",
"{class: wlan_pdc, ss: bb, res: s4j.m, enable: 1}",
"{class: wlan_pdc, ss: bb, res: s4j.v, enable: 1}",
"{class: wlan_pdc, ss: bb, res: s4j.v, upval: 932}",
"{class: wlan_pdc, ss: bb, res: s4j.v, dwnval: 444}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
};
};
&pcie0_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-geometry = <0x98000000 0x18010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF",
"non-fatal";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "sun-peach-cnss-v8.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp";
qcom,msm-id = <618 0x10000>, <618 0x20000>,
<639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x50001 0>, <0x40008 0>, <0x3000B 0>, <0x2000B 0>,
<0x30008 0>, <0x40001 0>, <0x30015 0>, <0x60008 0>,
<0x10021 0>, <0x3000B 1>, <0x40108 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,sun.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio18";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio19";
function = "wcn_sw";
};
};
cnss_host_sol_default: cnss_host_sol_default {
mux {
pins = "gpio202";
function = "gpio";
};
config {
pins = "gpio202";
drive-strength = <4>;
bias-pull-down;
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_peach: qcom,cnss-peach@b0000000 {
compatible = "qcom,cnss-peach";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x110E>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&pm8550ve_f_gpios 3 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
wlan-host-sol-gpio = <&tlmm 202 0>;
wlan-dev-sol-gpio = <&tlmm 203 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx", "sol_default";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
pinctrl-4 = <&cnss_host_sol_default>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
msix-match-addr = <0x3000>;
vdd-wlan-io-supply = <&L3F>;
qcom,vdd-wlan-io-config = <1800000 1800000 30000 0 1>;
vdd-wlan-io12-supply = <&L2F>;
qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
vdd-wlan-aon-supply = <&S4D>;
qcom,vdd-wlan-aon-config = <876000 1036000 0 0 1>;
vdd-wlan-dig-supply = <&S5F>;
qcom,vdd-wlan-dig-config = <876000 1000000 0 0 1>;
vdd-wlan-rfa1-supply = <&S3G>;
qcom,vdd-wlan-rfa1-config = <1860000 2000000 0 0 1>;
vdd-wlan-rfa2-supply = <&S7I>;
qcom,vdd-wlan-rfa2-config = <1312000 1340000 0 0 1>;
vdd-wlan-ant-share-supply = <&L6K>;
qcom,vdd-wlan-ant-share-config = <1800000 1860000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3224000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3224000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 4264000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s5f", "rf",
"s4d", "bb",
"s3g", "rf",
"s7i", "rf";
qcom,pmu_vreg_map =
"VDDD_AON_0P9", "s5f",
"VDDA_RFA_1P9", "s3g",
"VDDA_RFA_1P3", "s7i",
"VDDA_RFA_0P9", "s5f",
"VDDD_WLMX_0P9", "s4d",
"VDDD_WLCX_0P9", "s5f",
"VDDD_BTCX_0P9", "s5f",
"VDDD_BTCMX_0P9", "s5f",
"VDDA_PCIE_1P2", "s7i",
"VDDA_PCIE_0P9", "s7i";
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s5f.m, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s5f.v, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s5f.v, upval: 876}",
"{class: wlan_pdc, ss: rf, res: s5f.v, dwnval: 876}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
};
wlan_direct_link: qcom,cnss-direct-link {
compatible = "qcom,cnss-direct-link";
iommus = <&apps_smmu 0x100f 0x0>;
qcom,iommu-group = <&cnss_audio_iommu_group0>;
memory-region = <&direct_link_iommu_region_partition>;
dma-coherent;
direct_link_iommu_region_partition: direct_link_iommu_region_partition {
iommu-addresses = <&wlan_direct_link 0x00000000 0x18000000>,
<&wlan_direct_link 0xb0000000 0x50000000>;
};
};
};
&pcie0_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_audio_iommu_group0>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x18000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
};
};

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qcom/wlan/sun-peach-cnss.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "sun-peach-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp";
qcom,msm-id = <618 0x10000>, <618 0x20000>,
<639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <1 0>, <8 0>, <0x1000B 0>, <0x15 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,sun.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio16";
function = "gpio";
};
config {
pins = "gpio16";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio18";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio19";
function = "wcn_sw";
};
};
cnss_host_sol_default: cnss_host_sol_default {
mux {
pins = "gpio202";
function = "gpio";
};
config {
pins = "gpio202";
drive-strength = <4>;
bias-pull-down;
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_peach: qcom,cnss-peach@b0000000 {
compatible = "qcom,cnss-peach";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x110E>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&pm8550vs_f_gpios 3 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
wlan-host-sol-gpio = <&tlmm 202 0>;
wlan-dev-sol-gpio = <&tlmm 203 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx", "sol_default";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
pinctrl-4 = <&cnss_host_sol_default>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
msix-match-addr = <0x3000>;
vdd-wlan-io-supply = <&L3F>;
qcom,vdd-wlan-io-config = <1800000 1800000 30000 0 1>;
vdd-wlan-io12-supply = <&L2F>;
qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
vdd-wlan-aon-supply = <&S4D>;
qcom,vdd-wlan-aon-config = <876000 1036000 0 0 1>;
vdd-wlan-dig-supply = <&S4J>;
qcom,vdd-wlan-dig-config = <876000 1000000 0 0 1>;
vdd-wlan-rfa1-supply = <&S3G>;
qcom,vdd-wlan-rfa1-config = <1860000 2000000 0 0 1>;
vdd-wlan-rfa2-supply = <&S7I>;
qcom,vdd-wlan-rfa2-config = <1312000 1340000 0 0 1>;
vdd-wlan-ant-share-supply = <&L6K>;
qcom,vdd-wlan-ant-share-config = <1800000 1860000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3224000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3224000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 4264000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s4j", "rf",
"s4d", "bb",
"s3g", "rf",
"s7i", "rf";
qcom,pmu_vreg_map =
"VDDD_AON_0P9", "s4j",
"VDDA_RFA_1P9", "s3g",
"VDDA_RFA_1P3", "s7i",
"VDDA_RFA_0P9", "s4j",
"VDDD_WLMX_0P9", "s4d",
"VDDD_WLCX_0P9", "s4j",
"VDDD_BTCX_0P9", "s4j",
"VDDD_BTCMX_0P9", "s4j",
"VDDA_PCIE_1P2", "s7i",
"VDDA_PCIE_0P9", "s7i";
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s4j.m, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s4j.v, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s4j.v, upval: 876}",
"{class: wlan_pdc, ss: rf, res: s4j.v, dwnval: 876}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
};
wlan_direct_link: qcom,cnss-direct-link {
compatible = "qcom,cnss-direct-link";
iommus = <&apps_smmu 0x100f 0x0>;
qcom,iommu-group = <&cnss_audio_iommu_group0>;
memory-region = <&direct_link_iommu_region_partition>;
dma-coherent;
direct_link_iommu_region_partition: direct_link_iommu_region_partition {
iommu-addresses = <&wlan_direct_link 0x00000000 0x18000000>,
<&wlan_direct_link 0xb0000000 0x50000000>;
};
};
};
&pcie0_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_audio_iommu_group0>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x18000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "sunp-hdk-peach-cnss-v8.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs HDK";
compatible = "qcom,sunp-hdk", "qcom,sunp", "qcom,hdk";
qcom,msm-id = <639 0x10000>, <639 0x20000>, <618 0x10000>, <618 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x1001f 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-peach-cnss-v8.dtsi"
&wlan_peach {
/delete-property/ vdd-wlan-ant-share-supply;
/delete-property/ qcom,vdd-wlan-ant-share-config;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-kiwi-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna ATP + kiwi WLAN";
compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,atp", "qcom,tunap-atp",
"qcom,tunap";
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
qcom,board-id = <33 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-wcn7750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna CDP";
compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,cdp", "qcom,tunap-cdp",
"qcom,tunap";
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
qcom,board-id = <1 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,tuna.h>
&wlan_msa_mem {
status = "disabled";
};
&wpss_mem {
status = "disabled";
};
&wpss_pas {
status = "disabled";
};
&pcie0 {
status = "ok";
};
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio35";
function = "gpio";
};
config {
pins = "gpio35";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio35";
function = "gpio";
};
config {
pins = "gpio35";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio80";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio34";
function = "wcn_sw";
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 34 0>;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 35 0>;
qcom,bt-en-gpio = <&pm8550vs_g_gpios 4 0>;
qcom,sw-ctrl-gpio = <&tlmm 80 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <80 34>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
vdd-wlan-io-supply = <&L3G>;
qcom,vdd-wlan-io-config = <1800000 1800000 30000 0 1>;
vdd-wlan-io12-supply = <&L2G>;
qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
vdd-wlan-supply = <&S1G>;
qcom,vdd-wlan-config = <940000 1003000 0 0 1>;
vdd-wlan-dig-supply = <&S3B>;
qcom,vdd-wlan-dig-config = <976000 1040000 0 0 1>;
vdd-wlan-rfa1-supply = <&S1B>;
qcom,vdd-wlan-rfa1-config = <1864000 2104000 0 0 1>;
vdd-wlan-rfa2-supply = <&S2B>;
qcom,vdd-wlan-rfa2-config = <1316000 1408000 0 0 1>;
vdd-wlan-ant-share-supply = <&L6K>;
qcom,vdd-wlan-ant-share-config = <1800000 2000000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 400000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 400000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 400000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 400000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 1612000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 1612000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 2171000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 800000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8371200>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 14745600>,
/* low (latency critical): 18-60 Mbps ddr: 547 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s1g", "bb",
"s3b", "bb",
"s1b", "rf",
"s2b", "rf";
qcom,pmu_vreg_map =
"VDD095_MX_PMU", "s3b",
"VDD095_PMU", "s1g",
"VDD_PMU_AON_I", "s3b",
"VDD095_PMU_BT", "s3b",
"VDD09_PMU_RFA_I", "s3b",
"VDD13_PMU_PCIE_I", "s2b",
"VDD13_PMU_RFA_I", "s2b",
"VDD19_PMU_PCIE_I", "s1b",
"VDD19_PMU_RFA_I", "s1b";
qcom,pdc_init_table =
" {class: wlan_pdc, ss: rf, res: s3b.v, upval: 976}",
" {class: wlan_pdc, ss: rf, res: s3b.v, dwnval: 616}",
" {class: wlan_pdc, ss: rf, res: s1g.m, enable: 0}",
" {class: wlan_pdc, ss: rf, res: l18b.m, enable: 0}",
" {class: wlan_pdc, ss: rf, res: b1b.m, enable: 0}",
" {class: wlan_pdc, ss: rf, res: l4k.m, enable: 0}",
" {class: wlan_pdc, ss: rf, res: l2g.m, dwnval: 3}",
" {class: wlan_pdc, ss: bb, res: pdc, enable: 1}";
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
*/
wlan-txrx-intr-cpumask = <0x3 0x30>;
};
};
&pcie0_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region =
<&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition:
cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-geometry = <0x98000000 0x18010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF",
"non-fatal";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-kiwi-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,mtp", "qcom,tunap-mtp",
"qcom,tunap";
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
qcom,board-id = <8 2>, <8 3>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-wcn7750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP QMP1000";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,mtp", "qcom,tunap-mtp",
"qcom,tunap";
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
qcom,board-id = <8 1>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-wcn7750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,mtp", "qcom,tunap-mtp",
"qcom,tunap";
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
qcom,board-id = <8 0>, <8 4>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-wcn7750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna QRD";
compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,qrd", "qcom,tunap-qrd",
"qcom,tunap";
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
qcom,board-id = <11 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-kiwi-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna RCM + kiwi WLAN";
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,rcm", "qcom,tunap-rcm",
"qcom,tunap";
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
qcom,board-id = <21 1>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-wcn7750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna RCM";
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,rcm", "qcom,tunap-rcm",
"qcom,tunap";
qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>;
qcom,board-id = <21 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,tuna.h>
&tlmm {
icnss_sw_ctrl: icnss_sw_ctrl {
mux {
pins = "gpio80";
function = "wcn_sw_ctrl";
};
};
icnss_wlan_en_active: icnss_wlan_en_active {
mux {
pins = "gpio35";
function = "gpio";
};
config {
pins = "gpio35";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
icnss_wlan_en_sleep: icnss_wlan_en_sleep {
mux {
pins = "gpio35";
function = "gpio";
};
config {
pins = "gpio35";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
};
&soc {
qcom,smp2p-wpss {
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
qcom,entry-name = "wlan";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
qcom,entry-name = "wlan";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
qcom,entry-name = "wlan_soc_wake";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
qcom,entry-name = "wlan_soc_wake";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
qcom,entry-name = "wlan_ep_power_save";
#qcom,smem-state-cells = <1>;
};
};
icnss2_direct_link_iommu_group0: icnss2_direct_link_iommu_group0 {
qcom,iommu-dma-addr-pool = <0xb0000000 0x10000000>;
qcom,iommu-geometry = <0xb0000000 0x10010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
};
icnss2: qcom,wcn7750 {
compatible = "qcom,wcn7750";
reg = <0x17110040 0x0>,
<0xc0000000 0x10000>;
reg-names = "msi_addr", "smmu_iova_ipa";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x1400 0x1>;
wlan-en-gpio =<35>;
host-sol-gpio =<132>;
dev-sol-gpio =<32>;
sw-ctrl-gpio =<80>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <80>;
pin_wlan-en-gpio = <&tlmm 35 0>;
pin_sw-ctrl-gpio = <&tlmm 80 0>;
pinctrl-names = "sw_ctrl", "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&icnss_sw_ctrl>;
pinctrl-1 = <&icnss_wlan_en_active>;
pinctrl-2 = <&icnss_wlan_en_sleep>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-group = <&icnss2_direct_link_iommu_group0>;
dma-coherent;
pin-ctrl-support;
qcom,fw-prefix;
qcom,wlan;
tsens = "sys-therm-3";
wcn-hw-version = "wcn7750";
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
vdd-cx-mx-supply = <&S3B>;
qcom,vdd-cx-mx-config = <864000 1040000 0 0 0>;
vdd-1.8-xo-supply = <&S1B>;
qcom,vdd-1.8-xo-config = <1840000 2104000 0 0 0>;
vdd-1.3-rfa-supply = <&S2B>;
qcom,vdd-1.3-rfa-config = <1240000 1408000 0 0 0>;
vdd-1.8-io-supply = <&L3G>;
qcom,vdd-1.8-io-config = <1800000 1800000 0 0 0>;
vdd-1.2-io-supply = <&L2G>;
qcom,vdd-1.2-io-config = <1200000 1200000 0 0 0>;
qcom,smem-states = <&smp2p_wlan_1_out 0>,
<&smp2p_wlan_2_out 0>,
<&smp2p_wlan_3_out 0>;
qcom,smem-state-names = "wlan-smp2p-out",
"wlan-soc-wake-smp2p-out",
"wlan-ep-powersave-smp2p-out";
qcom,qmp = <&aoss_qmp>;
qcom,vreg_ol_cpr ="s3b";
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
/* ddr_type = 8(LPDDR5) */
ddr_cfg@0 {
ddr_type = <8>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 400000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 400000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 400000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 400000>,
/* very high: > 1200 Mbps snoc/anoc: 200 Mhz */
<175000 800000>,
/* ultra high: DBS mode snoc/anoc: 200 Mhz */
<312500 800000>,
/* super high: DBS mode snoc/anoc: 403 Mhz */
<587500 1612000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 800000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8371200>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 14745600>,
/* low (latency critical): 18-60 Mbps ddr: 2092 MHz */
<7500 8371200>;
};
icnss_cdev_apss: icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: icnss_cdev2 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
qcom,smp2p_map_wlan_2_in {
interrupts-extended = <&smp2p_wlan_2_in 0 0>;
interrupt-names = "qcom,smp2p-soc-wake-ack";
};
};
wlan_direct_link: qcom,icnss-direct-link {
compatible = "qcom,icnss-direct-link";
iommus = <&apps_smmu 0x100f 0x0>;
qcom,iommu-group = <&icnss2_direct_link_iommu_group0>;
dma-coherent;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "volcano-qca6750.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Volcano SoC";
compatible = "qcom,volcano";
qcom,msm-id = <636 0x10000>, <640 0x10000>, <0x4000291 0x10000>, <0x8000291 0x10000>, <0xc000291 0x10000>, <0x10000291 0x10000>, <0x4000292 0x10000>, <0x8000292 0x10000>, <0xc000292 0x10000>, <0x10000292 0x10000>;
qcom,board-id = <33 0>, <34 0>, <34 1>, <8 0>, <8 1>, <8 7>, <8 8>, <11 0>, <11 1>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
qcom,smp2p-wpss {
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
qcom,entry-name = "wlan";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
qcom,entry-name = "wlan";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
qcom,entry-name = "wlan_soc_wake";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
qcom,entry-name = "wlan_soc_wake";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
qcom,entry-name = "wlan_ep_power_save";
#qcom,smem-state-cells = <1>;
};
};
icnss2: qcom,wcn6750 {
compatible = "qcom,wcn6750";
reg = <0x17110040 0x0>,
<0xc0000000 0x10000>;
reg-names = "msi_addr", "smmu_iova_ipa";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x1400 0x1>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,iommu-dma-addr-pool = <0xb0000000 0x10000000>;
qcom,iommu-geometry = <0xb0000000 0x10010000>;
dma-coherent;
qcom,fw-prefix;
qcom,wlan;
tsens = "sys-therm-4";
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
vdd-cx-mx-supply = <&S3B>;
qcom,vdd-cx-mx-config = <968000 1040000 0 0 1>;
vdd-1.8-xo-supply = <&S1B>;
qcom,vdd-1.8-xo-config = <1856000 2040000 0 0 0>;
vdd-1.3-rfa-supply = <&S2B>;
qcom,vdd-1.3-rfa-config = <1256000 2050000 0 0 0>;
qcom,smem-states = <&smp2p_wlan_1_out 0>,
<&smp2p_wlan_2_out 0>,
<&smp2p_wlan_3_out 0>;
qcom,smem-state-names = "wlan-smp2p-out",
"wlan-soc-wake-smp2p-out",
"wlan-ep-powersave-smp2p-out";
qcom,qmp = <&aoss_qmp>;
qcom,vreg_ol_cpr ="s3b";
icnss_cdev_apss: qcom,icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: qcom,icnss_cdev2 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
qcom,smp2p_map_wlan_2_in {
interrupts-extended = <&smp2p_wlan_2_in 0 0>;
interrupt-names = "qcom,smp2p-soc-wake-ack";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "volcano6i-peach-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Volcano6I IOT SOC + Ganges/Brahma";
compatible = "qcom,volcano-idp", "qcom,volcano", "qcom,volcanop-idp",
"qcom,volcanop", "qcom,idp", "qcom,volcano-mtp",
"qcom,volcanop-mtp", "qcom,mtp";
qcom,msm-id = <0x4000291 0x10000>, <0x8000291 0x10000>, <0xc000291 0x10000>, <0x10000291 0x10000>, <0x4000292 0x10000>, <0x8000292 0x10000>, <0xc000292 0x10000>, <0x10000292 0x10000>;
qcom,board-id = <8 2>, <8 3>, <8 4>, <8 5>, <8 6>, <34 2>, <34 3>, <8 11>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,volcano.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio44";
function = "gpio";
};
config {
pins = "gpio44";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio44";
function = "gpio";
};
config {
pins = "gpio44";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
mux {
pins = "gpio45";
function = "wcn_sw_ctrl";
};
};
cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
mux {
pins = "gpio52";
function = "wcn_sw";
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&soc {
wlan_peach: qcom,cnss-peach@b0000000 {
compatible = "qcom,cnss-peach";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 52 0>;
supported-ids = <0x110E>;
wlan-en-gpio = <&tlmm 44 0>;
qcom,sw-ctrl-gpio = <&tlmm 45 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <45 52>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
"sw_ctrl_wl_cx";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_wlan_sw_ctrl>;
pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
qcom,wlan-cbc-enabled;
use-pm-domain;
qcom,same-dt-multi-dev;
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
vdd-wlan-io-supply = <&L1B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
vdd-wlan-io12-supply = <&L5B>;
qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>;
vdd-wlan-aon-supply = <&S1K>;
qcom,vdd-wlan-aon-config = <876000 1004000 0 0 0>;
vdd-wlan-dig-supply = <&S1L>;
qcom,vdd-wlan-dig-config = <876000 1000000 0 0 0>;
vdd-wlan-rfa1-supply = <&S1B>;
qcom,vdd-wlan-rfa1-config = <1860000 2000000 0 0 1>;
vdd-wlan-rfa2-supply = <&S2B>;
qcom,vdd-wlan-rfa2-config = <1312000 1340000 0 0 1>;
vdd-wlan-ant-share-supply = <&L18B>;
qcom,vdd-wlan-ant-share-config = <2800000 2800000 0 0 1>;
interconnects =
<&pcie_anoc MASTER_PCIE_0 &pcie_anoc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3224000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3224000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 4264000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s2b.v, dwnval: 1244}",
"{class: wlan_pdc, ss: rf, res: s3b.v, enable: 0}",
"{class: wlan_pdc, ss: rf, res: l5b.m, enable: 1}",
"{class: wlan_pdc, ss: rf, res: g1f.e, enable: 0}",
"{class: wlan_pdc, ss: rf, res: l1b.m, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s3b.m, enable: 0}",
"{class: wlan_pdc, ss: bb, res: pdc, enable: 1}";
};
};
&wpss_pas {
status = "disabled";
};
&wpss_mem {
status = "disabled";
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-dma-addr-pool = <0x98000000 0x18000000>;
qcom,iommu-geometry = <0x98000000 0x18001000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF",
"non-fatal";
};
};
};

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qcom/wlan/x1e80100-kiwi-cnss.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "x1e80100-kiwi-cnss.dtsi"
/ {
model = "Qualcomm Technologies, Inc. X1E80100 SoC";
compatible = "qcom,x1e80100";
qcom,msm-id = <0x22b 0x10000>, <0x22b 0x20000>;
qcom,board-id = <0x28 0x0>;
};

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qcom/wlan/x1e80100-kiwi-cnss.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,x1e80100.h>
&tlmm {
cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio117";
function = "gpio";
};
config {
pins = "gpio117";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio117";
function = "gpio";
};
config {
pins = "gpio117";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
};
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x4000000>;
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-cbc-enabled;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 117 0>;
qcom,bt-en-gpio = <&tlmm 116 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan;
qcom,wlan-rc-num = <4>;
qcom,wlan-ramdump-dynamic = <0x780000>;
cnss-enable-self-recovery;
use-pm-domain;
qcom,same-dt-multi-dev;
qcom,qmp = <&aoss_qmp>;
vdd-wlan-m2-supply = <&vreg_wlan_3p3>;
qcom,vdd-wlan-m2-config = <3300000 3300000 0 0 0>;
vdd-wlan-io-supply = <&L15B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 0>;
/* interconnect is not set */
};
};
&pcie4_rp {
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region =
<&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition:
cnss_pci0_iommu_region_partition {
iommu-addresses =
<&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
/* bypass due to SMMU V3 is NOT well supported yet */
qcom,iommu-dma = "bypass";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults =
"stall-disable", "HUPCF", "non-fatal";
};
};
};