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ARM: dts: msm: Add Qupv3 Q2SPI instance for SUN

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This change adds Q2SPI support on Qupv3_2 SE5 Instance.

Change-Id: I3af596d38e9997b6744f28e484f93325bbc613be
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
This commit is contained in:
Chandana Kishori Chiluveru
2023-10-26 19:46:11 +05:30
parent 7c6eec62b8
commit 96fb2799a5
2 changed files with 108 additions and 0 deletions
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82
qcom/sun-pinctrl.dtsi
View File

@@ -2509,6 +2509,88 @@
};
};
qupv3_se13_q2spi_pins: qupv3_se13_q2spi_pins {
qupv3_se13_q2spi_miso_active: qupv3_se13_q2spi_miso_active {
mux {
pins = "gpio20";
function = "qup2_se5_l0";
};
config {
pins = "gpio20";
drive-strength = <6>;
bias-disable;
};
};
qupv3_se13_q2spi_mosi_active: qupv3_se13_q2spi_mosi_active {
mux {
pins = "gpio21";
function = "qup2_se5_l1";
};
config {
pins = "gpio21";
drive-strength = <6>;
bias-pull-down;
};
};
qupv3_se13_q2spi_clk_active: qupv3_se13_q2spi_clk_active {
mux {
pins = "gpio22";
function = "qup2_se5_l2";
};
config {
pins = "gpio22";
drive-strength = <6>;
bias-pull-down;
};
};
qupv3_se13_q2spi_doorbell_active: qupv3_se13_q2spi_cs_active {
mux {
pins = "gpio23";
function = "qup2_se5_l6";
};
config {
pins = "gpio23";
drive-strength = <6>;
bias-pull-down;
};
};
qupv3_se13_q2spi_sleep: qupv3_se13_q2spi_sleep {
mux {
pins = "gpio21", "gpio22",
"gpio23";
function = "gpio";
};
config {
pins = "gpio21", "gpio22",
"gpio23";
drive-strength = <2>;
bias-pull-down;
};
};
qupv3_se13_q2spi_miso_sleep: qupv3_se13_q2spi_miso_sleep {
mux {
pins = "gpio20";
function = "gpio";
};
config {
pins = "gpio20";
drive-strength = <2>;
bias-disable;
};
};
};
qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
qupv3_se15_i2c_sda_active: qupv3_se15_i2c_sda_active {
mux {

26
qcom/sun-qupv3.dtsi
View File

@@ -954,6 +954,32 @@
status = "disabled";
};
/* Ganges UWB Q2SPI SE Instance */
qupv3_se13_q2spi: q2spi@894000 {
compatible = "qcom,q2spi-msm-geni";
reg = <0x894000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_q2spi_mosi_active>, <&qupv3_se13_q2spi_miso_active>,
<&qupv3_se13_q2spi_clk_active>, <&qupv3_se13_q2spi_doorbell_active>;
pinctrl-1 = <&qupv3_se13_q2spi_sleep>, <&qupv3_se13_q2spi_miso_sleep>;
dmas = <&gpi_dma2 0 5 14 64 0>,
<&gpi_dma2 1 5 14 64 0>;
dma-names = "tx", "rx";
q2spi-max-frequency = <10000000>;
status = "disabled";
};
/* HS UART Instance */
qupv3_se14_4uart: qcom,qup_uart@898000 {
compatible = "qcom,msm-geni-serial-hs";