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ARM: dts: msm: Add the "gcc_cfg_noc_pcie_anoc_ahb_clk" clock for tuna

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Add the "gcc_cfg_noc_pcie_anoc_ahb_clk" clock for tuna.

Change-Id: Ib023883dc4aac18e024aa8f0250de7aa5ad2b91a
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
This commit is contained in:
Paras Sharma
2024-10-22 17:52:13 +05:30
parent d1b840cb53
commit 960b39e2cc
1 changed files with 5 additions and 4 deletions
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9
qcom/tuna-pcie.dtsi
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@@ -94,6 +94,7 @@
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>, <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&pcie_0_pipe_clk>; <&pcie_0_pipe_clk>;
@@ -104,13 +105,13 @@
"pcie_rate_change_clk", "pcie_rate_change_clk",
"gcc_ddrss_pcie_sf_qtb_clk", "gcc_ddrss_pcie_sf_qtb_clk",
"pcie_aggre_noc_axi_clk", "pcie_aggre_noc_axi_clk",
"gcc_cnoc_pcie_sf_axi_clk", "pcie_0_pipe_div2_clk", "gcc_cnoc_pcie_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk",
"pcie_pipe_clk_mux", "pcie_0_pipe_div2_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src"; "pcie_pipe_clk_ext_src";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
<100000000>, <0>, <0>, <0>, <0>, <0>, <0>; <100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
<0>, <0>, <0>, <1>, <0>, <0>, <0>; <0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_0_BCR>, resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>; <&gcc GCC_PCIE_0_PHY_BCR>;