samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: msm: Remove coherent and voltage-level property in Ravelin

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Ravelin target doesn't support IO coherency.
So, remove the coherent property from storage nodes.

Don't vote for voltage for regulators shared between eMMC and UFS to be
in consistent with UFS design where regulator-min-microvolt and
regulator-max-microvolt properties are removed from regulator device
tree files for UFS regulators and to avoid below regulator API failures.

[3.198613] pm6450_l24: unsupportable voltage range: 2960000-0uV
[4.236846] sdhci_msm_vreg_set_voltage: regulator_set_voltage(vdd)failed.
min_uV=2960000,max_uV=2960000,ret=-22.

Change-Id: I780218b0903887e36589704af3e790a710932dd7
Signed-off-by: kamasali Satyanarayan <quic_kamasali@quicinc.com>
This commit is contained in:
kamasali Satyanarayan
2024-04-17 12:41:12 +05:30
committed by Kamasali Satyanarayan
parent 70e128cf60
commit 8e4ec07539
5 changed files with 10 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
qcom/ravelin-atp.dtsi
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@@ -56,7 +56,6 @@
&sdhc_2 { &sdhc_2 {
status = "ok"; status = "ok";
vdd-supply = <&L24B>; vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>; qcom,vdd-current-level = <0 800000>;
/* /*

1
qcom/ravelin-idp.dtsi
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@@ -105,7 +105,6 @@
&sdhc_2 { &sdhc_2 {
status = "ok"; status = "ok";
vdd-supply = <&L24B>; vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>; qcom,vdd-current-level = <0 800000>;
/* /*

1
qcom/ravelin-qrd.dtsi
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@@ -56,7 +56,6 @@
&sdhc_2 { &sdhc_2 {
status = "ok"; status = "ok";
vdd-supply = <&L24B>; vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>; qcom,vdd-current-level = <0 800000>;
/* /*

1
qcom/ravelin-rumi.dtsi
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@@ -156,7 +156,6 @@
&sdhc_2 { &sdhc_2 {
status = "ok"; status = "ok";
vdd-supply = <&L24B>; vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>; qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&L28B>; vdd-io-supply = <&L28B>;

23
qcom/ravelin.dtsi
View File

@@ -1736,6 +1736,11 @@
reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>,
<0x007C8000 0x8000>, <0x007D0000 0x9000>; <0x007C8000 0x8000>, <0x007D0000 0x9000>;
reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm"; reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm";
iommus = <&apps_smmu 0x560 0x0>;
qcom,iommu-dma = "fastmap";
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
@@ -1765,6 +1770,11 @@
qcom,ice-clk-rates = <300000000 100000000>; qcom,ice-clk-rates = <300000000 100000000>;
interconnects = <&aggre2_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc1_opp_table>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x000F642C 0x0 0x01 qcom,dll-hsr-list = <0x000F642C 0x0 0x01
0x2C010800 0x80040868>; 0x2C010800 0x80040868>;
@@ -1773,18 +1783,6 @@
resets = <&gcc GCC_SDCC1_BCR>; resets = <&gcc GCC_SDCC1_BCR>;
reset-names = "core_reset"; reset-names = "core_reset";
iommus = <&apps_smmu 0x560 0x0>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
interconnects = <&aggre2_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc1_opp_table>;
qos0 { qos0 {
mask = <0x03>; mask = <0x03>;
vote = <44>; vote = <44>;
@@ -1837,7 +1835,6 @@
0x2C010800 0x80040868>; 0x2C010800 0x80040868>;
iommus = <&apps_smmu 0x140 0x0>; iommus = <&apps_smmu 0x140 0x0>;
dma-coherent;
qcom,iommu-dma = "fastmap"; qcom,iommu-dma = "fastmap";
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;