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ARM: dts: msm: kera: Add capacity and DPC properties

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The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy model which in turn is used by EAS to take
placement decisions.

Change-Id: I6397ed3038d60fde457297fe3e015c2d5aaaa6a8
Signed-off-by: Atul Pant <quic_atulpant@quicinc.com>
This commit is contained in:
Atul Pant
2024-11-21 23:54:44 +05:30
parent 8b1c694a87
commit 8a7de6048a
1 changed files with 16 additions and 0 deletions
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16
qcom/kera.dtsi
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@@ -101,6 +101,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <1024>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -122,6 +124,8 @@
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
next-level-cache = <&L2_0>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -135,6 +139,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <1024>;
L2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -152,6 +158,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
dynamic-power-coefficient = <263>;
capacity-dmips-mhz = <1566>;
L2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -169,6 +177,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
dynamic-power-coefficient = <263>;
capacity-dmips-mhz = <1566>;
L2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -186,6 +196,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
dynamic-power-coefficient = <263>;
capacity-dmips-mhz = <1566>;
L2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -203,6 +215,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
dynamic-power-coefficient = <263>;
capacity-dmips-mhz = <1566>;
L2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -220,6 +234,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
dynamic-power-coefficient = <289>;
capacity-dmips-mhz = <1607>;
L2_7: l2-cache {
compatible = "cache";
cache-level = <2>;