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Merge "ARM: dts: msm: add spi, i2c, gpi nodes for SVM SUN"

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qctecmdr
2024-01-18 15:29:25 -08:00
committed by Gerrit - the friendly Code Review server
parent 5a7340943e 23738ec11d
commit 77d9a2c08a
2 changed files with 171 additions and 4 deletions
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8
qcom/sun-qupv3.dtsi
View File

@@ -1025,8 +1025,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>;
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
dmas = <&gpi_dma2 0 7 3 64 0>,
<&gpi_dma2 1 7 3 64 0>;
dmas = <&gpi_dma2 0 7 3 64 2>,
<&gpi_dma2 1 7 3 64 2>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1050,8 +1050,8 @@
pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>,
<&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>;
pinctrl-1 = <&qupv3_se15_spi_sleep>;
dmas = <&gpi_dma2 0 7 1 64 0>,
<&gpi_dma2 1 7 1 64 0>;
dmas = <&gpi_dma2 0 7 1 64 2>,
<&gpi_dma2 1 7 1 64 2>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";

167
qcom/sun-vm.dtsi
View File

@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
/ {
@@ -104,6 +105,16 @@
vm-attrs = "crash-fatal", "context-dump";
iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>;
/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
* QUP1_SE4: GPII5 : IRQ_316
* QUP2_SE7: GPII5 : IRQ_625
*/
gic-irq-ranges = <316 316
625 625>; /* PVM->SVM IRQ transfer */
memory {
#address-cells = <0x2>;
#size-cells = <0x0>;
@@ -432,6 +443,162 @@
msgq-label = <3>;
};
/*
* QUP1 : SE4 - Primary touch
* QUP2 : SE7 - Secondary touch
*/
qup_iommu_group: qup_common_iommu_group {
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
};
/* QUPv3_1 GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0xa00000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,static-gpii-mask = <0x20>;
qcom,gpii-mask = <0x0>;
qcom,ev-factor = <1>;
qcom,gpi-ee-offset = <0x10000>;
qcom,le-vm;
status = "ok";
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
/* Touchscreen I2C Instance */
qupv3_se4_i2c: i2c@a90000 {
compatible = "qcom,i2c-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma1 0 4 3 64 0xc>,
<&gpi_dma1 1 4 3 64 0xc>;
dma-names = "tx", "rx";
qcom,le-vm;
status = "disabled";
};
/* Touchscreen SPI Instance */
qupv3_se4_spi: spi@a90000 {
compatible = "qcom,spi-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma1 0 4 1 64 0xc>,
<&gpi_dma1 1 4 1 64 0xc>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,le-vm;
status = "disabled";
};
};
/* QUPv3_2 GPI Instance */
gpi_dma2: qcom,gpi-dma@800000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x800000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,static-gpii-mask = <0x20>;
qcom,gpii-mask = <0x0>;
qcom,ev-factor = <1>;
qcom,gpi-ee-offset = <0x10000>;
qcom,le-vm;
status = "ok";
};
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
/* Secondary Tounch */
qupv3_se15_i2c: i2c@89c000 {
compatible = "qcom,i2c-geni";
reg = <0x89c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma2 0 7 3 64 0xc>,
<&gpi_dma2 1 7 3 64 0xc>;
dma-names = "tx", "rx";
qcom,le-vm;
status = "disabled";
};
/* Secondary Tounch */
qupv3_se15_spi: spi@89c000 {
compatible = "qcom,spi-geni";
reg = <0x89c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma2 0 7 1 64 0xc>,
<&gpi_dma2 1 7 1 64 0xc>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,le-vm;
status = "disabled";
};
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};