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Merge "ARM: dts: msm: Add support for VIDEO clock controller on KERA"

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This commit is contained in:
QCTECMDR Service
2024-10-21 21:01:55 -07:00
committed by Gerrit - the friendly Code Review server
parent 45e36b8aeb 8aa0642122
commit 775fc046b0
2 changed files with 52 additions and 16 deletions
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2
bindings/clock/qcom,gpucc.yaml
View File

@@ -27,6 +27,7 @@ description: |
dt-bindings/clock/qcom,gpucc-parrot.h
dt-bindings/clock/qcom,gpucc-monaco.h
dt-bindings/clock/qcom,gpucc-tuna.h
dt-bindings/clock/qcom,gpucc-kera.h
properties:
compatible:
@@ -45,6 +46,7 @@ properties:
- qcom,parrot-gpucc
- qcom,monaco-gpucc
- qcom,tuna-gpucc
- qcom,kera-gpucc
clocks:
items:

66
qcom/kera.dtsi
View File

@@ -1132,8 +1132,27 @@
};
gcc: clock-controller@100000 {
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
compatible = "qcom,kera-gcc", "syscon";
reg = <0x100000 0x1f4200>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&pcie_0_pipe_clk>,
<&pcie_1_pipe_clk>,
<&sleep_clk>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo",
"pcie_0_pipe_clk",
"pcie_1_pipe_clk",
"sleep_clk",
"ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk",
"ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -1146,15 +1165,27 @@
};
tcsrcc: clock-controller@1f40000 {
compatible = "qcom,dummycc";
clock-output-names = "tcsrcc_clocks";
compatible = "qcom,kera-tcsrcc", "syscon";
reg = <0x1fbf000 0x20>;
reg-name = "cc_base";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,dummycc";
clock-output-names = "videocc_clocks";
compatible = "qcom,tuna-videocc", "syscon";
reg = <0xaaf0000 0x10000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_CX_LEVEL>;
vdd_mxc-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk",
"iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -1366,42 +1397,42 @@
};
&gcc_pcie_0_gdsc {
compatible = "regulator-fixed";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_pcie_0_phy_gdsc {
compatible = "regulator-fixed";
parent-supply = <&VDD_MX_LEVEL>;
status = "ok";
};
&gcc_pcie_1_gdsc {
compatible = "regulator-fixed";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_pcie_1_phy_gdsc {
compatible = "regulator-fixed";
parent-supply = <&VDD_MX_LEVEL>;
status = "ok";
};
&gcc_ufs_mem_phy_gdsc {
compatible = "regulator-fixed";
parent-supply = <&VDD_MX_LEVEL>;
status = "ok";
};
&gcc_ufs_phy_gdsc {
compatible = "regulator-fixed";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_usb30_prim_gdsc {
compatible = "regulator-fixed";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_usb3_phy_gdsc {
compatible = "regulator-fixed";
parent-supply = <&VDD_MX_LEVEL>;
status = "ok";
};
@@ -1421,12 +1452,15 @@
};
&video_cc_mvs0_gdsc {
compatible = "regulator-fixed";
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
status = "ok";
};
&video_cc_mvs0c_gdsc {
compatible = "regulator-fixed";
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};