From 57d974a17610aad69811c6ba4401024eb8ea65bc Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Mon, 17 Jun 2024 16:03:10 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Add support for GCC and TCSRCC on Kera Add support for GCC and TCSRCC on Kera platform. While at it, move the corresponding GDSC's to real. Change-Id: I1ecf7e1ec14afc71a9fc228c636668d9052ba14b Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 44 ++++++++++++++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 9dcb25d5..f4f395d9 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1132,8 +1132,27 @@ }; gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,kera-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk", + "sleep_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1146,8 +1165,9 @@ }; tcsrcc: clock-controller@1f40000 { - compatible = "qcom,dummycc"; - clock-output-names = "tcsrcc_clocks"; + compatible = "qcom,kera-tcsrcc", "syscon"; + reg = <0x1fbf000 0x20>; + reg-name = "cc_base"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1366,42 +1386,42 @@ }; &gcc_pcie_0_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_pcie_0_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_pcie_1_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_pcie_1_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_ufs_mem_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_ufs_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb30_prim_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb3_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; From cbf54b8fbf9db94a8c013dd636f02c58feba0f49 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Tue, 23 Jul 2024 16:20:08 +0530 Subject: [PATCH 2/3] dt-bindings: clock: qcom: add GPU clock controller bindings on kera Add GPU clock controller bindings on kera device. Change-Id: I64ce64a93077f9699a559e76865fa09d571a4f36 Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,gpucc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index ccdb4c98..2411e3c0 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -27,6 +27,7 @@ description: | dt-bindings/clock/qcom,gpucc-parrot.h dt-bindings/clock/qcom,gpucc-monaco.h dt-bindings/clock/qcom,gpucc-tuna.h + dt-bindings/clock/qcom,gpucc-kera.h properties: compatible: @@ -45,6 +46,7 @@ properties: - qcom,parrot-gpucc - qcom,monaco-gpucc - qcom,tuna-gpucc + - qcom,kera-gpucc clocks: items: From 8aa06421222e1040022bdd330806ccd9c712d8d4 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Fri, 28 Jun 2024 17:54:22 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Add support for VIDEO clock controller on KERA Add support for VIDEO clock controller and move corresponding gdsc's from dummy to real on Kera platform. Change-Id: I830ceb12fb979613401859313518d9e4de67e674 Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index f4f395d9..623e878f 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1173,8 +1173,19 @@ }; videocc: clock-controller@aaf0000 { - compatible = "qcom,dummycc"; - clock-output-names = "videocc_clocks"; + compatible = "qcom,tuna-videocc", "syscon"; + reg = <0xaaf0000 0x10000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_CX_LEVEL>; + vdd_mxc-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1441,12 +1452,15 @@ }; &video_cc_mvs0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; &video_cc_mvs0c_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; };