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ARM: dts: msm: Add support for 1150MHz frequency in Kera GPU

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Add support for 1150MHz frequency (Turbo L2) in Kera GPU.

Change-Id: Ibe95ea6dbfaae4090879d59e45d746ce94eff096
Signed-off-by: Kaushal Sanadhya <quic_ksanadhy@quicinc.com>
This commit is contained in:
Kaushal Sanadhya
2025-01-06 12:20:35 +05:30
committed by Sanjay Kumar Yadav
parent 9f996a9f8e
commit 7633c0c31d
1 changed files with 34 additions and 19 deletions
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53
gpu/kera-gpu-pwrlevels.dtsi
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@@ -1,10 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
&msm_gpu { &msm_gpu {
qcom,initial-pwrlevel = <7>; qcom,initial-pwrlevel = <8>;
/* Power levels */ /* Power levels */
qcom,gpu-pwrlevels { qcom,gpu-pwrlevels {
@@ -13,9 +13,24 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
/* Turbo_L1 */ /* Turbo_L2 */
qcom,gpu-pwrlevel@0 { qcom,gpu-pwrlevel@0 {
reg = <0>; reg = <0>;
qcom,gpu-freq = <1150000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
qcom,bus-freq-ddr7 = <10>;
qcom,bus-min-ddr7 = <10>;
qcom,bus-max-ddr7 = <10>;
qcom,bus-freq-ddr8 = <9>;
qcom,bus-min-ddr8 = <8>;
qcom,bus-max-ddr8 = <10>;
};
/* Turbo_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1075000000>; qcom,gpu-freq = <1075000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
@@ -29,8 +44,8 @@
}; };
/* Turbo */ /* Turbo */
qcom,gpu-pwrlevel@1 { qcom,gpu-pwrlevel@2 {
reg = <1>; reg = <2>;
qcom,gpu-freq = <975000000>; qcom,gpu-freq = <975000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>; qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
@@ -44,8 +59,8 @@
}; };
/* Nom_L1 */ /* Nom_L1 */
qcom,gpu-pwrlevel@2 { qcom,gpu-pwrlevel@3 {
reg = <2>; reg = <3>;
qcom,gpu-freq = <900000000>; qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@@ -59,8 +74,8 @@
}; };
/* Nom */ /* Nom */
qcom,gpu-pwrlevel@3 { qcom,gpu-pwrlevel@4 {
reg = <3>; reg = <4>;
qcom,gpu-freq = <796000000>; qcom,gpu-freq = <796000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -74,8 +89,8 @@
}; };
/* SVS_L2 */ /* SVS_L2 */
qcom,gpu-pwrlevel@4 { qcom,gpu-pwrlevel@5 {
reg = <4>; reg = <5>;
qcom,gpu-freq = <724000000>; qcom,gpu-freq = <724000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -89,8 +104,8 @@
}; };
/* SVS_L1 */ /* SVS_L1 */
qcom,gpu-pwrlevel@5 { qcom,gpu-pwrlevel@6 {
reg = <5>; reg = <6>;
qcom,gpu-freq = <645000000>; qcom,gpu-freq = <645000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -104,8 +119,8 @@
}; };
/* SVS */ /* SVS */
qcom,gpu-pwrlevel@6 { qcom,gpu-pwrlevel@7 {
reg = <6>; reg = <7>;
qcom,gpu-freq = <515000000>; qcom,gpu-freq = <515000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -119,8 +134,8 @@
}; };
/* Low_SVS */ /* Low_SVS */
qcom,gpu-pwrlevel@7 { qcom,gpu-pwrlevel@8 {
reg = <7>; reg = <8>;
qcom,gpu-freq = <345000000>; qcom,gpu-freq = <345000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -134,8 +149,8 @@
}; };
/* Low_SVS_D1 */ /* Low_SVS_D1 */
qcom,gpu-pwrlevel@8 { qcom,gpu-pwrlevel@9 {
reg = <8>; reg = <9>;
qcom,gpu-freq = <259000000>; qcom,gpu-freq = <259000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;