From 7633c0c31d0dd26888f36330a4bf3d86a4eb18c4 Mon Sep 17 00:00:00 2001
From: Kaushal Sanadhya <quic_ksanadhy@quicinc.com>
Date: Mon, 6 Jan 2025 12:20:35 +0530
Subject: [PATCH] ARM: dts: msm: Add support for 1150MHz frequency in Kera GPU

Add support for 1150MHz frequency (Turbo L2) in Kera GPU.

Change-Id: Ibe95ea6dbfaae4090879d59e45d746ce94eff096
Signed-off-by: Kaushal Sanadhya <quic_ksanadhy@quicinc.com>
---
 gpu/kera-gpu-pwrlevels.dtsi | 53 ++++++++++++++++++++++++-------------
 1 file changed, 34 insertions(+), 19 deletions(-)

diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi
index bba8f52f..a84af42e 100644
--- a/gpu/kera-gpu-pwrlevels.dtsi
+++ b/gpu/kera-gpu-pwrlevels.dtsi
@@ -1,10 +1,10 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 &msm_gpu {
-	qcom,initial-pwrlevel = <7>;
+	qcom,initial-pwrlevel = <8>;
 
 	/* Power levels */
 	qcom,gpu-pwrlevels {
@@ -13,9 +13,24 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		/* Turbo_L1 */
+		/* Turbo_L2 */
 		qcom,gpu-pwrlevel@0 {
 			reg = <0>;
+			qcom,gpu-freq = <1150000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+
+			qcom,bus-freq-ddr7 = <10>;
+			qcom,bus-min-ddr7 = <10>;
+			qcom,bus-max-ddr7 = <10>;
+
+			qcom,bus-freq-ddr8 = <9>;
+			qcom,bus-min-ddr8 = <8>;
+			qcom,bus-max-ddr8 = <10>;
+		};
+
+		/* Turbo_L1 */
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
 			qcom,gpu-freq = <1075000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 
@@ -29,8 +44,8 @@
 		};
 
 		/* Turbo */
-		qcom,gpu-pwrlevel@1 {
-			reg = <1>;
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
 			qcom,gpu-freq = <975000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
 
@@ -44,8 +59,8 @@
 		};
 
 		/* Nom_L1 */
-		qcom,gpu-pwrlevel@2 {
-			reg = <2>;
+		qcom,gpu-pwrlevel@3 {
+			reg = <3>;
 			qcom,gpu-freq = <900000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 
@@ -59,8 +74,8 @@
 		};
 
 		/* Nom */
-		qcom,gpu-pwrlevel@3 {
-			reg = <3>;
+		qcom,gpu-pwrlevel@4 {
+			reg = <4>;
 			qcom,gpu-freq = <796000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
@@ -74,8 +89,8 @@
 		};
 
 		/* SVS_L2 */
-		qcom,gpu-pwrlevel@4 {
-			reg = <4>;
+		qcom,gpu-pwrlevel@5 {
+			reg = <5>;
 			qcom,gpu-freq = <724000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
@@ -89,8 +104,8 @@
 		};
 
 		/* SVS_L1 */
-		qcom,gpu-pwrlevel@5 {
-			reg = <5>;
+		qcom,gpu-pwrlevel@6 {
+			reg = <6>;
 			qcom,gpu-freq = <645000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
@@ -104,8 +119,8 @@
 		};
 
 		/* SVS */
-		qcom,gpu-pwrlevel@6 {
-			reg = <6>;
+		qcom,gpu-pwrlevel@7 {
+			reg = <7>;
 			qcom,gpu-freq = <515000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
 
@@ -119,8 +134,8 @@
 		};
 
 		/* Low_SVS */
-		qcom,gpu-pwrlevel@7 {
-			reg = <7>;
+		qcom,gpu-pwrlevel@8 {
+			reg = <8>;
 			qcom,gpu-freq = <345000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 
@@ -134,8 +149,8 @@
 		};
 
 		/* Low_SVS_D1 */
-		qcom,gpu-pwrlevel@8 {
-			reg = <8>;
+		qcom,gpu-pwrlevel@9 {
+			reg = <9>;
 			qcom,gpu-freq = <259000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;