Merge remote-tracking branch 'quic/display-kernel-dev.lnx.1.0' into display-kernel.lnx.11.0
CRs SHA_ID Commit Message ---------------------------------------------------------------------- 3674590 I43968733 ARM: dts: msm: add SMMU_PROXY_DISPLAY_CB to MDP device in sun target 3674590 Ifa248132 ARM: dts: msm: enable idle-pc on sun target 3674524 Ie755d57d ARM: dts: msm: dsi: support LCD panels 3674523 I8e1652b0 ARM: dts: msm: increase LPM load current for L13B rail 3674521 I260ae895 ARM: dts: msm: dsi: add power supply for CSOT CPHY 3663901 Idabce49d ARM: dts: msm: add DSI nodes to connectors list for sun 3662802 I473dbca3 ARM: dts: msm: dsi: enable sun platforms 3663892 Ifa8b5904 ARM: dts: msm: dsi: add legacy panels CRs-Included: 3663892,3674523,3674590,3674521,3663901,3674524,3662802 Change-Id: Ib98b10a7babbbd188dfb05d8e36f1bdb926d50c6 Signed-off-by: Linux Display <lnxdisplay@localhost>
This commit is contained in:
2
Kbuild
2
Kbuild
@@ -1,4 +1,6 @@
|
||||
dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
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||||
display/sun-sde-display-cdp-overlay.dtbo \
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display/sun-sde-display-mtp-overlay.dtbo \
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||||
display/sun-sde-display-rumi-overlay.dtbo
|
||||
|
||||
always-y := $(dtb-y) $(dtbo-y)
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||||
|
96
display/dsi-panel-sharp-dsc-4k-cmd.dtsi
Normal file
96
display/dsi-panel-sharp-dsc-4k-cmd.dtsi
Normal file
@@ -0,0 +1,96 @@
|
||||
&mdss_mdp {
|
||||
dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd {
|
||||
qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0 1>;
|
||||
qcom,dsi-phy-num = <0 1>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
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||||
qcom,mdss-pan-physical-width-dimension = <71>;
|
||||
qcom,mdss-pan-physical-height-dimension = <129>;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
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||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
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||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,dcs-cmd-by-left;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
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||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
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||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
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||||
|
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qcom,mdss-dsi-display-timings {
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||||
timing@0 {
|
||||
cell-index = <0>;
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||||
qcom,mdss-dsi-panel-width = <1080>;
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||||
qcom,mdss-dsi-panel-height = <3840>;
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||||
qcom,mdss-dsi-h-front-porch = <30>;
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||||
qcom,mdss-dsi-h-back-porch = <100>;
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||||
qcom,mdss-dsi-h-pulse-width = <4>;
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||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
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||||
qcom,mdss-dsi-v-front-porch = <8>;
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||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
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||||
qcom,mdss-dsi-panel-framerate = <60>;
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||||
qcom,mdss-dsi-panel-jitter = <0x8 0xa>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 11 91 09 20 00 20 02
|
||||
00 03 1c 04 21 00
|
||||
0f 03 19 01 97
|
||||
39 01 00 00 00 00 03 92 10 f0
|
||||
15 01 00 00 00 00 02 90 03
|
||||
15 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 04
|
||||
15 01 00 00 00 00 02 c0 03
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 07
|
||||
15 01 00 00 00 00 02 ef 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
15 01 00 00 00 00 02 b4 01
|
||||
15 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 01
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 80
|
||||
15 01 00 00 00 00 02 6f 01
|
||||
15 01 00 00 00 00 02 f3 10
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 00
|
||||
/* sleep out + delay 120ms */
|
||||
05 01 00 00 78 00 01 11
|
||||
/* display on + delay 120ms */
|
||||
05 01 00 00 78 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 78 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <32>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
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qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
89
display/dsi-panel-sharp-dsc-4k-video.dtsi
Normal file
89
display/dsi-panel-sharp-dsc-4k-video.dtsi
Normal file
@@ -0,0 +1,89 @@
|
||||
&mdss_mdp {
|
||||
dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video {
|
||||
qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
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||||
|
||||
qcom,dsi-ctrl-num = <0 1>;
|
||||
qcom,dsi-phy-num = <0 1>;
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||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
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qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
|
||||
qcom,mdss-pan-physical-width-dimension = <71>;
|
||||
qcom,mdss-pan-physical-height-dimension = <129>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <3840>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 11 91 09 20 00 20 02
|
||||
00 03 1c 04 21 00
|
||||
0f 03 19 01 97
|
||||
39 01 00 00 00 00 03 92 10 f0
|
||||
15 01 00 00 00 00 02 90 03
|
||||
15 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 04
|
||||
15 01 00 00 00 00 02 c0 03
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 07
|
||||
15 01 00 00 00 00 02 ef 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
15 01 00 00 00 00 02 b4 10
|
||||
15 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 01
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 80
|
||||
15 01 00 00 00 00 02 6f 01
|
||||
15 01 00 00 00 00 02 f3 10
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 00
|
||||
/* sleep out + delay 120ms */
|
||||
05 01 00 00 78 00 01 11
|
||||
/* display on + delay 120ms */
|
||||
05 01 00 00 78 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 78 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <32>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
131
display/dsi-panel-sim-cmd-au.dtsi
Normal file
131
display/dsi-panel-sim-cmd-au.dtsi
Normal file
@@ -0,0 +1,131 @@
|
||||
&mdss_mdp {
|
||||
dsi_sim_panel_au: qcom,mdss_dsi_cmd_sim_panel_au {
|
||||
qcom,mdss-dsi-panel-name = "cmd mode dsi sim panel au";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,vert-padding-value = <2940>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 07 FF
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
1275
display/dsi-panel-sim-cmd.dtsi
Normal file
1275
display/dsi-panel-sim-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
1225
display/dsi-panel-sim-dsc-10bit-cmd.dtsi
Normal file
1225
display/dsi-panel-sim-dsc-10bit-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
279
display/dsi-panel-sim-dsc375-cmd.dtsi
Normal file
279
display/dsi-panel-sim-dsc375-cmd.dtsi
Normal file
@@ -0,0 +1,279 @@
|
||||
&mdss_mdp {
|
||||
dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"Simulator cmd mode DSC 3.75:1 dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-wd;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,panel-ack-disabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <2560>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <10>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-on-command = [
|
||||
/* CMD2_P0 */
|
||||
15 01 00 00 00 00 02 ff 20
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
15 01 00 00 00 00 02 00 01
|
||||
15 01 00 00 00 00 02 01 55
|
||||
15 01 00 00 00 00 02 02 45
|
||||
15 01 00 00 00 00 02 05 40
|
||||
15 01 00 00 00 00 02 06 19
|
||||
15 01 00 00 00 00 02 07 1e
|
||||
15 01 00 00 00 00 02 0b 73
|
||||
15 01 00 00 00 00 02 0c 73
|
||||
15 01 00 00 00 00 02 0e b0
|
||||
15 01 00 00 00 00 02 0f aE
|
||||
15 01 00 00 00 00 02 11 b8
|
||||
15 01 00 00 00 00 02 13 00
|
||||
15 01 00 00 00 00 02 58 80
|
||||
15 01 00 00 00 00 02 59 01
|
||||
15 01 00 00 00 00 02 5a 00
|
||||
15 01 00 00 00 00 02 5b 01
|
||||
15 01 00 00 00 00 02 5c 80
|
||||
15 01 00 00 00 00 02 5d 81
|
||||
15 01 00 00 00 00 02 5e 00
|
||||
15 01 00 00 00 00 02 5f 01
|
||||
15 01 00 00 00 00 02 72 31
|
||||
15 01 00 00 00 00 02 68 03
|
||||
/* CMD2_P4 */
|
||||
15 01 00 00 00 00 02 ff 24
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
15 01 00 00 00 00 02 00 1c
|
||||
15 01 00 00 00 00 02 01 0b
|
||||
15 01 00 00 00 00 02 02 0c
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 04 0f
|
||||
15 01 00 00 00 00 02 05 10
|
||||
15 01 00 00 00 00 02 06 10
|
||||
15 01 00 00 00 00 02 07 10
|
||||
15 01 00 00 00 00 02 08 89
|
||||
15 01 00 00 00 00 02 09 8a
|
||||
15 01 00 00 00 00 02 0a 13
|
||||
15 01 00 00 00 00 02 0b 13
|
||||
15 01 00 00 00 00 02 0c 15
|
||||
15 01 00 00 00 00 02 0d 15
|
||||
15 01 00 00 00 00 02 0e 17
|
||||
15 01 00 00 00 00 02 0f 17
|
||||
15 01 00 00 00 00 02 10 1c
|
||||
15 01 00 00 00 00 02 11 0b
|
||||
15 01 00 00 00 00 02 12 0c
|
||||
15 01 00 00 00 00 02 13 01
|
||||
15 01 00 00 00 00 02 14 0f
|
||||
15 01 00 00 00 00 02 15 10
|
||||
15 01 00 00 00 00 02 16 10
|
||||
15 01 00 00 00 00 02 17 10
|
||||
15 01 00 00 00 00 02 18 89
|
||||
15 01 00 00 00 00 02 19 8a
|
||||
15 01 00 00 00 00 02 1a 13
|
||||
15 01 00 00 00 00 02 1b 13
|
||||
15 01 00 00 00 00 02 1c 15
|
||||
15 01 00 00 00 00 02 1d 15
|
||||
15 01 00 00 00 00 02 1e 17
|
||||
15 01 00 00 00 00 02 1f 17
|
||||
/* STV */
|
||||
15 01 00 00 00 00 02 20 40
|
||||
15 01 00 00 00 00 02 21 01
|
||||
15 01 00 00 00 00 02 22 00
|
||||
15 01 00 00 00 00 02 23 40
|
||||
15 01 00 00 00 00 02 24 40
|
||||
15 01 00 00 00 00 02 25 6d
|
||||
15 01 00 00 00 00 02 26 40
|
||||
15 01 00 00 00 00 02 27 40
|
||||
/* Vend */
|
||||
15 01 00 00 00 00 02 e0 00
|
||||
15 01 00 00 00 00 02 dc 21
|
||||
15 01 00 00 00 00 02 dd 22
|
||||
15 01 00 00 00 00 02 de 07
|
||||
15 01 00 00 00 00 02 df 07
|
||||
15 01 00 00 00 00 02 e3 6d
|
||||
15 01 00 00 00 00 02 e1 07
|
||||
15 01 00 00 00 00 02 e2 07
|
||||
/* UD */
|
||||
15 01 00 00 00 00 02 29 d8
|
||||
15 01 00 00 00 00 02 2a 2a
|
||||
/* CLK */
|
||||
15 01 00 00 00 00 02 4b 03
|
||||
15 01 00 00 00 00 02 4c 11
|
||||
15 01 00 00 00 00 02 4d 10
|
||||
15 01 00 00 00 00 02 4e 01
|
||||
15 01 00 00 00 00 02 4f 01
|
||||
15 01 00 00 00 00 02 50 10
|
||||
15 01 00 00 00 00 02 51 00
|
||||
15 01 00 00 00 00 02 52 80
|
||||
15 01 00 00 00 00 02 53 00
|
||||
15 01 00 00 00 00 02 56 00
|
||||
15 01 00 00 00 00 02 54 07
|
||||
15 01 00 00 00 00 02 58 07
|
||||
15 01 00 00 00 00 02 55 25
|
||||
/* Reset XDONB */
|
||||
15 01 00 00 00 00 02 5b 43
|
||||
15 01 00 00 00 00 02 5c 00
|
||||
15 01 00 00 00 00 02 5f 73
|
||||
15 01 00 00 00 00 02 60 73
|
||||
15 01 00 00 00 00 02 63 22
|
||||
15 01 00 00 00 00 02 64 00
|
||||
15 01 00 00 00 00 02 67 08
|
||||
15 01 00 00 00 00 02 68 04
|
||||
/* Resolution:1440x2560*/
|
||||
15 01 00 00 00 00 02 72 02
|
||||
/* mux */
|
||||
15 01 00 00 00 00 02 7a 80
|
||||
15 01 00 00 00 00 02 7b 91
|
||||
15 01 00 00 00 00 02 7c d8
|
||||
15 01 00 00 00 00 02 7d 60
|
||||
15 01 00 00 00 00 02 7f 15
|
||||
15 01 00 00 00 00 02 75 15
|
||||
/* ABOFF */
|
||||
15 01 00 00 00 00 02 b3 c0
|
||||
15 01 00 00 00 00 02 b4 00
|
||||
15 01 00 00 00 00 02 b5 00
|
||||
/* Source EQ */
|
||||
15 01 00 00 00 00 02 78 00
|
||||
15 01 00 00 00 00 02 79 00
|
||||
15 01 00 00 00 00 02 80 00
|
||||
15 01 00 00 00 00 02 83 00
|
||||
/* FP BP */
|
||||
15 01 00 00 00 00 02 93 0a
|
||||
15 01 00 00 00 00 02 94 0a
|
||||
/* Inversion Type */
|
||||
15 01 00 00 00 00 02 8a 00
|
||||
15 01 00 00 00 00 02 9b ff
|
||||
/* IMGSWAP =1 @PortSwap=1 */
|
||||
15 01 00 00 00 00 02 9d b0
|
||||
15 01 00 00 00 00 02 9f 63
|
||||
15 01 00 00 00 00 02 98 10
|
||||
/* FRM */
|
||||
15 01 00 00 00 00 02 ec 00
|
||||
/* CMD1 */
|
||||
15 01 00 00 00 00 02 ff 10
|
||||
/* VESA DSC PPS settings
|
||||
* (1440x2560 slide 16H)
|
||||
*/
|
||||
39 01 00 00 00 00 11 c1 09
|
||||
20 00 10 02 00 02 68 01 bb
|
||||
00 0a 06 67 04 c5
|
||||
|
||||
39 01 00 00 00 00 03 c2 10 f0
|
||||
/* C0h = 0x0(2 Port SDC)
|
||||
* 0x01(1 PortA FBC)
|
||||
* 0x02(MTK) 0x03(1 PortA VESA)
|
||||
*/
|
||||
15 01 00 00 00 00 02 c0 03
|
||||
/* VBP+VSA=,VFP = 10H */
|
||||
15 01 00 00 00 00 04 3b 03 0a 0a
|
||||
/* FTE on */
|
||||
15 01 00 00 00 00 02 35 00
|
||||
/* EN_BK =1(auto black) */
|
||||
15 01 00 00 00 00 02 e5 01
|
||||
/* CMD mode(10) VDO mode(03) */
|
||||
15 01 00 00 00 00 02 bb 10
|
||||
/* Non Reload MTP */
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
05 01 00 00 f0 00 01 00
|
||||
];
|
||||
qcom,mdss-dsi-off-command = [05 01 00 00 78 00
|
||||
02 28 00 05 01 00 00 78 00 02 10 00];
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <16>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <1920>;
|
||||
qcom,mdss-dsi-h-front-porch = <0>;
|
||||
qcom,mdss-dsi-h-back-porch = <0>;
|
||||
qcom,mdss-dsi-h-pulse-width = <0>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <0>;
|
||||
qcom,mdss-dsi-v-front-porch = <0>;
|
||||
qcom,mdss-dsi-v-pulse-width = <0>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-on-command = [
|
||||
15 01 00 00 00 00 02 bb 10
|
||||
15 01 00 00 00 00 02 b0 03
|
||||
05 01 00 00 78 00 01 11
|
||||
15 01 00 00 00 00 02 51 ff
|
||||
15 01 00 00 00 00 02 53 24
|
||||
15 01 00 00 00 00 02 ff 23
|
||||
15 01 00 00 00 00 02 08 05
|
||||
15 01 00 00 00 00 02 46 90
|
||||
15 01 00 00 00 00 02 ff 10
|
||||
15 01 00 00 00 00 02 ff f0
|
||||
15 01 00 00 00 00 02 92 01
|
||||
15 01 00 00 00 00 02 ff 10
|
||||
/* enable TE generation */
|
||||
15 01 00 00 00 00 02 35 00
|
||||
05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 10 00 01 28
|
||||
05 01 00 00 40 00 01 10];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <16>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
258
display/dsi-panel-sim-dualmipi-cmd.dtsi
Normal file
258
display/dsi-panel-sim-dualmipi-cmd.dtsi
Normal file
@@ -0,0 +1,258 @@
|
||||
&mdss_mdp {
|
||||
dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0 1>;
|
||||
qcom,dsi-phy-num = <0 1>;
|
||||
qcom,mdss-dsi-bpp-switch;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,cmd-sync-wait-broadcast;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-hor-line-idle = <0 40 256>,
|
||||
<40 120 128>,
|
||||
<120 240 64>;
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-wd;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,panel-ack-disabled;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <30>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <2520>;
|
||||
qcom,mdss-dsi-panel-height = <2160>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,dsi-wd-jitter-enable;
|
||||
qcom,mdss-dsi-panel-jitter = <0x2 0x1>;
|
||||
qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>;
|
||||
qcom,dsi-wd-ltj-time-sec = <3600>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-mdp-transfer-time-us-min = <14000>;
|
||||
qcom,mdss-mdp-transfer-time-us-max = <16000>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-width = <540>;
|
||||
qcom,mdss-dsi-panel-height = <1920>;
|
||||
qcom,mdss-dsi-h-front-porch = <28>;
|
||||
qcom,mdss-dsi-h-back-porch = <4>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <12>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,dsi-wd-jitter-enable;
|
||||
qcom,mdss-dsi-panel-jitter = <0x2 0x1>;
|
||||
qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>;
|
||||
qcom,dsi-wd-ltj-time-sec = <3600>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-mdp-transfer-time-us-min = <6900>;
|
||||
qcom,mdss-mdp-transfer-time-us-max = <7900>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-width = <1280>;
|
||||
qcom,mdss-dsi-panel-height = <1440>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <44>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
cell-index = <3>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <3840>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <40>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
};
|
||||
|
||||
timing@4 {
|
||||
cell-index = <4>;
|
||||
qcom,mdss-dsi-panel-width = <2520>;
|
||||
qcom,mdss-dsi-panel-height = <2160>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <80>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
};
|
||||
|
||||
timing@5 {
|
||||
cell-index = <5>;
|
||||
qcom,mdss-dsi-bpp-mode= <24>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <540>;
|
||||
qcom,mdss-dsi-panel-height = <1920>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <44>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <80>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
};
|
||||
|
||||
timing@6 {
|
||||
cell-index = <6>;
|
||||
qcom,mdss-dsi-bpp-mode= <30>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <540>;
|
||||
qcom,mdss-dsi-panel-height = <1920>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <44>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <80>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
1458
display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi
Normal file
1458
display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
64
display/dsi-panel-sim-dualmipi-video.dtsi
Normal file
64
display/dsi-panel-sim-dualmipi-video.dtsi
Normal file
@@ -0,0 +1,64 @@
|
||||
&mdss_mdp {
|
||||
dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video {
|
||||
qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0 1>;
|
||||
qcom,dsi-phy-num = <0 1>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-panel-broadcast-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
|
||||
qcom,panel-ack-disabled;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <45>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <1280>;
|
||||
qcom,mdss-dsi-panel-height = <1440>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <44>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 32 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
64
display/dsi-panel-sim-sec-hd-cmd.dtsi
Normal file
64
display/dsi-panel-sim-sec-hd-cmd.dtsi
Normal file
@@ -0,0 +1,64 @@
|
||||
&mdss_mdp {
|
||||
dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"sim hd command mode secondary dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,panel-ack-disabled;
|
||||
qcom,mdss-dsi-te-using-wd;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,mdss-dsi-post-init-delay = <1>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <720>;
|
||||
qcom,mdss-dsi-panel-height = <1280>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <60>;
|
||||
qcom,mdss-dsi-h-pulse-width = <12>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <2>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-on-command = [
|
||||
05 01 00 00 f0 00 01 00
|
||||
];
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 78 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00
|
||||
];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
66
display/dsi-panel-sim-video.dtsi
Normal file
66
display/dsi-panel-sim-video.dtsi
Normal file
@@ -0,0 +1,66 @@
|
||||
&mdss_mdp {
|
||||
dsi_sim_vid: qcom,mdss_dsi_sim_video {
|
||||
qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-t-clk-post = <0x04>;
|
||||
qcom,mdss-dsi-t-clk-pre = <0x1b>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>;
|
||||
qcom,panel-ack-disabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <2560>;
|
||||
qcom,mdss-dsi-h-front-porch = <8>;
|
||||
qcom,mdss-dsi-h-back-porch = <8>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <6>;
|
||||
qcom,mdss-dsi-v-front-porch = <6>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-on-command =
|
||||
[32 01 00 00 00 00 02 00 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[22 01 00 00 00 00 02 00 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
360
display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi
Normal file
360
display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi
Normal file
@@ -0,0 +1,360 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_120hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled cmd mode 120hz dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <683100000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <683100000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <683100000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
123
display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi
Normal file
123
display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi
Normal file
@@ -0,0 +1,123 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_120hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled video mode 120hz dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
552
display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi
Normal file
552
display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi
Normal file
@@ -0,0 +1,552 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled cmd mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-panel-mode-switch;
|
||||
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,spr-pack-type = "pentile";
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-video-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <10>;
|
||||
qcom,mdss-dsi-h-back-porch = <16>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <18>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <813936000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
];
|
||||
|
||||
qcom,cmd-on-commands = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,vid-on-commands = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,cmd-mode-switch-out-commands = [
|
||||
39 01 00 00 00 00 02 6f 07
|
||||
];
|
||||
qcom,cmd-mode-switch-out-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,video-mode-switch-in-commands = [
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
];
|
||||
qcom,video-mode-switch-in-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,video-mode-switch-out-commands = [
|
||||
39 01 00 00 00 00 02 6f 03
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
];
|
||||
qcom,video-mode-switch-out-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <813936000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <813936000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
cell-index = <3>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <813936000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
129
display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi
Normal file
129
display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi
Normal file
@@ -0,0 +1,129 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_video: qcom,mdss_dsi_vtdr6130_fhd_plus_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled video mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,spr-pack-type = "pentile";
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
159
display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi
Normal file
159
display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi
Normal file
@@ -0,0 +1,159 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_qsync_144hz_cmd: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled qsync cmd mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <95>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 3c 00 3c 00
|
||||
0c 00 0c 04 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 0c bb 00 4c 00 01 00
|
||||
01 32 01 6e 01 6e
|
||||
39 01 00 00 00 00 02 bb 01
|
||||
];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 02 bb 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
127
display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi
Normal file
127
display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi
Normal file
@@ -0,0 +1,127 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_qsync_144hz_video: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled qsync video mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <80>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
@@ -331,5 +331,141 @@
|
||||
qcom,sde-dspp-dither = <0x82c 0x00010007>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
|
||||
compatible = "qcom,dsi-ctrl-hw-v2.9";
|
||||
label = "dsi-ctrl-0";
|
||||
cell-index = <0>;
|
||||
frame-threshold-time-us = <800>;
|
||||
reg = <0xae94000 0x1000>,
|
||||
<0xaf0f000 0x4>,
|
||||
<0x0ae36000 0x300>;
|
||||
reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <4 0>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <16600>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
|
||||
compatible = "qcom,dsi-ctrl-hw-v2.9";
|
||||
label = "dsi-ctrl-1";
|
||||
cell-index = <1>;
|
||||
frame-threshold-time-us = <800>;
|
||||
reg = <0xae96000 0x1000>,
|
||||
<0xaf0f000 0x4>,
|
||||
<0x0ae37000 0x300>;
|
||||
reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <5 0>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <16600>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 {
|
||||
compatible = "qcom,dsi-phy-v7.2";
|
||||
label = "dsi-phy-0";
|
||||
cell-index = <0>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0xae95000 0xa00>,
|
||||
<0xae95500 0x400>,
|
||||
<0xae94200 0xa0>;
|
||||
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
|
||||
pll-label = "dsi_pll_3nm";
|
||||
|
||||
qcom,platform-strength-ctrl = [55 03
|
||||
55 03
|
||||
55 03
|
||||
55 03
|
||||
55 00];
|
||||
qcom,platform-lane-config = [00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 8a 8a];
|
||||
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <880000>;
|
||||
qcom,supply-enable-load = <98000>;
|
||||
qcom,supply-disable-load = <96>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 {
|
||||
compatible = "qcom,dsi-phy-v7.2";
|
||||
label = "dsi-phy-1";
|
||||
cell-index = <1>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0xae97000 0xa00>,
|
||||
<0xae97500 0x400>,
|
||||
<0xae96200 0xa0>;
|
||||
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
|
||||
pll-label = "dsi_pll_3nm";
|
||||
|
||||
qcom,platform-strength-ctrl = [55 03
|
||||
55 03
|
||||
55 03
|
||||
55 03
|
||||
55 00];
|
||||
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
||||
qcom,platform-lane-config = [00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 8a 8a];
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <880000>;
|
||||
qcom,supply-enable-load = <98000>;
|
||||
qcom,supply-disable-load = <96>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_pll_codes_data:dsi_pll_codes {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
label = "dsi_pll_codes";
|
||||
};
|
||||
};
|
||||
|
@@ -14,4 +14,3 @@
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>;
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
|
||||
|
@@ -5,3 +5,179 @@
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
avdd-supply = <&display_panel_avdd>;
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se15_i2c {
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy>;
|
||||
};
|
||||
};
|
||||
|
924
display/sun-sde-display-common.dtsi
Normal file
924
display/sun-sde-display-common.dtsi
Normal file
@@ -0,0 +1,924 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi"
|
||||
#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi"
|
||||
#include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi"
|
||||
#include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi"
|
||||
#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
|
||||
#include "dsi-panel-sharp-dsc-4k-video.dtsi"
|
||||
#include "dsi-panel-sim-cmd-au.dtsi"
|
||||
#include "dsi-panel-sim-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dsc375-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-video.dtsi"
|
||||
#include "dsi-panel-sim-sec-hd-cmd.dtsi"
|
||||
#include "dsi-panel-sim-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi"
|
||||
|
||||
#include "sun-sde-display-pinctrl.dtsi"
|
||||
|
||||
&soc {
|
||||
dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "dummy";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <220000>;
|
||||
qcom,supply-disable-load = <8000>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <154000>;
|
||||
qcom,supply-disable-load = <45000>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vdd";
|
||||
qcom,supply-min-voltage = <1000000>;
|
||||
qcom,supply-max-voltage = <1100000>;
|
||||
qcom,supply-enable-load = <220000>;
|
||||
qcom,supply-disable-load = <471>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@2 {
|
||||
reg = <2>;
|
||||
qcom,supply-name = "vci";
|
||||
qcom,supply-min-voltage = <3000000>;
|
||||
qcom,supply-max-voltage = <3000000>;
|
||||
qcom,supply-enable-load = <10000>;
|
||||
qcom,supply-disable-load = <300>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@3 {
|
||||
reg = <3>;
|
||||
qcom,supply-name = "tvdd";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
qcom,supply-post-on-sleep = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <220000>;
|
||||
qcom,supply-disable-load = <8000>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "avdd";
|
||||
qcom,supply-min-voltage = <4600000>;
|
||||
qcom,supply-max-voltage = <6000000>;
|
||||
qcom,supply-enable-load = <260000>;
|
||||
qcom,supply-disable-load = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi: qcom,dsi-display-primary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "primary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 86 0>;
|
||||
qcom,panel-te-source = <0>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
qcom,demura-panel-id = <0x0122e700 0x00000471>;
|
||||
};
|
||||
|
||||
sde_dsi1: qcom,dsi-display-secondary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "secondary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
|
||||
pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 87 0>;
|
||||
qcom,panel-te-source = <1>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
qcom,demura-panel-id = <0x0 0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PHY TIMINGS REVISION YL with reduced margins */
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
qcom,dsi-supported-dfps-list = <144 120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-supported-dfps-list = <120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
|
||||
0b 0a 02 04 00 21 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
|
||||
0b 0a 02 04 00 21 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x77>;
|
||||
qcom,mdss-dsi-panel-on-check-value = <0x77>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
qcom,esd-check-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x77>;
|
||||
qcom,mdss-dsi-panel-on-check-value = <0x77>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
qcom,esd-check-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,poms-align-panel-vsync;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS cmd-vid mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
07 07 02 04 00 16 0c];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <50>;
|
||||
};
|
||||
|
||||
timing@1 { /* WQHD 60FPS vid mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
07 07 02 04 00 16 0c];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <50>;
|
||||
};
|
||||
|
||||
timing@2 { /* FHD+ 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a
|
||||
0a 0a 02 04 00 1f 0f];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <10>;
|
||||
};
|
||||
|
||||
timing@3 { /* HD 60FPS cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 29 0a 0b 1b 26 0a
|
||||
0b 0a 02 04 00 21 10];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <48>;
|
||||
};
|
||||
|
||||
timing@4 { /* FHD+ 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e
|
||||
0f 0d 02 04 00 2d 13];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD+ 180 FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 69 1d 1d 35 2f 1b
|
||||
1d 18 02 04 00 51 21];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <96>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD+ 240 FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 89 26 27 42 39 25
|
||||
27 1f 02 04 00 69 2a];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <110>;
|
||||
};
|
||||
|
||||
timing@7 { /* FHD+ 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 4a 13 14 28 24 12
|
||||
14 11 02 04 00 39 18];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <40>;
|
||||
};
|
||||
|
||||
timing@8 { /* FHD+ 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <60>;
|
||||
};
|
||||
|
||||
timing@9 { /* WQHD 1FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@10 { /* WQHD 5FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@11 { /* WQHD 10FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <5>;
|
||||
};
|
||||
|
||||
timing@12 { /* WQHD 24FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <15>;
|
||||
};
|
||||
|
||||
timing@13 { /* WQHD 30FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <22>;
|
||||
};
|
||||
|
||||
timing@14 { /* WQHD 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
|
||||
timing@15 { /* WQHD 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09
|
||||
09 09 02 04 00 1d 0e];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <10>;
|
||||
};
|
||||
|
||||
timing@16 { /* WQHD 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c
|
||||
0c 0b 02 04 00 24 11];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@17 { /* WQHD 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 17 14 0e
|
||||
0e 0d 02 04 00 2b 12];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <5>;
|
||||
};
|
||||
|
||||
timing@18 { /* WQHD 180FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f
|
||||
10 0e 02 04 00 2f 13];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,qsync-enable;
|
||||
qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>;
|
||||
qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a
|
||||
0a 09 02 04 00 1e 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 1080p */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05
|
||||
05 06 02 04 00 13 0a];
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* qhd */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03
|
||||
03 02 02 04 00 0b 08];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* QHD 60fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05
|
||||
05 06 02 04 00 13 0a];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@1 { /* FHD+ 60fps cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03
|
||||
03 02 02 04 00 0c 08];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@2 { /* QHD 90fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08
|
||||
08 08 02 04 00 19 0d];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@3 { /* FHD+ 180FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 16 08
|
||||
08 08 02 04 00 1a 0d];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* FHD+ 240FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
|
||||
0b 0a 02 04 00 21 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD+ 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
|
||||
06 06 02 04 00 13 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD+ 1FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01
|
||||
00 01 02 04 00 05 05];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@7 { /* FHD+ 10FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@8 { /* FHD+ 24FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02
|
||||
01 01 02 04 00 08 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@9 { /* FHD+ 30FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02
|
||||
02 01 02 04 00 09 07];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@10 { /* FHD+ 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e
|
||||
0f 0d 02 04 00 2d 13];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@11 { /* FHD+ 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 5K 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11
|
||||
12 0f 02 04 00 35 16];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* FHD 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07
|
||||
07 08 02 04 00 18 0c];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* WQHD 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07
|
||||
07 07 02 04 00 17 0c];
|
||||
qcom,display-topology = <2 0 2>,
|
||||
<1 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@3 { /* 4K 40FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a
|
||||
0a 0a 02 04 00 1f 0f];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* 5K 80FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17
|
||||
18 14 02 04 00 43 1c];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD 60FPS 24bpp cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD 60FPS 30bpp cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 4k 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* 4k 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* 4k 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09
|
||||
09 09 02 04 00 1d 0e];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@3 { /* 1080 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01
|
||||
01 02 02 04 00 08 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* 1080 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* 1080 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04
|
||||
03 03 02 04 00 0d 08];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* 1080 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04
|
||||
04 03 02 04 00 0f 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@7 { /* qhd 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@8 { /* qhd 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@9 { /* qhd 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@10 { /* qhd 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@11 { /* 5k */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07
|
||||
07 07 02 04 00 17 0c];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@12 { /* 720p 30 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@13 { /* 720p 60 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01
|
||||
01 02 02 04 00 08 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@14 { /* 720p 90 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@15 { /* 720 120 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03
|
||||
03 02 02 04 00 0a 08];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@16 { /* 1080 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@17 { /* WQHD 144 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e
|
||||
04 04 03 02 04 00 0e 09];
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
@@ -14,4 +14,3 @@
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>;
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
|
||||
|
@@ -5,3 +5,92 @@
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy>;
|
||||
};
|
||||
};
|
||||
|
||||
&battery_charger {
|
||||
qcom,display-panels = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy>;
|
||||
};
|
||||
|
113
display/sun-sde-display-pinctrl.dtsi
Normal file
113
display/sun-sde-display-pinctrl.dtsi
Normal file
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&tlmm {
|
||||
pmx_sde: pmx_sde {
|
||||
sde_dsi_active: sde_dsi_active {
|
||||
mux {
|
||||
pins = "gpio98";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio98";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi_suspend: sde_dsi_suspend {
|
||||
mux {
|
||||
pins = "gpio98";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio98";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi1_active: sde_dsi1_active {
|
||||
mux {
|
||||
pins = "gpio97";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio97";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi1_suspend: sde_dsi1_suspend {
|
||||
mux {
|
||||
pins = "gpio97";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio97";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmx_sde_te: pmx_sde_te {
|
||||
sde_te_active: sde_te_active {
|
||||
mux {
|
||||
pins = "gpio86";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio86";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te_suspend: sde_te_suspend {
|
||||
mux {
|
||||
pins = "gpio86";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio86";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te1_active: sde_te1_active {
|
||||
mux {
|
||||
pins = "gpio87";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio87";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te1_suspend: sde_te1_suspend {
|
||||
mux {
|
||||
pins = "gpio87";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio87";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
@@ -4,8 +4,21 @@
|
||||
*/
|
||||
|
||||
#include "sun-sde.dtsi"
|
||||
#include "sun-sde-display-common.dtsi"
|
||||
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
||||
|
||||
&pm8550_gpios {
|
||||
display_panel_avdd_default: display_panel_avdd_default {
|
||||
pins = "gpio11";
|
||||
function = "normal";
|
||||
input-disable;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
power-source = <1>;
|
||||
qcom,drive-strength = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
sde_wb1: qcom,wb-display@1 {
|
||||
compatible = "qcom,wb-display";
|
||||
@@ -18,9 +31,160 @@
|
||||
cell-index = <1>;
|
||||
label = "wb_display2";
|
||||
};
|
||||
|
||||
|
||||
display_panel_avdd: display_gpio_regulator@1 {
|
||||
compatible = "qti-regulator-fixed";
|
||||
regulator-name = "display_panel_avdd";
|
||||
regulator-min-microvolt = <5500000>;
|
||||
regulator-max-microvolt = <5500000>;
|
||||
regulator-enable-ramp-delay = <233>;
|
||||
gpio = <&pm8550_gpios 11 0>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
proxy-supply = <&display_panel_avdd>;
|
||||
qcom,proxy-consumer-enable;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
* finishes, the dispcc sync state can get called before
|
||||
* the dsi_display probe potentially disturbing the clock
|
||||
* votes for cont_splash use case. Hence we are no longer
|
||||
* protected by the component model in this case against the
|
||||
* disp cc sync state getting triggered after the dsi_ctrl
|
||||
* probe. To protect against this incorrect sync state trigger
|
||||
* add this dummy MDP clk vote handle to the dsi_display
|
||||
* DT node. Since the dsi_display driver does not parse
|
||||
* MDP clock nodes, no actual vote shall be added and this
|
||||
* change is done just to satisfy sync state requirements.
|
||||
*/
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk";
|
||||
vddio-supply = <&L12B>;
|
||||
vci-supply = <&L13B>;
|
||||
vdd-supply = <&L11B>;
|
||||
tvdd-supply = <&L4B>;
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
* finishes, the dispcc sync state can get called before
|
||||
* the dsi_display probe potentially disturbing the clock
|
||||
* votes for cont_splash use case. Hence we are no longer
|
||||
* protected by the component model in this case against the
|
||||
* disp cc sync state getting triggered after the dsi_ctrl
|
||||
* probe. To protect against this incorrect sync state trigger
|
||||
* add this dummy MDP clk vote handle to the dsi_display
|
||||
* DT node. Since the dsi_display driver does not parse
|
||||
* MDP clock nodes, no actual vote shall be added and this
|
||||
* change is done just to satisfy sync state requirements.
|
||||
*/
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk";
|
||||
vddio-supply = <&L12B>;
|
||||
vci-supply = <&L13B>;
|
||||
vdd-supply = <&L11B>;
|
||||
tvdd-supply = <&L4B>;
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&smmu_sde_unsec &sde_wb1 &sde_wb2>;
|
||||
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS cmd vid mode*/
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@2 { /* FHD 60FPS cmd mode*/
|
||||
qcom,panel-roi-alignment = <540 40 540 40 540 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@3 { /* HD 60FPS cmd mode*/
|
||||
qcom,panel-roi-alignment = <360 20 360 20 360 20>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@@ -9,6 +9,7 @@
|
||||
#include <dt-bindings/interconnect/qcom,sun.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
|
||||
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
|
||||
#include "sun-sde-common.dtsi"
|
||||
|
||||
&soc {
|
||||
@@ -47,6 +48,8 @@
|
||||
vdd-supply = <&disp_cc_mdss_core_gdsc>;
|
||||
mmcx-supply = <&VDD_MMCX_LEVEL>;
|
||||
|
||||
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
|
||||
|
||||
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
|
||||
|
||||
/* data and reg bus scale settings */
|
||||
@@ -57,6 +60,8 @@
|
||||
interconnect-names = "qcom,sde-data-bus0",
|
||||
"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
|
||||
|
||||
qcom,sde-has-idle-pc;
|
||||
|
||||
qcom,sde-ib-bw-vote = <2500000 0 800000>;
|
||||
qcom,sde-dspp-ltm-version = <0x00010002>;
|
||||
/* offsets are based off dspp 0, 1, 2, and 3 */
|
||||
@@ -86,3 +91,46 @@
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-1p2-supply = <&L3G>;
|
||||
qcom,split-link-supported;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
vdda-1p2-supply = <&L3G>;
|
||||
qcom,split-link-supported;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
vdda-0p9-supply = <&L3I>;
|
||||
qcom,panel-allow-phy-poweroff;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
pll_codes_region = <&dsi_pll_codes_data>;
|
||||
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
vdda-0p9-supply = <&L3I>;
|
||||
qcom,panel-allow-phy-poweroff;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
};
|
||||
|
Reference in New Issue
Block a user