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ARM: dts: msm: add support for ipcc protocol for hw fence on sun

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This change adds the register address and size for ipcc base and
the dpu client physical id to be used for hw fencing register access.

Change-Id: I6a389626c186cc0f5a10900e890ecd33f6a606d2
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This commit is contained in:
Christina Oliveira
2024-01-29 14:19:45 -08:00
parent eb5a7fdf0e
commit 745316e53e
1 changed files with 7 additions and 2 deletions
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9
display/sun-sde-common.dtsi
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@@ -12,10 +12,12 @@
compatible = "qcom,sde-kms"; compatible = "qcom,sde-kms";
reg = <0x0ae00000 0x93800>, reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>, <0x0aeb0000 0x2008>,
<0x0af80000 0x7000>; <0x0af80000 0x7000>,
<0x400000 0x2000>;
reg-names = "mdp_phys", reg-names = "mdp_phys",
"vbif_phys", "vbif_phys",
"regdma_phys"; "regdma_phys",
"ipcc_reg";
/* interrupt config */ /* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -261,6 +263,9 @@
qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>;
qcom,sde-ipcc-protocol-id = <0x4>;
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
/* offsets are relative to "mdp_phys + qcom,sde-off */ /* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x800>; qcom,sde-reg-dma-off = <0 0x800>;
qcom,sde-reg-dma-id = <0 1>; qcom,sde-reg-dma-id = <0 1>;