From 745316e53e8d59bdffb7b2091c4b28fa2569c5ea Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Mon, 29 Jan 2024 14:19:45 -0800 Subject: [PATCH] ARM: dts: msm: add support for ipcc protocol for hw fence on sun This change adds the register address and size for ipcc base and the dpu client physical id to be used for hw fencing register access. Change-Id: I6a389626c186cc0f5a10900e890ecd33f6a606d2 Signed-off-by: Christina Oliveira --- display/sun-sde-common.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index d8fe8840..36d306c0 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -12,10 +12,12 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, - <0x0af80000 0x7000>; + <0x0af80000 0x7000>, + <0x400000 0x2000>; reg-names = "mdp_phys", "vbif_phys", - "regdma_phys"; + "regdma_phys", + "ipcc_reg"; /* interrupt config */ interrupts = ; @@ -261,6 +263,9 @@ qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; qcom,sde-reg-dma-id = <0 1>;