ARM: dts: msm: enable display on kera platforms
Enable display on kera platforms. Change-Id: I40b6a9f002a72a527e2cbe61f0f59f059ad5716e Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com> Signed-off-by: lnxdisplay <lnxdisplay@localhost>
This commit is contained in:
committed by
Linux Display Service Account
parent
91808d9891
commit
738b90d9fe
10
Kbuild
10
Kbuild
@@ -49,6 +49,16 @@ dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo
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display/trustedvm-tuna-sde-display-rcm-overlay.dtbo
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endif
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ifneq ($(CONFIG_ARCH_QTI_VM), y)
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dtbo-$(CONFIG_ARCH_KERA) += display/kera-sde.dtbo \
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display/kera-sde-display-atp-overlay.dtbo \
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display/kera-sde-display-cdp-overlay.dtbo \
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display/kera-sde-display-mtp-overlay.dtbo \
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display/kera-sde-display-qrd-overlay.dtbo \
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display/kera-sde-display-rumi-overlay.dtbo \
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display/kera-sde-display-rcm-overlay.dtbo
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endif
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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156
display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi
Normal file
156
display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi
Normal file
@@ -0,0 +1,156 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&mdss_mdp {
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dsi_vtdr6130_amoled_60hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_60hz_cmd {
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qcom,mdss-dsi-panel-name =
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"vtdr6130 amoled cmd mode dsi visionox panel with DSC";
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qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
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qcom,mdss-dsi-panel-physical-type = "oled";
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qcom,mdss-dsi-virtual-channel-id = <0>;
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qcom,mdss-dsi-stream = <0>;
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qcom,mdss-dsi-bpp = <24>;
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qcom,mdss-dsi-color-order = "rgb_swap_rgb";
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qcom,mdss-dsi-underflow-color = <0xff>;
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qcom,mdss-dsi-border-color = <0>;
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qcom,dsi-ctrl-num = <0>;
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qcom,dsi-phy-num = <0>;
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qcom,dsi-sec-ctrl-num = <1>;
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qcom,dsi-sec-phy-num = <1>;
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qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
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qcom,mdss-dsi-lane-map = "lane_map_0123";
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qcom,mdss-dsi-bllp-eof-power-mode;
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qcom,mdss-dsi-bllp-power-mode;
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qcom,mdss-dsi-lane-0-state;
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qcom,mdss-dsi-lane-1-state;
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qcom,mdss-dsi-lane-2-state;
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qcom,mdss-dsi-lane-3-state;
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qcom,mdss-dsi-dma-trigger = "trigger_sw";
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qcom,mdss-dsi-mdp-trigger = "none";
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qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
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qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
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17000 15500 30000 8000 3000>;
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qcom,mdss-dsi-panel-peak-brightness = <4200000>;
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qcom,mdss-dsi-panel-blackness-level = <3230>;
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qcom,mdss-dsi-te-pin-select = <1>;
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qcom,mdss-dsi-wr-mem-start = <0x2c>;
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qcom,mdss-dsi-wr-mem-continue = <0x3c>;
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qcom,mdss-dsi-te-dcs-command = <1>;
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qcom,mdss-dsi-te-check-enable;
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qcom,mdss-dsi-te-using-te-pin;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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cell-index = <0>;
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qcom,mdss-dsi-panel-framerate = <60>;
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qcom,mdss-dsi-panel-width = <1080>;
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qcom,mdss-dsi-panel-height = <2400>;
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qcom,mdss-dsi-h-front-porch = <20>;
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qcom,mdss-dsi-h-back-porch = <20>;
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qcom,mdss-dsi-h-pulse-width = <2>;
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qcom,mdss-dsi-h-sync-skew = <0>;
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qcom,mdss-dsi-v-back-porch = <18>;
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qcom,mdss-dsi-v-front-porch = <20>;
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qcom,mdss-dsi-v-pulse-width = <2>;
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qcom,mdss-dsi-h-left-border = <0>;
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qcom,mdss-dsi-h-right-border = <0>;
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qcom,mdss-dsi-v-top-border = <0>;
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qcom,mdss-dsi-v-bottom-border = <0>;
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qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
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qcom,mdss-dsi-panel-clockrate = <353116800>;
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qcom,mdss-dsi-timing-switch-command = [
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39 01 00 00 00 00 02 6c 02
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39 01 00 00 00 00 03 f0 aa 10
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39 01 00 00 00 00 16 b1 01 38 00 14 00
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1c 00 01 66 00 14 01 fc 00 01 66 00
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14 0d 6c 00
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39 01 00 00 00 00 03 f0 aa 13
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39 01 00 00 00 00 18 d3 15 c2 15 c2 15
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02 13 25 0d 8a 00 90 00 7d 00 57 00
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0c 00 0c 0b 00 7e
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];
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qcom,mdss-dsi-on-command = [
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39 01 00 00 00 00 02 03 01
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39 01 00 00 00 00 02 35 00
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39 01 00 00 00 00 02 53 20
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39 01 00 00 00 00 03 51 00 00
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39 01 00 00 00 00 02 59 09
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39 01 00 00 00 00 02 6c 02
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39 01 00 00 00 00 02 6d 00
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39 01 00 00 00 00 02 6f 02
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39 01 00 00 00 00 5f 70 12 00 00 ab 30
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80 09 60 04 38 00 28 02 1c 02 1c 02
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00 02 0e 00 20 03 dd 00 07 00 0c 02
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77 02 8b 18 00 10 f0 07 10 20 00 06
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0f 0f 33 0e 1c 2a 38 46 54 62 69 70
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77 79 7b 7d 7e 02 02 22 00 2a 40 2a
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be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
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b6 4b b6 4b f4 4b f4 6c 34 84 74 00
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00 00 00 00 00
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39 01 00 00 00 00 03 f0 aa 10
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39 01 00 00 00 00 16 b1 01 38 00 14 00
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1c 00 01 66 00 14 01 fc 00 01 66 00
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14 0d 6c 00
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39 01 00 00 00 00 03 f0 aa 13
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39 01 00 00 00 00 18 d3 15 c2 15 c2 15
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02 13 25 0d 8a 00 90 00 7d 00 57 00
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0c 00 0c 0b 00 7e
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39 01 00 00 00 00 03 f0 aa 14
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39 01 00 00 00 00 03 b2 03 33
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39 01 00 00 00 00 0d b4 00 33 00 00 00
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3e 00 00 00 3e 00 00
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39 01 00 00 00 00 0a b5 00 09 09 09 09
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09 09 06 01
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39 01 00 00 00 00 07 b9 00 00 08 09 09
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09
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39 01 00 00 00 00 0d bc 10 00 00 06 11
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09 3b 09 47 09 47 00
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39 01 00 00 00 00 0d be 10 10 00 08 22
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09 19 09 25 09 25 00
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39 01 00 00 00 00 03 ff 5a 80
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39 01 00 00 00 00 02 65 14
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39 01 00 00 00 00 04 fa 08 08 08
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39 01 00 00 00 00 03 ff 5a 81
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39 01 00 00 00 00 02 65 05
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39 01 00 00 00 00 02 f3 0f
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39 01 00 00 00 00 03 f0 aa 00
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39 01 00 00 00 00 03 ff 5a 82
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39 01 00 00 00 00 02 f9 00
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39 01 00 00 00 00 03 ff 51 83
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39 01 00 00 00 00 02 65 04
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39 01 00 00 00 00 02 f8 00
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39 01 00 00 00 00 03 ff 5a 00
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39 01 00 00 00 00 02 65 01
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39 01 00 00 00 00 02 f4 9a
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39 01 00 00 00 00 03 ff 5a 00
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05 01 00 00 78 00 01 11
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05 01 00 00 14 00 01 29
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];
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qcom,mdss-dsi-off-command = [
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05 01 00 00 14 00 02 28 00
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05 01 00 00 78 00 02 10 00];
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qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-timing-switch-command-state =
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"dsi_lp_mode";
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qcom,mdss-dsi-h-sync-pulse = <0>;
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qcom,compression-mode = "dsc";
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qcom,mdss-dsc-slice-height = <40>;
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qcom,mdss-dsc-slice-width = <540>;
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qcom,mdss-dsc-slice-per-pkt = <1>;
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qcom,mdss-dsc-bit-per-component = <8>;
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qcom,mdss-dsc-bit-per-pixel = <8>;
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qcom,mdss-dsc-block-prediction-enable;
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};
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};
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};
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};
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134
display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi
Normal file
134
display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi
Normal file
@@ -0,0 +1,134 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&mdss_mdp {
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dsi_vtdr6130_amoled_60hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_60hz_vid {
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qcom,mdss-dsi-panel-name =
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"vtdr6130 amoled video mode dsi visionox panel with DSC";
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qcom,mdss-dsi-panel-type = "dsi_video_mode";
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qcom,mdss-dsi-panel-physical-type = "oled";
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qcom,mdss-dsi-virtual-channel-id = <0>;
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qcom,mdss-dsi-stream = <0>;
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qcom,mdss-dsi-bpp = <24>;
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qcom,mdss-dsi-border-color = <0>;
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qcom,dsi-ctrl-num = <0>;
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qcom,dsi-phy-num = <0>;
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qcom,dsi-sec-ctrl-num = <1>;
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qcom,dsi-sec-phy-num = <1>;
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qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
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qcom,mdss-dsi-bllp-eof-power-mode;
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qcom,mdss-dsi-bllp-power-mode;
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qcom,mdss-dsi-lane-0-state;
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qcom,mdss-dsi-lane-1-state;
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qcom,mdss-dsi-lane-2-state;
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qcom,mdss-dsi-lane-3-state;
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qcom,mdss-dsi-dma-trigger = "trigger_sw";
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qcom,mdss-dsi-mdp-trigger = "none";
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qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
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qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
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17000 15500 30000 8000 3000>;
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qcom,mdss-dsi-panel-peak-brightness = <4200000>;
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qcom,mdss-dsi-panel-blackness-level = <3230>;
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qcom,mdss-dsi-wr-mem-start = <0x2c>;
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qcom,mdss-dsi-wr-mem-continue = <0x3c>;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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cell-index = <0>;
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qcom,mdss-dsi-panel-framerate = <60>;
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qcom,mdss-dsi-panel-width = <1080>;
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qcom,mdss-dsi-panel-height = <2400>;
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qcom,mdss-dsi-h-front-porch = <20>;
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qcom,mdss-dsi-h-back-porch = <20>;
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qcom,mdss-dsi-h-pulse-width = <2>;
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qcom,mdss-dsi-h-sync-skew = <0>;
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qcom,mdss-dsi-v-back-porch = <18>;
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qcom,mdss-dsi-v-front-porch = <20>;
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qcom,mdss-dsi-v-pulse-width = <2>;
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qcom,mdss-dsi-h-left-border = <0>;
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qcom,mdss-dsi-h-right-border = <0>;
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qcom,mdss-dsi-v-top-border = <0>;
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qcom,mdss-dsi-v-bottom-border = <0>;
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qcom,mdss-dsi-on-command = [
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39 01 00 00 00 00 02 03 01
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39 01 00 00 00 00 02 35 00
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39 01 00 00 00 00 02 53 20
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39 01 00 00 00 00 03 51 00 00
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39 01 00 00 00 00 02 59 00
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39 01 00 00 00 00 02 6C 01
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39 01 00 00 00 00 02 6D 00
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39 01 00 00 00 00 02 6F 01
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39 01 00 00 00 00 5F 70 12 00 00 AB 30
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80 09 60 04 38 00 28 02 1C 02 1C 02
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00 02 0E 00 20 03 DD 00 07 00 0C 02
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77 02 8B 18 00 10 F0 07 10 20 00 06
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0F 0F 33 0E 1C 2A 38 46 54 62 69 70
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77 79 7B 7D 7E 02 02 22 00 2A 40 2A
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BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
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B6 4B B6 4B F4 4B F4 6C 34 84 74 00
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00 00 00 00 00
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39 01 00 00 00 00 03 F0 AA 10
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39 01 00 00 00 00 02 65 16
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39 01 00 00 00 00 03 EB 00 00
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39 01 00 00 00 00 16 B1 01 38 00 14 00
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1C 00 01 66 00 14 00 14 00 01 66 00
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14 05 CC 00
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39 01 00 00 00 00 03 F0 AA 13
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39 01 00 00 00 00 18 CE 09 11 09 11 08
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C1 07 FA 05 A4 00 3C 00 34 00 24 00
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0C 00 0C 04 00 35
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39 01 00 00 00 00 03 F0 AA 14
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39 01 00 00 00 00 03 B2 03 33
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39 01 00 00 00 00 0D B4 00 33 00 00 00
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3E 00 00 00 3E 00 00
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39 01 00 00 00 00 0A B5 00 09 09 09 09
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09 09 06 01
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39 01 00 00 00 00 07 B9 00 00 08 09 09
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09
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39 01 00 00 00 00 0D BC 10 00 00 06 11
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09 3B 09 47 09 47 00
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39 01 00 00 00 00 0D BE 10 10 00 08 22
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09 19 09 25 09 25 00
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39 01 00 00 00 00 03 FF 5A 80
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39 01 00 00 00 00 02 65 14
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39 01 00 00 00 00 04 FA 08 08 08
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39 01 00 00 00 00 03 FF 5A 81
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39 01 00 00 00 00 02 65 05
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39 01 00 00 00 00 02 F3 0F
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39 01 00 00 00 00 03 F0 AA 00
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39 01 00 00 00 00 03 FF 5A 82
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39 01 00 00 00 00 02 F9 00
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39 01 00 00 00 00 03 FF 51 83
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39 01 00 00 00 00 02 65 04
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39 01 00 00 00 00 02 F8 00
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39 01 00 00 00 00 03 FF 5A 00
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39 01 00 00 00 00 02 65 01
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39 01 00 00 00 00 02 F4 9A
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39 01 00 00 00 00 03 FF 5A 00
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05 01 00 00 78 00 01 11
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05 01 00 00 14 00 01 29
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];
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qcom,mdss-dsi-off-command = [
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05 01 00 00 14 00 02 28 00
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05 01 00 00 78 00 02 10 00];
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qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-timing-switch-command-state =
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"dsi_lp_mode";
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qcom,mdss-dsi-h-sync-pulse = <0>;
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qcom,compression-mode = "dsc";
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qcom,mdss-dsc-slice-height = <40>;
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qcom,mdss-dsc-slice-width = <540>;
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qcom,mdss-dsc-slice-per-pkt = <1>;
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qcom,mdss-dsc-bit-per-component = <8>;
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qcom,mdss-dsc-bit-per-pixel = <8>;
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qcom,mdss-dsc-block-prediction-enable;
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};
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};
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};
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};
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262
display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi
Normal file
262
display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi
Normal file
@@ -0,0 +1,262 @@
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// SPDX-License-Identifier: BSD-3-Clause
|
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
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*/
|
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|
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&mdss_mdp {
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dsi_vtdr6130_amoled_90hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_cmd {
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qcom,mdss-dsi-panel-name =
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"vtdr6130 amoled cmd mode dsi visionox panel with DSC";
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qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
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qcom,mdss-dsi-panel-physical-type = "oled";
|
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qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
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qcom,mdss-dsi-bpp = <24>;
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qcom,mdss-dsi-color-order = "rgb_swap_rgb";
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qcom,mdss-dsi-underflow-color = <0xff>;
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qcom,mdss-dsi-border-color = <0>;
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qcom,dsi-ctrl-num = <0>;
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qcom,dsi-phy-num = <0>;
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qcom,dsi-sec-ctrl-num = <1>;
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qcom,dsi-sec-phy-num = <1>;
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qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
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qcom,mdss-dsi-lane-map = "lane_map_0123";
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qcom,mdss-dsi-bllp-eof-power-mode;
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qcom,mdss-dsi-bllp-power-mode;
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qcom,mdss-dsi-lane-0-state;
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qcom,mdss-dsi-lane-1-state;
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qcom,mdss-dsi-lane-2-state;
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qcom,mdss-dsi-lane-3-state;
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qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
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qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
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qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <529675200>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <529675200>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
134
display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi
Normal file
134
display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi
Normal file
@@ -0,0 +1,134 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_90hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled video mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 00
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 02 65 16
|
||||
39 01 00 00 00 00 03 EB 00 00
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
17
display/kera-sde-display-atp-overlay.dts
Normal file
17
display/kera-sde-display-atp-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera ATP";
|
||||
compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap",
|
||||
"qcom,atp";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <33 0>;
|
||||
};
|
17
display/kera-sde-display-cdp-overlay.dts
Normal file
17
display/kera-sde-display-cdp-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera CDP";
|
||||
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
|
||||
"qcom,cdp";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>;
|
||||
};
|
185
display/kera-sde-display-cdp.dtsi
Normal file
185
display/kera-sde-display-cdp.dtsi
Normal file
@@ -0,0 +1,185 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
942
display/kera-sde-display-common.dtsi
Normal file
942
display/kera-sde-display-common.dtsi
Normal file
@@ -0,0 +1,942 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "dsi-panel-sim-cmd.dtsi"
|
||||
#include "dsi-panel-sim-video.dtsi"
|
||||
#include "dsi-panel-sim-dsc375-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-video.dtsi"
|
||||
#include "dsi-panel-sim-sec-hd-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi"
|
||||
|
||||
#include "kera-sde-display-pinctrl.dtsi"
|
||||
|
||||
&soc {
|
||||
dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "dummy";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <220000>;
|
||||
qcom,supply-disable-load = <8000>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <2000000>;
|
||||
qcom,supply-enable-load = <220000>;
|
||||
qcom,supply-disable-load = <8000>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vci";
|
||||
qcom,supply-min-voltage = <3000000>;
|
||||
qcom,supply-max-voltage = <3544000>;
|
||||
qcom,supply-enable-load = <10000>;
|
||||
qcom,supply-disable-load = <300>;
|
||||
qcom,supply-post-on-sleep = <1>;
|
||||
qcom,supply-post-off-sleep = <2>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@2 {
|
||||
reg = <2>;
|
||||
qcom,supply-name = "vdd";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1250000>;
|
||||
qcom,supply-enable-load = <200000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
qcom,supply-post-off-sleep = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi: qcom,dsi-display-primary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "primary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 17 0>;
|
||||
qcom,panel-te-source = <0>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
qcom,demura-panel-id = <0x0122e700 0x00000471>;
|
||||
};
|
||||
|
||||
sde_dsi1: qcom,dsi-display-secondary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "secondary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
|
||||
pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 121 0>;
|
||||
qcom,panel-te-source = <1>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
qcom,demura-panel-id = <0x0 0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PHY TIMINGS REVISION YL with reduced margins */
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,dsi-supported-dfps-list = <144 120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,dsi-supported-dfps-list = <120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 1>,
|
||||
<1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 1>,
|
||||
<1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 1>,
|
||||
<1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <2 2 1>,
|
||||
<1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <2 2 1>,
|
||||
<1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,poms-align-panel-vsync;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS cmd-vid mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
07 07 02 04 00 16 0c];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <50>;
|
||||
};
|
||||
|
||||
timing@1 { /* WQHD 60FPS vid mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
07 07 02 04 00 16 0c];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <50>;
|
||||
};
|
||||
|
||||
timing@2 { /* FHD+ 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08
|
||||
08 08 02 04 00 1a 0d];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <10>;
|
||||
};
|
||||
|
||||
timing@3 { /* HD 60FPS cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <48>;
|
||||
};
|
||||
|
||||
timing@4 { /* FHD+ 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 26 0c
|
||||
0c 0b 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD+ 180 FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 28 16
|
||||
17 14 02 04 00 43 1b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <96>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD+ 240 FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 6f 1f 1f 38 31 1d
|
||||
1f 19 02 04 00 55 23];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <110>;
|
||||
};
|
||||
|
||||
timing@7 { /* FHD+ 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f
|
||||
10 0e 02 04 00 30 14];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <40>;
|
||||
};
|
||||
|
||||
timing@8 { /* FHD+ 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 47 12 13 27 22 12
|
||||
13 10 02 04 00 37 17];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <60>;
|
||||
};
|
||||
|
||||
timing@9 { /* WQHD 1FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0D 18 01
|
||||
00 01 02 04 00 05 05];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@10 { /* WQHD 5FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1D 1A 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@11 { /* WQHD 10FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01
|
||||
01 02 02 04 00 08 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <5>;
|
||||
};
|
||||
|
||||
timing@12 { /* WQHD 24FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 10 1d 03
|
||||
03 02 02 04 00 0b 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <15>;
|
||||
};
|
||||
|
||||
timing@13 { /* WQHD 30FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <22>;
|
||||
};
|
||||
|
||||
timing@14 { /* WQHD 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
|
||||
timing@15 { /* WQHD 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09
|
||||
09 09 02 04 00 1d 0e];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <10>;
|
||||
};
|
||||
|
||||
timing@16 { /* WQHD 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c
|
||||
0c 0b 02 04 00 24 11];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@17 { /* WQHD 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 20 1d 0e
|
||||
0e 0d 02 04 00 2c 13];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <5>;
|
||||
};
|
||||
|
||||
timing@18 { /* WQHD 180FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f
|
||||
10 0e 02 04 00 2f 13];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,qsync-enable;
|
||||
qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>;
|
||||
qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a
|
||||
0a 09 02 04 00 1e 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 1080p */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05
|
||||
05 06 02 04 00 13 0a];
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* qhd */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03
|
||||
03 02 02 04 00 0b 08];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* QHD 60fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05
|
||||
05 06 02 04 00 13 0a];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@1 { /* FHD+ 60fps cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03
|
||||
03 02 02 04 00 0c 08];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@2 { /* QHD 90fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08
|
||||
08 08 02 04 00 19 0d];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@3 { /* FHD+ 180FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2a 0b 0b 1c 1a 0b
|
||||
0c 0b 02 04 00 23 10];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* FHD+ 240FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0e 21 1d 0f
|
||||
0f 0d 02 04 00 2e 13];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD+ 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
|
||||
06 06 02 04 00 13 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD+ 1FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01
|
||||
00 01 02 04 00 05 05];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@7 { /* FHD+ 10FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@8 { /* FHD+ 24FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02
|
||||
01 01 02 04 00 08 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@9 { /* FHD+ 30FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02
|
||||
02 01 02 04 00 09 07];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@10 { /* FHD+ 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 12 1e 04
|
||||
04 03 02 04 00 0f 09];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@11 { /* FHD+ 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07
|
||||
07 07 02 04 00 17 0c];
|
||||
qcom,display-topology = <2 0 2>,
|
||||
<1 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 5K 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11
|
||||
12 0f 02 04 00 35 16];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* FHD 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07
|
||||
07 08 02 04 00 18 0c];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* WQHD 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07
|
||||
07 07 02 04 00 17 0c];
|
||||
qcom,display-topology = <2 0 2>,
|
||||
<1 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@3 { /* 4K 40FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a
|
||||
0a 0a 02 04 00 1f 0f];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* 5K 80FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17
|
||||
18 14 02 04 00 43 1c];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD 60FPS 24bpp cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD 60FPS 30bpp cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 4k 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* 4k 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* 4k 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09
|
||||
09 09 02 04 00 1d 0e];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@3 { /* 1080 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01
|
||||
01 02 02 04 00 08 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* 1080 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* 1080 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04
|
||||
03 03 02 04 00 0d 08];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* 1080 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04
|
||||
04 03 02 04 00 0f 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@7 { /* qhd 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@8 { /* qhd 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@9 { /* qhd 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@10 { /* qhd 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@11 { /* 5k */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07
|
||||
07 07 02 04 00 17 0c];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@12 { /* 720p 30 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@13 { /* 720p 60 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01
|
||||
01 02 02 04 00 08 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@14 { /* 720p 90 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@15 { /* 720 120 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03
|
||||
03 02 02 04 00 0a 08];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@16 { /* 1080 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@17 { /* WQHD 144 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e
|
||||
04 04 03 02 04 00 0e 09];
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
18
display/kera-sde-display-mtp-overlay.dts
Normal file
18
display/kera-sde-display-mtp-overlay.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera MTP";
|
||||
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>,
|
||||
<0x30008 1>;
|
||||
};
|
185
display/kera-sde-display-mtp.dtsi
Normal file
185
display/kera-sde-display-mtp.dtsi
Normal file
@@ -0,0 +1,185 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
114
display/kera-sde-display-pinctrl.dtsi
Normal file
114
display/kera-sde-display-pinctrl.dtsi
Normal file
@@ -0,0 +1,114 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&tlmm {
|
||||
pmx_sde: pmx_sde {
|
||||
sde_dsi_active: sde_dsi_active {
|
||||
mux {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio12";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi_suspend: sde_dsi_suspend {
|
||||
mux {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi1_active: sde_dsi1_active {
|
||||
mux {
|
||||
pins = "gpio127";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio127";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi1_suspend: sde_dsi1_suspend {
|
||||
mux {
|
||||
pins = "gpio127";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio127";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmx_sde_te: pmx_sde_te {
|
||||
sde_te_active: sde_te_active {
|
||||
mux {
|
||||
pins = "gpio17";
|
||||
function = "mdp_vsync_p";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio17";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te_suspend: sde_te_suspend {
|
||||
mux {
|
||||
pins = "gpio17";
|
||||
function = "mdp_vsync_p";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio17";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te1_active: sde_te1_active {
|
||||
mux {
|
||||
pins = "gpio121";
|
||||
function = "mdp_vsync_s";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio121";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te1_suspend: sde_te1_suspend {
|
||||
mux {
|
||||
pins = "gpio121";
|
||||
function = "mdp_vsync_s";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio121";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
17
display/kera-sde-display-qrd-overlay.dts
Normal file
17
display/kera-sde-display-qrd-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera QRD";
|
||||
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
|
||||
};
|
185
display/kera-sde-display-qrd.dtsi
Normal file
185
display/kera-sde-display-qrd.dtsi
Normal file
@@ -0,0 +1,185 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
18
display/kera-sde-display-rcm-overlay.dts
Normal file
18
display/kera-sde-display-rcm-overlay.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera RCM";
|
||||
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
|
||||
"qcom,rcm";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>,
|
||||
<0x30015 1>;
|
||||
};
|
16
display/kera-sde-display-rumi-overlay.dts
Normal file
16
display/kera-sde-display-rumi-overlay.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-sde-display-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera RUMI";
|
||||
compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi";
|
||||
qcom,msm-id = <659 0x10000>;
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
11
display/kera-sde-display-rumi.dtsi
Normal file
11
display/kera-sde-display-rumi.dtsi
Normal file
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-sde-display.dtsi"
|
||||
|
||||
&mdss_mdp {
|
||||
qcom,sde-emulated-env;
|
||||
};
|
||||
|
@@ -19,8 +19,8 @@
|
||||
&sde_dsi {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
<&mdss_dsi_phy1 0>,
|
||||
<&mdss_dsi_phy1 1>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
@@ -48,8 +48,8 @@
|
||||
&sde_dsi1 {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
<&mdss_dsi_phy1 0>,
|
||||
<&mdss_dsi_phy1 1>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
|
@@ -248,7 +248,6 @@
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-1p2-supply = <&L4B>;
|
||||
qcom,split-link-supported;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
@@ -262,7 +261,6 @@
|
||||
|
||||
&mdss_dsi1 {
|
||||
vdda-1p2-supply = <&L4B>;
|
||||
qcom,split-link-supported;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
|
Reference in New Issue
Block a user