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Change-Id: I9548c4e372161177c694c2734d56d239cf249832
This commit is contained in:
Linux Build Service Account
2025-03-17 11:03:28 -07:00
parent dbd3507af7 7cd5aa0fed
commit 72ae49734e
19 changed files with 403 additions and 16 deletions
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57
bindings/firmware/qcom,hwkm.yaml Normal file
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@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/qcom,hwkm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HWKM (Hardware Key Manager)
maintainers:
- Neeraj Soni <quic_neersoni@quicinc.com>
- Debraj Mukhopadhyay <quic_dmukhopa@quicinc.com>
- Gaurav Kashyap <quic_gaurkash@quicinc.com>
description: |
The HWKM driver is a platform device driver that helps
communicating with both the master and slave blocks of the
hardware key manager to issue commands to perform key operations
mainly required for storage encryption.
properties:
compatible:
const: "qcom,hwkm"
reg:
description: |
Register set for both master and slaves.
reg-names:
description: |
Identifiers for parsing master and slave regs.
clocks:
description: |
clocks needed for operating master and the slave.
clock-names:
description: |
name identifiers corresponding to the clocks.
qcom,enable-hwkm-clk: to ensure clocks can be handled by HLOS.
qcom,op-freq-hz: Max frequency of the listed clocks.
required:
- compatible
additionalProperties: false
examples:
- |
qcom_hwkm: hwkm@10c0000 {
compatible = "qcom,hwkm";
reg = <0x10c0000 0x9000>, <0x1d90000 0x9000>;
reg-names = "km_master", "ice_slave";
qcom,enable-hwkm-clk;
clock-names = "km_clk_src";
clocks = <&clock_rpmh RPMH_HWKM_CLK>;
qcom,op-freq-hz = <75000000>;
};

1
bindings/nvmem/qcom,qfprom.yaml
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@@ -24,6 +24,7 @@ properties:
- qcom,msm8996-qfprom
- qcom,msm8998-qfprom
- qcom,qcs404-qfprom
- qcom,parrot-qfprom
- qcom,sc7180-qfprom
- qcom,sc7280-qfprom
- qcom,sdm630-qfprom

112
bindings/pci/qcom,msm_mhi_dev.yaml Normal file
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@@ -0,0 +1,112 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,msm_mhi_dev.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) MSM MHI Device
maintainers:
- Anvita T <quic_atadepal@quicinc.com>
properties:
compatible:
enum:
- qcom,msm-mhi-dev
reg:
minItems: 1
items:
- description: MHI MMIO physical register space.
- description: IPA uC Command Ring doorbell mail box address.
- description: IPA uC Event Ring doorbell mail box address.
reg-names:
minItems: 1
items:
- const: mhi_mmio_base
- const: ipa_uc_mbox_crdb
- const: ipa_uc_mbox_erdb
interrupts:
items:
- description: Interrupt line for the device.
interrupt-names:
items:
- const: mhi-device-inta
qcom,mhi-ifc-id:
description: ID of HW interface via which MHI on device side communicates with host side.
qcom,mhi-ep-msi:
description: End point MSI number.
qcom,mhi-version:
description: MHI specification version supported by the device.
qcom,use-mhi-dma-software-channel:
description: Uses IPA hardware accelerated path for MHI software channel data transfers between host and device.
qcom,mhi-config-iatu:
description: Maps the control and data region between host and device using iatu.
qcom,mhi-interrupt:
description: Registers for mhi interrupt.
qcom,mhi-local-pa-base:
description: The physical base address on the device used by the MHI device driver to map
the control and data region with the MHI driver on the host. This property is
required if iatu property qcom,mhi-config-iatu is present.
qcom,enable-m2:
description: M2 autonomous is enabled.
qcom,mhi-has-smmu:
description: Uses mapped address to route the doorbell addresses to IPA.
qcom,mhi-num-ipc-pages-dev-fac:
description: Reduces the MHI ipc logging size based on the divisor factor.
This property also represents the divisor factor.
qcom,no-m0-timeout:
description: Device waits for M0 state without any timeout period.
mhi-virt-device-int-x:
description: To be used if the target supports virtual functions.
The property lists the interrupt number for the virtual functions.
Replace x with the appropriate interrupt number.
qcom,use-pcie-edma:
description: Uses eDMA as DMA for MHI software channel data transfers between host and device.
qcom,mhi-chan-hw-base:
description: If the target uses any other h/w channel than ch-100 as the start of the hardware
accelerated channel, then use this property to mention the start h/w channel.
qcom,mhi-is-flashless:
description: If the target uses flashless boot (boot over PCIe) then mention this property.
required:
- compatible
- reg
- reg-names
- qcom,mhi-ifc-id
- qcom,mhi-ep-msi
- qcom,mhi-version
unevaluatedProperties: false
examples:
- |
mhi: qcom,msm-mhi-dev {
compatible = "qcom,msm-mhi-dev";
reg = <0xfc527000 0x1000>,
<0xfd4fa000 0x1>,
<0xfd4fa080 0x1>;
reg-names = "mhi_mmio_base", "ipa_uc_mbox_crdb","ipa_uc_mbox_erdb";
qcom,mhi-ifc-id = <0x030017cb>;
qcom,mhi-ep-msi = <1>;
qcom,mhi-version = <0x1000000>;
};

35
bindings/pci/qcom,msm_mhi_net_dev.yaml Normal file
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@@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,msm_mhi_net_dev.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) MSM MHI NET Device
maintainers:
- Anvita T <quic_atadepal@quicinc.com>
properties:
compatible:
enum:
- qcom,msm-mhi-dev-net
qcom,mhi-ethernet-interface-ch-list:
description: Channels list which expects Ethernet packet parsing support.
qcom,tx_rx_reqs:
description: If property present it will override the number of elements in
rx and tx queues for mhi_dev_net device.(Default:128)
required:
- compatible
unevaluatedProperties: false
examples:
- |
qcom,mhi_net_dev {
compatible = "qcom,msm-mhi-dev-net";
qcom,mhi-ethernet-interface;
};

45
bindings/soc/qcom/qcom,pmic-ecid.yaml Normal file
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@@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,pmic-ecid.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PMIC ECID Identification
maintainers:
- Brindha T <quic_brint@quicinc.com>
description: |
PMIC ECID (Exclusive Chip Identifier) device to provide information on PMIC specific part identification.
properties:
compatible:
const: qcom,pmic-ecid
reg:
description: Specifies the SPMI base address of PMIC ECID
maxItems: 1
qcom,pmic-name:
$ref: /schemas/types.yaml#/definitions/string
description: Specifies the PMIC name
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pmic {
#address-cells = <1>;
#size-cells = <0>;
qcom-pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550";
};
};
...

10
qcom/kera-qrd.dtsi
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@@ -80,9 +80,9 @@
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1393@34 {
qcom,smb1393@35 {
compatible = "qcom,i2c-pmic";
reg = <0x34>;
reg = <0x35>;
qcom,can-sleep;
};
};
@@ -92,17 +92,17 @@
status = "ok";
smb1393_1_iin {
reg = <0x1053401>;
reg = <0x1053501>;
label = "smb1393_1_iin";
};
smb1393_1_ichg {
reg = <0x1053402>;
reg = <0x1053502>;
label = "smb1393_1_ichg";
};
smb1393_1_die_temp {
reg = <0x1053403>;
reg = <0x1053503>;
label = "smb1393_1_die_temp";
};
};

1
qcom/kera-usb.dtsi
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@@ -41,6 +41,7 @@
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,core-clk-rate-disconnected = <133333333>;
qcom,pm-qos-latency = <2>;
qcom,use-pdc-interrupts;
qcom,use-eusb2-phy;

12
qcom/monaco.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -611,6 +611,16 @@
compatible = "qcom,smcinvoke";
};
qcom_hwkm: hwkm@4440000 {
compatible = "qcom,hwkm";
reg = <0x4440000 0x9000>;
reg-names = "km_master";
qcom,enable-hwkm-clk;
clock-names = "km_clk_src";
clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
qcom,op-freq-hz = <75000000>;
};
qcom_tzlog: tz-log@c125720 {
compatible = "qcom,tz-log";
reg = <0xc125720 0x3000>;

2
qcom/parrot.dtsi
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@@ -2554,7 +2554,7 @@
qfprom: qfprom@221c8000 {
compatible = "qcom,qfprom";
compatible = "qcom,parrot-qfprom", "qcom,qfprom";
reg = <0x221c8000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;

14
qcom/pm8010.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -18,6 +18,12 @@
#address-cells = <1>;
#size-cells = <0>;
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8010_m";
};
pm8010m_tz: pm8010m-temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
@@ -32,6 +38,12 @@
#address-cells = <1>;
#size-cells = <0>;
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8010_n";
};
pm8010n_tz: pm8010n-temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;

8
qcom/pm8550.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -19,6 +19,12 @@
#address-cells = <1>;
#size-cells = <0>;
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550";
};
pm8550_tz: pm8550-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;

26
qcom/pm8550ve.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -19,6 +19,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550ve_d";
};
pm8550ve_d_tz: pm8550ve-d-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -43,6 +49,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550ve_f";
};
pm8550ve_f_tz: pm8550ve-f-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -67,6 +79,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550ve_g";
};
pm8550ve_g_tz: pm8550ve-g-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -91,6 +109,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550ve_i";
};
pm8550ve_i_tz: pm8550ve-i-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;

38
qcom/pm8550vs.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -19,6 +19,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550vs_c";
};
pm8550vs_c_tz: pm8550vs-c-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -43,6 +49,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550vs_d";
};
pm8550vs_d_tz: pm8550vs-d-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -67,6 +79,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550vs_e";
};
pm8550vs_e_tz: pm8550vs-e-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -91,6 +109,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550vs_f";
};
pm8550vs_f_tz: pm8550vs-f-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -115,6 +139,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550vs_g";
};
pm8550vs_g_tz: pm8550vs-g-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -139,6 +169,12 @@
#size-cells = <0>;
status = "disabled";
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pm8550vs_j";
};
pm8550vs_j_tz: pm8550vs-j-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;

8
qcom/pmd802x.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -18,6 +18,12 @@
#address-cells = <1>;
#size-cells = <0>;
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pmd802x";
};
pmd802x_tz: pmd802x-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;

8
qcom/pmih010x.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -19,6 +19,12 @@
#address-cells = <1>;
#size-cells = <0>;
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pmih010x";
};
pmih010x_tz: pmih010x-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;

8
qcom/pmk8550.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/input/input.h>
@@ -24,6 +24,12 @@
#address-cells = <1>;
#size-cells = <0>;
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pmk8550";
};
pmk8550_sdam_1: sdam@7000 {
compatible = "qcom,spmi-sdam";
reg = <0x7000>;

8
qcom/pmr735d.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -18,6 +18,12 @@
#address-cells = <1>;
#size-cells = <0>;
pmic-ecid@100 {
compatible = "qcom,pmic-ecid";
reg = <0x100>;
qcom,pmic-name = "pmr735d";
};
pmr735d_tz: pmr735d-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;

23
qcom/sdxkova.dtsi
View File

@@ -298,6 +298,29 @@
compatible = "qcom,sdxkova-pcie-pdc", "qcom,pcie-pdc";
reg = <0x0 0xb2b0000 0x0 0x30000>;
};
cpuss-sleep-stats@17800054 {
compatible = "qcom,cpuss-sleep-stats-v2";
reg = <0x0 0x17800054 0x0 0x4>, <0x0 0x17810054 0x0 0x4>, <0x0 0x17820054 0x0 0x4>,
<0x0 0x17830054 0x0 0x4>, <0x0 0x17880098 0x0 0x4>, <0x0 0x178c0000 0x0 0x10000>;
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
num-cpus = <4>;
};
sram@c3f0000 {
compatible = "qcom,rpmh-stats-v4";
reg = <0x0 0xc3f0000 0x0 0x400>;
qcom,qmp = <&aoss_qmp>;
ss-name = "modem", "apss";
};
sys-pm-vx@c300000 {
compatible = "qcom,sys-pm-violators", "qcom,sys-pm-sdxkova";
reg = <0x0 0xc300000 0x0 0x400>;
qcom,qmp = <&aoss_qmp>;
};
};
firmware: firmware { };

3
qcom/sun-pcie.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-sun.h>
@@ -214,6 +214,7 @@
0x0814 0x07 0x0
0x0820 0xc1 0x0
0x0894 0x00 0x0
0x08f8 0x1f 0x0
0x05d0 0x8c 0x0
0x0568 0x17 0x0
0x0570 0x2e 0x0