Merge commit 'e203547e9ac1ca186b0866fe1276a00075d8eb06' into kernel.lnx.6.6.r1-rel
Change-Id: I7fc62dd0516b8a2d27ac3a00dffe469d0fcaa055 Signed-off-by: Akhil Kallankandy <quic_c_akhika@quicinc.com>
This commit is contained in:
Akhil Kallankandy
@@ -21,6 +21,7 @@ properties:
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enum:
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- qcom,sun-camcc
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- qcom,tuna-camcc
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- qcom,kera-camcc
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clocks:
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items:
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@@ -22,6 +22,7 @@ properties:
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- qcom,sdx75-debugcc
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- qcom,sm4450-debugcc
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- qcom,monaco-debugcc
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- qcom,tuna-debugcc
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clocks:
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items:
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@@ -31,6 +31,8 @@ properties:
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- qcom,sm6115-qfprom
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- qcom,sun-qfprom
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- qcom,ravelin-qfprom
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- qcom,tuna-qfprom
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- qcom,kera-qfprom
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- const: qcom,qfprom
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reg:
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190
bindings/pinctrl/qcom,tuna-vm-tlmm.yaml
Normal file
190
bindings/pinctrl/qcom,tuna-vm-tlmm.yaml
Normal file
@@ -0,0 +1,190 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,tuna-vm-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SUN VM TLMM block
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maintainers:
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- Murali Nalajala <quic_mnalajal@quicinc.com>
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- Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>
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description: |
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This binding describes the Top Level Mode Multiplexer block for VM.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,tuna-vm-tlmm
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reg:
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maxItems: 1
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interrupts-extended: true
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interrupt-controller: true
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'#interrupt-cells': true
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gpio-controller: true
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'#gpio-cells': true
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gpio-ranges: true
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gpios:
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description: array of gpio pin number required by VM TLMM clients
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required:
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- compatible
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- reg
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additionalProperties: false
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patternProperties:
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'-state$':
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oneOf:
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- $ref: "#/$defs/qcom-tuna-vm-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-tuna-vm-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-tuna-vm-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$"
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3,
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atest_char_start, atest_usb0, atest_usb00, atest_usb01,
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atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1,
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audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk,
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cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0,
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cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4,
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cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2,
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cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0,
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cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0,
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cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx,
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coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete,
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ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
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ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2,
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gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0,
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i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0,
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i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0,
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i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0,
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i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0,
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i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0,
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i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck,
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i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1,
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mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,
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mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
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nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1,
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phase_flag10, phase_flag11, phase_flag12, phase_flag13,
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phase_flag14, phase_flag15, phase_flag16, phase_flag17,
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phase_flag18, phase_flag19, phase_flag2, phase_flag20,
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phase_flag21, phase_flag22, phase_flag23, phase_flag24,
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phase_flag25, phase_flag26, phase_flag27, phase_flag28,
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phase_flag29, phase_flag3, phase_flag30, phase_flag31,
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phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8,
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phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
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prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0,
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qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
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qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4,
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qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
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qlink_big_enable, qlink_big_request, qlink_little_enable,
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qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3,
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qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2,
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qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3,
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qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4,
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qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2,
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qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3,
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qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0,
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qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1,
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qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2,
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qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3,
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qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4,
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qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2,
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qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3,
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qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6,
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qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0,
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qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40,
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sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2,
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tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2,
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tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
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uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
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uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0,
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vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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allOf:
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- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
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- if:
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properties:
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pins:
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pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
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then:
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required:
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- function
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@f100000 {
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compatible = "qcom,tuna-vm-tlmm";
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reg = <0x0f100000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 211>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts-extended = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-state {
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rx-pins {
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pins = "gpio26";
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function = "qup1_se7_l0";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio27";
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function = "qup1_se7_l1";
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bias-disable;
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};
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};
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};
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...
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@@ -63,15 +63,22 @@ properties:
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- qcom,sun-cdsp-pas
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- qcom,sun-modem-pas
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- qcom,sun-soccp-pas
|
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- qcom,tuna-adsp-pas
|
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- qcom,tuna-cdsp-pas
|
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- qcom,tuna-modem-pas
|
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- qcom,parrot-adsp-pas
|
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- qcom,parrot-cdsp-pas
|
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- qcom,parrot-modem-pas
|
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- qcom,parrot-wpss-pas
|
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- qcom,kera-adsp-pas
|
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- qcom,kera-cdsp-pas
|
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- qcom,kera-modem-pas
|
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- qcom,ravelin-adsp-pas
|
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- qcom,ravelin-modem-pas
|
||||
- qcom,ravelin-wpss-pas
|
||||
- qcom,monaco-modem-pas
|
||||
- qcom,monaco-adsp-pas
|
||||
- qcom,tuna-wpss-pas
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -85,6 +85,13 @@ properties:
|
||||
description: >
|
||||
which of the PMIC Arb provided channels to use for accesses
|
||||
|
||||
qcom,mid:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
description: >
|
||||
SPMI master ID of this controller.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg-names
|
||||
|
||||
@@ -52,7 +52,7 @@ sun-dtb-$(CONFIG_ARCH_SUN) += \
|
||||
$(call add-overlays, $(SUN_BOARDS) $(APQ_SUN_BOARDS),$(SUN_APQ_BASE_DTB))
|
||||
sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB)
|
||||
|
||||
TUNA_BASE_DTB += tuna.dtb
|
||||
TUNA_BASE_DTB += tuna.dtb tuna7.dtb
|
||||
NOAPQ_TUNA_BOARDS += \
|
||||
tuna-atp-overlay.dtbo \
|
||||
tuna-cdp-overlay.dtbo \
|
||||
@@ -210,6 +210,30 @@ dtb-y += $(sun_tuivm-dtb-y)
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_TUNA), y)
|
||||
ifeq ($(CONFIG_ARCH_QTI_VM), y)
|
||||
tuna_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += tuna-vm-rumi.dtb \
|
||||
tuna-vm-atp.dtb \
|
||||
tuna-vm-cdp.dtb \
|
||||
tuna-vm-mtp.dtb \
|
||||
tuna-vm-mtp-kiwi.dtb \
|
||||
tuna-vm-mtp-qmp1000.dtb \
|
||||
tuna-vm-qrd.dtb \
|
||||
tuna-vm-rcm.dtb \
|
||||
tuna-vm-rcm-kiwi.dtb \
|
||||
tuna-oemvm-rumi.dtb \
|
||||
tuna-oemvm-atp.dtb \
|
||||
tuna-oemvm-cdp.dtb \
|
||||
tuna-oemvm-mtp.dtb \
|
||||
tuna-oemvm-mtp-kiwi.dtb \
|
||||
tuna-oemvm-mtp-qmp1000.dtb \
|
||||
tuna-oemvm-qrd.dtb \
|
||||
tuna-oemvm-rcm.dtb \
|
||||
tuna-oemvm-rcm-kiwi.dtb
|
||||
dtb-y += $(tuna_tuivm-dtb-y)
|
||||
endif
|
||||
endif
|
||||
|
||||
MONACO_BASE_DTB += monaco.dtb monacop.dtb
|
||||
|
||||
MONACO_BOARDS += \
|
||||
|
||||
461
qcom/kera-debug.dtsi
Normal file
461
qcom/kera-debug.dtsi
Normal file
@@ -0,0 +1,461 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/soc/qcom,dcc_v2.h>
|
||||
|
||||
&reserved_memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
dump_mem: mem_dump_region {
|
||||
alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
|
||||
size = <0x0 0x1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
dcc: dcc_v2@100ff000 {
|
||||
compatible = "qcom,dcc-v2";
|
||||
reg = <0x100ff000 0x1000>,
|
||||
<0x10084000 0x4000>;
|
||||
|
||||
status = "disabled";
|
||||
qcom,transaction_timeout = <0>;
|
||||
|
||||
reg-names = "dcc-base", "dcc-ram-base";
|
||||
dcc-ram-offset = <0x4000>;
|
||||
};
|
||||
|
||||
mem_dump {
|
||||
compatible = "qcom,mem-dump";
|
||||
memory-region = <&dump_mem>;
|
||||
|
||||
static_dump {
|
||||
qcom,static-mem-dump;
|
||||
|
||||
c0_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x0>;
|
||||
};
|
||||
|
||||
c100_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x1>;
|
||||
};
|
||||
|
||||
c200_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x2>;
|
||||
};
|
||||
|
||||
c300_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x3>;
|
||||
};
|
||||
|
||||
c400_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x4>;
|
||||
};
|
||||
|
||||
c500_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x5>;
|
||||
};
|
||||
|
||||
c600_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x6>;
|
||||
};
|
||||
|
||||
c700_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x7>;
|
||||
};
|
||||
|
||||
l1_icache0 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x60>;
|
||||
};
|
||||
|
||||
l1_icache100 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x61>;
|
||||
};
|
||||
|
||||
l1_icache200 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x62>;
|
||||
};
|
||||
|
||||
l1_icache300 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x63>;
|
||||
};
|
||||
|
||||
l1_icache400 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x64>;
|
||||
};
|
||||
|
||||
l1_icache500 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x65>;
|
||||
};
|
||||
|
||||
l1_icache600 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x66>;
|
||||
};
|
||||
|
||||
l1_icache700 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x67>;
|
||||
};
|
||||
|
||||
l1_dcache0 {
|
||||
qcom,dump-size = <0x12100>;
|
||||
qcom,dump-id = <0x80>;
|
||||
};
|
||||
|
||||
l1_dcache100 {
|
||||
qcom,dump-size = <0x12100>;
|
||||
qcom,dump-id = <0x81>;
|
||||
};
|
||||
|
||||
l1_dcache200 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x82>;
|
||||
};
|
||||
|
||||
l1_dcache300 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x83>;
|
||||
};
|
||||
|
||||
l1_dcache400 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x84>;
|
||||
};
|
||||
|
||||
l1_dcache500 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x85>;
|
||||
};
|
||||
|
||||
l1_dcache600 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x86>;
|
||||
};
|
||||
|
||||
l1_dcache700 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x87>;
|
||||
};
|
||||
|
||||
l1_itlb700 {
|
||||
qcom,dump-size = <0x600>;
|
||||
qcom,dump-id = <0x27>;
|
||||
};
|
||||
|
||||
l1_dtlb700 {
|
||||
qcom,dump-size = <0xa00>;
|
||||
qcom,dump-id = <0x47>;
|
||||
};
|
||||
|
||||
l2_cache0 {
|
||||
qcom,dump-size = <0x90100>;
|
||||
qcom,dump-id = <0xc0>;
|
||||
};
|
||||
|
||||
l2_cache100 {
|
||||
qcom,dump-size = <0x90100>;
|
||||
qcom,dump-id = <0xc1>;
|
||||
};
|
||||
|
||||
l2_cache200 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc2>;
|
||||
};
|
||||
|
||||
l2_cache300 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc3>;
|
||||
};
|
||||
|
||||
l2_cache400 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc4>;
|
||||
};
|
||||
|
||||
l2_cache500 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc5>;
|
||||
};
|
||||
|
||||
l2_cache600 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc6>;
|
||||
};
|
||||
|
||||
l2_cache700 {
|
||||
qcom,dump-size = <0x340100>;
|
||||
qcom,dump-id = <0xc7>;
|
||||
};
|
||||
|
||||
l2_tlb0 {
|
||||
qcom,dump-size = <0xf700>;
|
||||
qcom,dump-id = <0x120>;
|
||||
};
|
||||
|
||||
l2_tlb100 {
|
||||
qcom,dump-size = <0xf700>;
|
||||
qcom,dump-id = <0x121>;
|
||||
};
|
||||
|
||||
l2_tlb700 {
|
||||
qcom,dump-size = <0xa900>;
|
||||
qcom,dump-id = <0x127>;
|
||||
};
|
||||
|
||||
l1dcdirty0 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x170>;
|
||||
};
|
||||
|
||||
l1dcdirty100 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x171>;
|
||||
};
|
||||
|
||||
l1dcmte0 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x180>;
|
||||
};
|
||||
|
||||
l1dcmte100 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x181>;
|
||||
};
|
||||
|
||||
l2dcmte0 {
|
||||
qcom,dump-size = <0x10100>;
|
||||
qcom,dump-id = <0x190>;
|
||||
};
|
||||
|
||||
l2dcmte100 {
|
||||
qcom,dump-size = <0x10100>;
|
||||
qcom,dump-id = <0x191>;
|
||||
};
|
||||
|
||||
l0mopca700 {
|
||||
qcom,dump-size = <0x4100>;
|
||||
qcom,dump-id = <0x1a7>;
|
||||
};
|
||||
|
||||
l2victim700 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x1e7>;
|
||||
};
|
||||
|
||||
l2tldtcsp200 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x202>;
|
||||
};
|
||||
|
||||
l2tldtcsp300 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x203>;
|
||||
};
|
||||
|
||||
l2tldtcsp400 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x204>;
|
||||
};
|
||||
|
||||
l2tldtcsp500 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x205>;
|
||||
};
|
||||
|
||||
l2tldtcsp600 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x206>;
|
||||
};
|
||||
|
||||
l2tldtcmp200 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x212>;
|
||||
};
|
||||
|
||||
l2tldtcmp300 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x213>;
|
||||
};
|
||||
|
||||
l2tldtcmp400 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x214>;
|
||||
};
|
||||
|
||||
l2tldtcmp500 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x215>;
|
||||
};
|
||||
|
||||
l2tldtcmp600 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x216>;
|
||||
};
|
||||
|
||||
rpmh {
|
||||
qcom,dump-size = <0x400000>;
|
||||
qcom,dump-id = <0xec>;
|
||||
};
|
||||
|
||||
rpm_sw {
|
||||
qcom,dump-size = <0x28000>;
|
||||
qcom,dump-id = <0xea>;
|
||||
};
|
||||
|
||||
pmic {
|
||||
qcom,dump-size = <0x200000>;
|
||||
qcom,dump-id = <0xe4>;
|
||||
};
|
||||
|
||||
fcm {
|
||||
qcom,dump-size = <0x8400>;
|
||||
qcom,dump-id = <0xee>;
|
||||
};
|
||||
|
||||
etf_swao {
|
||||
qcom,dump-size = <0x10000>;
|
||||
qcom,dump-id = <0xf1>;
|
||||
};
|
||||
|
||||
etr_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x100>;
|
||||
};
|
||||
|
||||
etfswao_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x102>;
|
||||
};
|
||||
|
||||
etr1_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x105>;
|
||||
};
|
||||
|
||||
misc_data {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0xe8>;
|
||||
};
|
||||
|
||||
etf_slpi {
|
||||
qcom,dump-size = <0x4000>;
|
||||
qcom,dump-id = <0xf3>;
|
||||
};
|
||||
|
||||
etfslpi_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x103>;
|
||||
};
|
||||
|
||||
etf_lpass {
|
||||
qcom,dump-size = <0x4000>;
|
||||
qcom,dump-id = <0xf4>;
|
||||
};
|
||||
|
||||
etflpass_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x104>;
|
||||
};
|
||||
|
||||
osm_reg {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x163>;
|
||||
};
|
||||
|
||||
pcu_reg {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x164>;
|
||||
};
|
||||
|
||||
fsm_data {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x165>;
|
||||
};
|
||||
|
||||
scandump_smmu {
|
||||
qcom,dump-size = <0x40000>;
|
||||
qcom,dump-id = <0x220>;
|
||||
};
|
||||
};
|
||||
|
||||
dynamic_mem_dump {
|
||||
qcom,dynamic-mem-dump;
|
||||
|
||||
scandump_gpu {
|
||||
scandump_gpu {
|
||||
qcom,dump-size = <0x300000>;
|
||||
qcom,dump-id = <0x221>;
|
||||
};
|
||||
};
|
||||
|
||||
cpuss_reg {
|
||||
cpuss_reg {
|
||||
qcom,dump-size = <0x36000>;
|
||||
qcom,dump-id = <0xef>;
|
||||
};
|
||||
};
|
||||
|
||||
spr {
|
||||
spr_cpu0 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f0>;
|
||||
};
|
||||
|
||||
spr_cpu1 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f1>;
|
||||
};
|
||||
|
||||
spr_cpu2 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f2>;
|
||||
};
|
||||
|
||||
spr_cpu3 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f3>;
|
||||
};
|
||||
|
||||
spr_cpu4 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f4>;
|
||||
};
|
||||
|
||||
spr_cpu5 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f5>;
|
||||
};
|
||||
|
||||
spr_cpu6 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f6>;
|
||||
};
|
||||
|
||||
spr_cpu7 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
615
qcom/kera-stub-regulators.dtsi
Normal file
615
qcom/kera-stub-regulators.dtsi
Normal file
@@ -0,0 +1,615 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
&soc {
|
||||
|
||||
S1B:
|
||||
pmxr2230_s1: regulator-pmxr2230-s1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_s1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1856000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
|
||||
S2B:
|
||||
pmxr2230_s2: regulator-pmxr2230-s2 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_s2";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1020000>;
|
||||
regulator-max-microvolt = <2100000>;
|
||||
};
|
||||
|
||||
S3B:
|
||||
pmxr2230_s3: regulator-pmxr2230-s3 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_s3";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <375000>;
|
||||
regulator-max-microvolt = <2744000>;
|
||||
};
|
||||
|
||||
S4B:
|
||||
pmxr2230_s4: regulator-pmxr2230-s4 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_s4";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2156000>;
|
||||
regulator-max-microvolt = <2400000>;
|
||||
};
|
||||
|
||||
VDD_NSP1_LEVEL:
|
||||
S5B_LEVEL:
|
||||
pmxr2230_s5_level: regulator-pmxr2230-s5-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_s5_level";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
L1B:
|
||||
pmxr2230_l1: regulator-pmxr2230-l1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <870000>;
|
||||
regulator-max-microvolt = <970000>;
|
||||
};
|
||||
|
||||
L2B:
|
||||
pmxr2230_l2: regulator-pmxr2230-l2 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l2";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <720000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
};
|
||||
|
||||
L4B:
|
||||
pmxr2230_l4: regulator-pmxr2230-l4 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l4";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1080000>;
|
||||
regulator-max-microvolt = <1320000>;
|
||||
};
|
||||
|
||||
L5B:
|
||||
pmxr2230_l5: regulator-pmxr2230-l5 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l5";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1140000>;
|
||||
regulator-max-microvolt = <1260000>;
|
||||
};
|
||||
|
||||
L6B:
|
||||
pmxr2230_l6: regulator-pmxr2230-l6 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l6";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1170000>;
|
||||
regulator-max-microvolt = <1370000>;
|
||||
};
|
||||
|
||||
L7B:
|
||||
pmxr2230_l7: regulator-pmxr2230-l7 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l7";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1080000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
L8B:
|
||||
pmxr2230_l8: regulator-pmxr2230-l8 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l8";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
L9B:
|
||||
pmxr2230_l9: regulator-pmxr2230-l9 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l9";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <756000>;
|
||||
regulator-max-microvolt = <816000>;
|
||||
};
|
||||
|
||||
L10B:
|
||||
pmxr2230_l10: regulator-pmxr2230-l10 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l10";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <866000>;
|
||||
regulator-max-microvolt = <958000>;
|
||||
};
|
||||
|
||||
L11B:
|
||||
pmxr2230_l11: regulator-pmxr2230-l11 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l11";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
};
|
||||
|
||||
L12B:
|
||||
pmxr2230_l12: regulator-pmxr2230-l12 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l12";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2400000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
L13B:
|
||||
pmxr2230_l13: regulator-pmxr2230-l13 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l13";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
L14B:
|
||||
pmxr2230_l14: regulator-pmxr2230-l14 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l14";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2650000>;
|
||||
regulator-max-microvolt = <2940000>;
|
||||
};
|
||||
|
||||
L15B:
|
||||
pmxr2230_l15: regulator-pmxr2230-l15 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l15";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
L16B:
|
||||
pmxr2230_l16: regulator-pmxr2230-l16 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l16";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2600000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
L17B:
|
||||
pmxr2230_l17: regulator-pmxr2230-l17 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l17";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
L18B:
|
||||
pmxr2230_l18: regulator-pmxr2230-l18 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l18";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
L19B:
|
||||
pmxr2230_l19: regulator-pmxr2230-l19 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l19";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2600000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
L20B:
|
||||
pmxr2230_l20: regulator-pmxr2230-l20 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l20";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
L21B:
|
||||
pmxr2230_l21: regulator-pmxr2230-l21 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l21";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
L22B:
|
||||
pmxr2230_l22: regulator-pmxr2230-l22 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l22";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
};
|
||||
|
||||
L23B:
|
||||
pmxr2230_l23: regulator-pmxr2230-l23 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l23";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
VDD_MX_LEVEL:
|
||||
S1D_LEVEL:
|
||||
pm_v6d_s1_level: regulator-pm_v6d-s1-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_s1_level";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
VDD_MX_LEVEL_AO:
|
||||
S1D_LEVEL_AO:
|
||||
pm_v6d_s1_level_ao: regulator-pm_v6d-s1-level-ao {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_s1_level_ao";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
VDD_EBI_LEVEL:
|
||||
S3D_LEVEL:
|
||||
pm_v6d_s3_level: regulator-pm_v6d-s3-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_s3_level";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
VDD_MODEM_LEVEL:
|
||||
S4D_LEVEL:
|
||||
pm_v6d_s4_level: regulator-pm_v6d-s4-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_s4_level";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
VDD_CX_LEVEL:
|
||||
S5D_LEVEL:
|
||||
pm_v6d_s5_level: regulator-pm_v6d-s5-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_s5_level";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
VDD_CX_LEVEL_AO:
|
||||
S5D_LEVEL_AO:
|
||||
pm_v6d_s5_level_ao: regulator-pm_v6d-s5-level-ao {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_s5_level_ao";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
L1D:
|
||||
pm_v6d_l1: regulator-pm_v6d-l1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_l1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <866000>;
|
||||
regulator-max-microvolt = <958000>;
|
||||
};
|
||||
|
||||
L2D:
|
||||
pm_v6d_l2: regulator-pm_v6d-l2 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_l2";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <556000>;
|
||||
regulator-max-microvolt = <816000>;
|
||||
};
|
||||
|
||||
VDD_LPI_CX_LEVEL:
|
||||
L3D_LEVEL:
|
||||
pm_v6d_l3_level: regulator-pm_v6d-l3-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6d_l3_level";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
VDD_LPI_MX_LEVEL:
|
||||
L3B_LEVEL:
|
||||
pmxr2230_l3_level: regulator-pmxr2230-l3-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmxr2230_l3_level";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
VDD_GFX_LEVEL:
|
||||
S1G_LEVEL:
|
||||
pm_v6g_s1_level: regulator-pm_v6g-s1-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6g_s1_level";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
S3G:
|
||||
pm_v6g_s3: regulator-pm_v6g-s3 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6g_s3";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1010000>;
|
||||
regulator-max-microvolt = <1170000>;
|
||||
};
|
||||
|
||||
L1G:
|
||||
pm_v6g_l1: regulator-pm_v6g-l1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6g_l1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <320000>;
|
||||
regulator-max-microvolt = <570000>;
|
||||
};
|
||||
|
||||
L2G:
|
||||
pm_v6g_l2: regulator-pm_v6g-l2 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6g_l2";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
L3G:
|
||||
pm_v6g_l3: regulator-pm_v6g-l3 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm_v6g_l3";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
};
|
||||
|
||||
S1I:
|
||||
pmg1110i_s1: regulator-pmg1110i-s1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmg1110i_s1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <320000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
|
||||
S1J:
|
||||
pmg1110j_s1: regulator-pmg1110j-s1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmg1110j_s1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <320000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
|
||||
L1K:
|
||||
pmr735b_l1: regulator-pmr735b-l1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmr735b_l1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <806000>;
|
||||
regulator-max-microvolt = <901000>;
|
||||
};
|
||||
|
||||
L2K:
|
||||
pmr735b_l2: regulator-pmr735b-l2 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmr735b_l2";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <920000>;
|
||||
regulator-max-microvolt = <969000>;
|
||||
};
|
||||
|
||||
L3K:
|
||||
pmr735b_l3: regulator-pmr735b-l3 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmr735b_l3";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1144000>;
|
||||
regulator-max-microvolt = <1224000>;
|
||||
};
|
||||
|
||||
L4K:
|
||||
pmr735b_l4: regulator-pmr735b-l4 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmr735b_l4";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1854000>;
|
||||
};
|
||||
|
||||
L5K:
|
||||
pmr735b_l5: regulator-pmr735b-l5 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmr735b_l5";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <866000>;
|
||||
regulator-max-microvolt = <931000>;
|
||||
};
|
||||
|
||||
L6K:
|
||||
pmr735b_l6: regulator-pmr735b-l6 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmr735b_l6";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
L7K:
|
||||
pmr735b_l7: regulator-pmr735b-l7 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pmr735b_l7";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <831000>;
|
||||
regulator-max-microvolt = <919000>;
|
||||
};
|
||||
|
||||
L1M:
|
||||
pm8010m_l1: regulator-pm8010m-l1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010m_l1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
L2M:
|
||||
pm8010m_l2: regulator-pm8010m-l2 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010m_l2";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
};
|
||||
|
||||
L3M:
|
||||
pm8010m_l3: regulator-pm8010m-l3 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010m_l3";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
L4M:
|
||||
pm8010m_l4: regulator-pm8010m-l4 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010m_l4";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
L5M:
|
||||
pm8010m_l5: regulator-pm8010m-l5 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010m_l5";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1504000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
L6M:
|
||||
pm8010m_l6: regulator-pm8010m-l6 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010m_l6";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
L7M:
|
||||
pm8010m_l7: regulator-pm8010m-l7 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010m_l7";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
L1N:
|
||||
pm8010n_l1: regulator-pm8010n-l1 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010n_l1";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
L2N:
|
||||
pm8010n_l2: regulator-pm8010n-l2 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010n_l2";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
};
|
||||
|
||||
L3N:
|
||||
pm8010n_l3: regulator-pm8010n-l3 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010n_l3";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1792000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
};
|
||||
|
||||
L4N:
|
||||
pm8010n_l4: regulator-pm8010n-l4 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010n_l4";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1792000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
};
|
||||
|
||||
L5N:
|
||||
pm8010n_l5: regulator-pm8010n-l5 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010n_l5";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <1504000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
};
|
||||
|
||||
L6N:
|
||||
pm8010n_l6: regulator-pm8010n-l6 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010n_l6";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
L7N:
|
||||
pm8010n_l7: regulator-pm8010n-l7 {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm8010n_l7";
|
||||
qcom,hpm-min-load = <10000>;
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
@@ -37,7 +37,7 @@
|
||||
reg = <0xa600000 0xd93c>;
|
||||
|
||||
iommus = <&apps_smmu 0x40 0x0>;
|
||||
qcom,iommu-dma = "bypass";
|
||||
qcom,iommu-dma = "atomic";
|
||||
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
||||
dma-coherent;
|
||||
|
||||
|
||||
@@ -30,7 +30,8 @@
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
|
||||
bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops";
|
||||
stdout-path = "/soc/qcom,qupv3_1_geni_se@8c0000/qcom,qup_uart@894000:115200n8";
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {};
|
||||
@@ -201,6 +202,10 @@
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
|
||||
hypervisor: hypervisor {
|
||||
gh_watchdog: qcom,gh-watchdog { };
|
||||
};
|
||||
};
|
||||
|
||||
&firmware {
|
||||
@@ -403,6 +408,7 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
wakeup-parent = <&pdc>;
|
||||
qcom,gpios-reserved = <20 21 22 23 100 111 112 116>;
|
||||
};
|
||||
|
||||
tcsr_mutex_block: syscon@1f40000 {
|
||||
@@ -900,8 +906,9 @@
|
||||
size = <0x0 0x4800000>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "kera-debug.dtsi"
|
||||
#include "kera-pinctrl.dtsi"
|
||||
#include "kera-stub-regulators.dtsi"
|
||||
#include "kera-usb.dtsi"
|
||||
#include "kera-qupv3.dtsi"
|
||||
|
||||
|
||||
@@ -44,6 +44,10 @@
|
||||
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
qcom,actlr =
|
||||
/* All CBs of GFX: +15 deep PF */
|
||||
<0x000 0x3ff 0x32B>;
|
||||
|
||||
gpu_qtb: gpu_qtb@03de8000 {
|
||||
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
||||
reg = <0x3de8000 0x1000>;
|
||||
@@ -179,6 +183,48 @@
|
||||
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
qcom,actlr =
|
||||
/* CAM_HF:Camera */
|
||||
<0x1c00 0x0000 0x00000001>,
|
||||
|
||||
/* Mnoc_HF_23:Display */
|
||||
<0x0800 0x0002 0x00000001>,
|
||||
<0x0801 0x0000 0x00000001>,
|
||||
|
||||
/* NSP:Compute */
|
||||
<0x0c01 0x0000 0x00000303>,
|
||||
<0x0c02 0x0000 0x00000303>,
|
||||
<0x0c03 0x0000 0x00000303>,
|
||||
<0x0c04 0x0000 0x00000303>,
|
||||
<0x0c05 0x0000 0x00000303>,
|
||||
<0x0c06 0x0000 0x00000303>,
|
||||
<0x0c07 0x0000 0x00000303>,
|
||||
<0x0c08 0x0000 0x00000303>,
|
||||
<0x0c09 0x0000 0x00000303>,
|
||||
<0x0c0c 0x0000 0x00000303>,
|
||||
<0x0c0d 0x0000 0x00000303>,
|
||||
<0x0c0e 0x0000 0x00000303>,
|
||||
|
||||
/* SF:Camera */
|
||||
<0x1800 0x00c0 0x00000001>,
|
||||
<0x1820 0x0000 0x00000001>,
|
||||
<0x1860 0x0000 0x00000103>,
|
||||
<0x18a0 0x0000 0x00000103>,
|
||||
<0x18e0 0x0000 0x00000103>,
|
||||
<0x1980 0x0000 0x00000001>,
|
||||
|
||||
/* SF:EVA */
|
||||
<0x1900 0x0020 0x00000103>,
|
||||
<0x1904 0x0020 0x00000103>,
|
||||
<0x1923 0x0000 0x00000103>,
|
||||
|
||||
/* SF:Video */
|
||||
<0x1940 0x0000 0x00000103>,
|
||||
<0x1941 0x0004 0x00000103>,
|
||||
<0x1943 0x0000 0x00000103>,
|
||||
<0x1944 0x0000 0x00000103>,
|
||||
<0x1947 0x0000 0x00000103>;
|
||||
|
||||
anoc_1_qtb: anoc_1_qtb@16f2000 {
|
||||
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
||||
reg = <0x16f2000 0x1000>;
|
||||
|
||||
@@ -23,10 +23,12 @@
|
||||
vdd-supply = <&gpu_cx_gdsc>;
|
||||
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu_clk";
|
||||
"gpu_cc_hlos1_vote_gpu_smmu_clk",
|
||||
"xo";
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
ranges;
|
||||
|
||||
@@ -76,6 +76,7 @@ _platform_map = {
|
||||
"tuna": {
|
||||
"dtb_list": [
|
||||
{"name": "tuna.dtb"},
|
||||
{"name": "tuna7.dtb"},
|
||||
],
|
||||
"dtbo_list": [
|
||||
{
|
||||
@@ -141,6 +142,7 @@ _platform_map = {
|
||||
{"name": "sunp-vm-hdk.dtb"},
|
||||
{"name": "sun-vm-rumi.dtb"},
|
||||
],
|
||||
"binary_compatible_with": ["tuna-tuivm"],
|
||||
},
|
||||
"sun-oemvm": {
|
||||
"dtb_list": [
|
||||
@@ -160,6 +162,53 @@ _platform_map = {
|
||||
{"name": "sunp-vm-hdk.dtb"},
|
||||
{"name": "sun-vm-rumi.dtb"},
|
||||
],
|
||||
"binary_compatible_with": ["tuna-oemvm"],
|
||||
},
|
||||
"tuna-tuivm": {
|
||||
"dtb_list": [
|
||||
# keep sorted
|
||||
{"name": "tuna-oemvm-atp.dtb"},
|
||||
{"name": "tuna-oemvm-cdp.dtb"},
|
||||
{"name": "tuna-oemvm-mtp.dtb"},
|
||||
{"name": "tuna-oemvm-mtp-kiwi.dtb"},
|
||||
{"name": "tuna-oemvm-mtp-qmp1000.dtb"},
|
||||
{"name": "tuna-oemvm-qrd.dtb"},
|
||||
{"name": "tuna-oemvm-rcm.dtb"},
|
||||
{"name": "tuna-oemvm-rcm-kiwi.dtb"},
|
||||
{"name": "tuna-oemvm-rumi.dtb"},
|
||||
{"name": "tuna-vm-atp.dtb"},
|
||||
{"name": "tuna-vm-cdp.dtb"},
|
||||
{"name": "tuna-vm-mtp.dtb"},
|
||||
{"name": "tuna-vm-mtp-kiwi.dtb"},
|
||||
{"name": "tuna-vm-mtp-qmp1000.dtb"},
|
||||
{"name": "tuna-vm-qrd.dtb"},
|
||||
{"name": "tuna-vm-rcm.dtb"},
|
||||
{"name": "tuna-vm-rcm-kiwi.dtb"},
|
||||
{"name": "tuna-vm-rumi.dtb"},
|
||||
],
|
||||
},
|
||||
"tuna-oemvm": {
|
||||
"dtb_list": [
|
||||
# keep sorted
|
||||
{"name": "tuna-oemvm-atp.dtb"},
|
||||
{"name": "tuna-oemvm-cdp.dtb"},
|
||||
{"name": "tuna-oemvm-mtp.dtb"},
|
||||
{"name": "tuna-oemvm-mtp-kiwi.dtb"},
|
||||
{"name": "tuna-oemvm-mtp-qmp1000.dtb"},
|
||||
{"name": "tuna-oemvm-qrd.dtb"},
|
||||
{"name": "tuna-oemvm-rcm.dtb"},
|
||||
{"name": "tuna-oemvm-rcm-kiwi.dtb"},
|
||||
{"name": "tuna-oemvm-rumi.dtb"},
|
||||
{"name": "tuna-vm-atp.dtb"},
|
||||
{"name": "tuna-vm-cdp.dtb"},
|
||||
{"name": "tuna-vm-mtp.dtb"},
|
||||
{"name": "tuna-vm-mtp-kiwi.dtb"},
|
||||
{"name": "tuna-vm-mtp-qmp1000.dtb"},
|
||||
{"name": "tuna-vm-qrd.dtb"},
|
||||
{"name": "tuna-vm-rcm.dtb"},
|
||||
{"name": "tuna-vm-rcm-kiwi.dtb"},
|
||||
{"name": "tuna-vm-rumi.dtb"},
|
||||
],
|
||||
},
|
||||
"pineapple": {
|
||||
"dtb_list": [
|
||||
|
||||
@@ -93,6 +93,7 @@
|
||||
<&qupv3_se2_tx>, <&qupv3_se2_default_rx>;
|
||||
pinctrl-3 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
|
||||
<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
|
||||
qcom,suspend-ignore-children;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -77,6 +77,7 @@
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
tx-fifo-resize;
|
||||
num-hc-interrupters = /bits/ 16 <3>;
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "super-speed";
|
||||
usb-role-switch;
|
||||
|
||||
@@ -1317,6 +1317,11 @@
|
||||
cap-based-alloc-and-pwr-collapse;
|
||||
};
|
||||
|
||||
qcom,sps {
|
||||
compatible = "qcom,msm-sps-4k";
|
||||
qcom,pipe-attr-ee;
|
||||
};
|
||||
|
||||
qcom,msm-imem@14680000 {
|
||||
compatible = "qcom,msm-imem";
|
||||
reg = <0x0 0x14680000 0x0 0x1000>;
|
||||
@@ -1659,6 +1664,49 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
modem_pas: remoteproc-mss@04080000 {
|
||||
compatible = "qcom,sdxpinn-modem-pas";
|
||||
reg = <0x0 0x4080000 0x0 0x10000>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
cx-supply = <&VDD_CX_LEVEL>;
|
||||
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
||||
mx-supply = <&VDD_MODEM_LEVEL>;
|
||||
mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
|
||||
reg-names = "cx", "mx";
|
||||
|
||||
qcom,signal-aop;
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
memory-region = <&mpssadsp_mem>,
|
||||
<&q6_mpss_dtb_mem>,
|
||||
<&system_cma>,
|
||||
<&dsm_partition_1_mem>,
|
||||
<&dsm_partition_2_mem>,
|
||||
<&qlink_logging_mem>;
|
||||
firmware-name = "modem.mdt", "modem_dtb.mdt";
|
||||
|
||||
/* Inputs from mss */
|
||||
interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 0 0>,
|
||||
<&modem_smp2p_in 2 0>,
|
||||
<&modem_smp2p_in 1 0>,
|
||||
<&modem_smp2p_in 3 0>,
|
||||
<&modem_smp2p_in 7 0>;
|
||||
|
||||
interrupt-names = "wdog",
|
||||
"fatal",
|
||||
"handover",
|
||||
"ready",
|
||||
"stop-ack",
|
||||
"shutdown-ack";
|
||||
|
||||
/* Outputs to mss */
|
||||
qcom,smem-states = <&modem_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
};
|
||||
};
|
||||
|
||||
&gcc {
|
||||
|
||||
@@ -1765,7 +1765,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1788,7 +1788,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1811,7 +1811,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1834,7 +1834,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1857,7 +1857,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1880,7 +1880,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1903,7 +1903,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1926,7 +1926,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1949,7 +1949,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1972,7 +1972,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -1995,7 +1995,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -2018,7 +2018,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
@@ -2055,7 +2055,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
@@ -2251,7 +2251,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2360,7 +2360,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2469,7 +2469,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2578,7 +2578,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2687,7 +2687,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2796,7 +2796,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2833,7 +2833,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2927,7 +2927,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2962,7 +2962,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -2999,7 +2999,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -3044,7 +3044,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD0>;
|
||||
|
||||
in-ports {
|
||||
@@ -3149,7 +3149,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD1>;
|
||||
|
||||
in-ports {
|
||||
@@ -3257,7 +3257,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD1>;
|
||||
|
||||
in-ports {
|
||||
@@ -3294,7 +3294,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD1>;
|
||||
|
||||
in-ports {
|
||||
@@ -3356,7 +3356,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD1>;
|
||||
|
||||
in-ports {
|
||||
@@ -3391,7 +3391,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD1>;
|
||||
|
||||
in-ports {
|
||||
@@ -3428,7 +3428,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD1>;
|
||||
|
||||
in-ports {
|
||||
@@ -3473,7 +3473,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
power-domains = <&CLUSTER_PD1>;
|
||||
|
||||
in-ports {
|
||||
@@ -3506,7 +3506,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
@@ -5627,7 +5627,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
};
|
||||
|
||||
cti@12195000 {
|
||||
@@ -5641,7 +5641,7 @@
|
||||
clocks = <&aoss_qmp>,
|
||||
<&scmi_clk 0>;
|
||||
clock-names = "apb_pclk",
|
||||
"dynamic_clk";
|
||||
"atclk";
|
||||
};
|
||||
|
||||
cti@10a05000 {
|
||||
|
||||
@@ -20,11 +20,11 @@
|
||||
dcc: dcc@100ff000 {
|
||||
compatible = "qcom,dcc-v2";
|
||||
reg = <0x100ff000 0x1000>,
|
||||
<0x10080800 0x7800>;
|
||||
<0x10084000 0x4000>;
|
||||
reg-names = "dcc-base", "dcc-ram-base";
|
||||
|
||||
qcom,transaction_timeout = <0x80>;
|
||||
dcc-ram-offset = <0x800>;
|
||||
dcc-ram-offset = <0x4000>;
|
||||
|
||||
link_list_0 {
|
||||
qcom,curr-link-list = <6>;
|
||||
@@ -1651,266 +1651,6 @@
|
||||
<DCC_READ 0x25C720B0 1 0>;
|
||||
};
|
||||
|
||||
link_list_1 {
|
||||
qcom,curr-link-list = <4>;
|
||||
qcom,data-sink = "sram";
|
||||
qcom,ap-qad-override;
|
||||
qcom,link-list = <DCC_READ 0x16801000 2 0>,
|
||||
<DCC_READ 0x240e0010 1 0>,
|
||||
<DCC_READ 0x240e0020 8 0>,
|
||||
<DCC_READ 0x240e0248 1 0>,
|
||||
<DCC_READ 0x24330010 1 0>,
|
||||
<DCC_READ 0x24330020 8 0>,
|
||||
<DCC_READ 0x24330248 1 0>,
|
||||
<DCC_READ 0x240e1018 1 0>,
|
||||
<DCC_READ 0x240e1008 1 0>,
|
||||
<DCC_LOOP 0x9 0 0>,
|
||||
<DCC_READ 0x240e1010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x24331018 1 0>,
|
||||
<DCC_READ 0x24331008 1 0>,
|
||||
<DCC_LOOP 0x8 0 0>,
|
||||
<DCC_READ 0x24331010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01780010 1 0>,
|
||||
<DCC_READ 0x01780020 8 0>,
|
||||
<DCC_READ 0x01780248 1 0>,
|
||||
<DCC_READ 0x01782018 1 0>,
|
||||
<DCC_READ 0x01782008 1 0>,
|
||||
<DCC_LOOP 0xc 0 0>,
|
||||
<DCC_READ 0x01782010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01783018 1 0>,
|
||||
<DCC_READ 0x01783008 1 0>,
|
||||
<DCC_LOOP 0x11 0 0>,
|
||||
<DCC_READ 0x01783010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01680010 1 0>,
|
||||
<DCC_READ 0x01680020 8 0>,
|
||||
<DCC_READ 0x01681048 1 0>,
|
||||
<DCC_READ 0x01682018 1 0>,
|
||||
<DCC_READ 0x01682008 1 0>,
|
||||
<DCC_LOOP 0x6 0 0>,
|
||||
<DCC_READ 0x01682010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x016e0010 1 0>,
|
||||
<DCC_READ 0x016e0020 8 0>,
|
||||
<DCC_READ 0x016e0248 1 0>,
|
||||
<DCC_READ 0x016e1018 1 0>,
|
||||
<DCC_READ 0x016e1008 1 0>,
|
||||
<DCC_LOOP 0x4 0 0>,
|
||||
<DCC_READ 0x016e1010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x016e1098 1 0>,
|
||||
<DCC_READ 0x016e1088 1 0>,
|
||||
<DCC_LOOP 0x3 0 0>,
|
||||
<DCC_READ 0x016e1090 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x016e1118 1 0>,
|
||||
<DCC_READ 0x016e1108 1 0>,
|
||||
<DCC_LOOP 0x7 0 0>,
|
||||
<DCC_READ 0x016e1110 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01700010 1 0>,
|
||||
<DCC_READ 0x01700020 8 0>,
|
||||
<DCC_READ 0x01700248 1 0>,
|
||||
<DCC_READ 0x1702018 1 0>,
|
||||
<DCC_READ 0x1702008 1 0>,
|
||||
<DCC_LOOP 0x4 0 0>,
|
||||
<DCC_READ 0x1702010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x1702218 1 0>,
|
||||
<DCC_READ 0x1702208 1 0>,
|
||||
<DCC_LOOP 0x2 0 0>,
|
||||
<DCC_READ 0x1702210 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x1702118 1 0>,
|
||||
<DCC_READ 0x1702108 1 0>,
|
||||
<DCC_LOOP 0x3 0 0>,
|
||||
<DCC_READ 0x1702110 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01600010 1 0>,
|
||||
<DCC_READ 0x01600020 8 0>,
|
||||
<DCC_READ 0x01600248 2 0>,
|
||||
<DCC_READ 0x01600258 1 0>,
|
||||
<DCC_READ 0x01602018 1 0>,
|
||||
<DCC_READ 0x01602008 1 0>,
|
||||
<DCC_LOOP 0x7 0 0>,
|
||||
<DCC_READ 0x01602010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01602098 1 0>,
|
||||
<DCC_READ 0x01602088 1 0>,
|
||||
<DCC_LOOP 0x2 0 0>,
|
||||
<DCC_READ 0x01602090 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01602118 1 0>,
|
||||
<DCC_READ 0x01602108 1 0>,
|
||||
<DCC_LOOP 0x3 0 0>,
|
||||
<DCC_READ 0x01602110 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01602198 1 0>,
|
||||
<DCC_READ 0x01602188 1 0>,
|
||||
<DCC_LOOP 0x3 0 0>,
|
||||
<DCC_READ 0x01602190 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01602218 1 0>,
|
||||
<DCC_READ 0x01602208 1 0>,
|
||||
<DCC_LOOP 0x2 0 0>,
|
||||
<DCC_READ 0x01602210 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x1602098 1 0>,
|
||||
<DCC_READ 0x1602088 1 0>,
|
||||
<DCC_LOOP 0x2 0 0>,
|
||||
<DCC_READ 0x1602090 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01500010 1 0>,
|
||||
<DCC_READ 0x01500020 8 0>,
|
||||
<DCC_READ 0x01500248 1 0>,
|
||||
<DCC_READ 0x01500448 1 0>,
|
||||
<DCC_READ 0x01502018 1 0>,
|
||||
<DCC_READ 0x01502008 1 0>,
|
||||
<DCC_LOOP 0x7 0 0>,
|
||||
<DCC_READ 0x01502010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x01502098 1 0>,
|
||||
<DCC_READ 0x01502088 1 0>,
|
||||
<DCC_LOOP 0x7 0 0>,
|
||||
<DCC_READ 0x01502090 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x16E00010 1 0>,
|
||||
<DCC_READ 0x16E00020 8 0>,
|
||||
<DCC_READ 0x16E00248 1 0>,
|
||||
<DCC_READ 0x16E01018 1 0>,
|
||||
<DCC_READ 0x16E01008 1 0>,
|
||||
<DCC_LOOP 0x6 0 0>,
|
||||
<DCC_READ 0x16E01010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x1B600010 1 0>,
|
||||
<DCC_READ 0x1B600020 8 0>,
|
||||
<DCC_READ 0x1B600248 1 0>,
|
||||
<DCC_READ 0x1B601018 1 0>,
|
||||
<DCC_READ 0x1B601008 1 0>,
|
||||
<DCC_LOOP 0x6 0 0>,
|
||||
<DCC_READ 0x1B601010 2 0>,
|
||||
<DCC_LOOP 0x1 0 0>,
|
||||
<DCC_READ 0x16000104 30 0>,
|
||||
<DCC_READ 0x16000204 29 0>,
|
||||
<DCC_READ 0x16000384 30 0>,
|
||||
<DCC_READ 0xB291024 1 0>,
|
||||
<DCC_READ 0xC201244 1 0>,
|
||||
<DCC_READ 0xC202244 1 0>,
|
||||
<DCC_READ 0xBDE1034 1 0>,
|
||||
<DCC_READ 0xBDE1038 1 0>,
|
||||
<DCC_READ 0xB201020 2 0>,
|
||||
<DCC_READ 0xB211020 2 0>,
|
||||
<DCC_READ 0xB221020 2 0>,
|
||||
<DCC_READ 0xB231020 2 0>,
|
||||
<DCC_READ 0xB204520 1 0>,
|
||||
<DCC_READ 0xB200000 1 0>,
|
||||
<DCC_READ 0xB210000 1 0>,
|
||||
<DCC_READ 0xB220000 1 0>,
|
||||
<DCC_READ 0xB230000 1 0>,
|
||||
<DCC_READ 0x16500010 1 0>,
|
||||
<DCC_READ 0x16510010 1 0>,
|
||||
<DCC_READ 0x16520010 1 0>,
|
||||
<DCC_READ 0x16530010 1 0>,
|
||||
<DCC_READ 0x16500030 1 0>,
|
||||
<DCC_READ 0x16510030 1 0>,
|
||||
<DCC_READ 0x16520030 1 0>,
|
||||
<DCC_READ 0x16530030 1 0>,
|
||||
<DCC_READ 0x16500038 1 0>,
|
||||
<DCC_READ 0x16510038 1 0>,
|
||||
<DCC_READ 0x16520038 1 0>,
|
||||
<DCC_READ 0x16530038 1 0>,
|
||||
<DCC_READ 0x16500040 1 0>,
|
||||
<DCC_READ 0x16510040 1 0>,
|
||||
<DCC_READ 0x16520040 1 0>,
|
||||
<DCC_READ 0x16530040 1 0>,
|
||||
<DCC_READ 0x16500048 1 0>,
|
||||
<DCC_READ 0x16500400 3 0>,
|
||||
<DCC_READ 0x16510400 3 0>,
|
||||
<DCC_READ 0x16520400 3 0>,
|
||||
<DCC_READ 0x16530400 3 0>,
|
||||
<DCC_READ 0x16510d3c 1 0>,
|
||||
<DCC_READ 0x16510d54 1 0>,
|
||||
<DCC_READ 0x16510d6c 1 0>,
|
||||
<DCC_READ 0x16510d84 1 0>,
|
||||
<DCC_READ 0x16510d9c 1 0>,
|
||||
<DCC_READ 0x16510db4 1 0>,
|
||||
<DCC_READ 0x16510dcc 1 0>,
|
||||
<DCC_READ 0x16510de4 1 0>,
|
||||
<DCC_READ 0x16510dfc 1 0>,
|
||||
<DCC_READ 0x16510e14 1 0>,
|
||||
<DCC_READ 0x16510e2c 1 0>,
|
||||
<DCC_READ 0x16510e44 1 0>,
|
||||
<DCC_READ 0x16510e5c 1 0>,
|
||||
<DCC_READ 0x16510e74 1 0>,
|
||||
<DCC_READ 0x16510e8c 1 0>,
|
||||
<DCC_READ 0x16510ea4 1 0>,
|
||||
<DCC_READ 0x16510fdc 1 0>,
|
||||
<DCC_READ 0x16510ff4 1 0>,
|
||||
<DCC_READ 0x1651100c 1 0>,
|
||||
<DCC_READ 0x16511024 1 0>,
|
||||
<DCC_READ 0x1651103c 1 0>,
|
||||
<DCC_READ 0x16511054 1 0>,
|
||||
<DCC_READ 0x1651106c 1 0>,
|
||||
<DCC_READ 0x16511084 1 0>,
|
||||
<DCC_READ 0x1651109c 1 0>,
|
||||
<DCC_READ 0x165110b4 1 0>,
|
||||
<DCC_READ 0x165110cc 1 0>,
|
||||
<DCC_READ 0x165110e4 1 0>,
|
||||
<DCC_READ 0x165110fc 1 0>,
|
||||
<DCC_READ 0x16511114 1 0>,
|
||||
<DCC_READ 0x1651112c 1 0>,
|
||||
<DCC_READ 0x16511144 1 0>,
|
||||
<DCC_READ 0x1651127c 1 0>,
|
||||
<DCC_READ 0x16511294 1 0>,
|
||||
<DCC_READ 0x165112ac 1 0>,
|
||||
<DCC_READ 0x165112c4 1 0>,
|
||||
<DCC_READ 0x165112dc 1 0>,
|
||||
<DCC_READ 0x165112f4 1 0>,
|
||||
<DCC_READ 0x1651130c 1 0>,
|
||||
<DCC_READ 0x16511324 1 0>,
|
||||
<DCC_READ 0x1651133c 1 0>,
|
||||
<DCC_READ 0x16511354 1 0>,
|
||||
<DCC_READ 0x1651136c 1 0>,
|
||||
<DCC_READ 0x16511384 1 0>,
|
||||
<DCC_READ 0x1651139c 1 0>,
|
||||
<DCC_READ 0x165113b4 1 0>,
|
||||
<DCC_READ 0x165113cc 1 0>,
|
||||
<DCC_READ 0x165113e4 1 0>,
|
||||
<DCC_READ 0x1651151c 1 0>,
|
||||
<DCC_READ 0x16511534 1 0>,
|
||||
<DCC_READ 0x1651154c 1 0>,
|
||||
<DCC_READ 0x16511564 1 0>,
|
||||
<DCC_READ 0x1651157c 1 0>,
|
||||
<DCC_READ 0x16511594 1 0>,
|
||||
<DCC_READ 0x165115ac 1 0>,
|
||||
<DCC_READ 0x165115c4 1 0>,
|
||||
<DCC_READ 0x165115dc 1 0>,
|
||||
<DCC_READ 0x165115f4 1 0>,
|
||||
<DCC_READ 0x1651160c 1 0>,
|
||||
<DCC_READ 0x16511624 1 0>,
|
||||
<DCC_READ 0x1651163c 1 0>,
|
||||
<DCC_READ 0x16511654 1 0>,
|
||||
<DCC_READ 0x1651166c 1 0>,
|
||||
<DCC_READ 0x16511684 1 0>,
|
||||
<DCC_READ 0x110004 2 0>,
|
||||
<DCC_READ 0x11003C 3 0>,
|
||||
<DCC_READ 0x176040 1 0>,
|
||||
<DCC_READ 0x10C0000 4 0>,
|
||||
<DCC_READ 0x10C1000 2 0>,
|
||||
<DCC_READ 0x10C1010 7 0>,
|
||||
<DCC_READ 0x10C1100 3 0>,
|
||||
<DCC_READ 0x10C1110 5 0>,
|
||||
<DCC_READ 0x10C1130 2 0>,
|
||||
<DCC_READ 0x10C113C 2 0>,
|
||||
<DCC_READ 0x10C1148 3 0>,
|
||||
<DCC_READ 0x10C1800 11 0>,
|
||||
<DCC_READ 0x10C2000 1 0>,
|
||||
<DCC_READ 0x10CF004 1 0>,
|
||||
<DCC_READ 0x16801000 2 0>;
|
||||
};
|
||||
};
|
||||
|
||||
mem_dump {
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
interrupt-parent = <&vgic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force";
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force rcupdate.rcu_expedited=1 rcu_nocbs=0-1";
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
||||
@@ -2,3 +2,84 @@
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "ok";
|
||||
qcom,touch-active = "st,fts";
|
||||
|
||||
st_fts@49 {
|
||||
compatible = "st,fts";
|
||||
reg = <0x49>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <176 0x2008>;
|
||||
vdd-supply = <&L1D>;
|
||||
avdd-supply = <&L22B>;
|
||||
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
|
||||
pinctrl-0 = <&ts_active>;
|
||||
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
|
||||
st,irq-gpio = <&tlmm 176 0x2008>;
|
||||
st,irq-flags = <8>;
|
||||
st,reset-gpio = <&tlmm 189 0x00>;
|
||||
st,regulator_dvdd = "vdd";
|
||||
st,regulator_avdd = "avdd";
|
||||
|
||||
st,touch-type = "primary";
|
||||
st,qts_en;
|
||||
qts,trusted-touch-mode = "vm_mode";
|
||||
qts,touch-environment = "pvm";
|
||||
qts,trusted-touch-type = "primary";
|
||||
qts,trusted-touch-spi-irq = <658>;
|
||||
qts,trusted-touch-io-bases = <0xa90000>;
|
||||
qts,trusted-touch-io-sizes = <0x1000>;
|
||||
qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0
|
||||
&tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>;
|
||||
};
|
||||
};
|
||||
|
||||
&ufsphy_mem {
|
||||
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
|
||||
|
||||
/* VDDA_UFS_CORE */
|
||||
vdda-phy-supply = <&L1F>;
|
||||
vdda-phy-max-microamp = <213100>;
|
||||
/*
|
||||
* Platforms supporting Gear 5 && Rate B require a different
|
||||
* voltage supply. Check the Power Grid document.
|
||||
*/
|
||||
vdda-phy-min-microvolt = <912000>;
|
||||
|
||||
/* VDDA_UFS_0_1P2 */
|
||||
vdda-pll-supply = <&L4B>;
|
||||
vdda-pll-max-microamp = <18340>;
|
||||
|
||||
/* Phy GDSC for VDD_MX, always on */
|
||||
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
|
||||
|
||||
/* Qref power supply, Refer Qref diagram */
|
||||
vdda-qref-supply = <&L2B>;
|
||||
vdda-qref-max-microamp = <64500>;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ufshc_mem {
|
||||
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
|
||||
|
||||
vcc-supply = <&L12B>;
|
||||
vcc-max-microamp = <1200000>;
|
||||
|
||||
vccq-supply = <&L3F>;
|
||||
vccq-max-microamp = <1200000>;
|
||||
|
||||
/* VDD_PX10 is voted for the ufs_reset_n */
|
||||
qcom,vddp-ref-clk-supply = <&L5B>;
|
||||
qcom,vddp-ref-clk-max-microamp = <100>;
|
||||
|
||||
qcom,vccq-parent-supply = <&S2B>;
|
||||
qcom,vccq-parent-max-microamp = <210000>;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
4833
qcom/tuna-coresight.dtsi
Normal file
4833
qcom/tuna-coresight.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
461
qcom/tuna-debug.dtsi
Normal file
461
qcom/tuna-debug.dtsi
Normal file
@@ -0,0 +1,461 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/soc/qcom,dcc_v2.h>
|
||||
|
||||
&reserved_memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
dump_mem: mem_dump_region {
|
||||
alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
|
||||
size = <0x0 0x1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
dcc: dcc_v2@100ff000 {
|
||||
compatible = "qcom,dcc-v2";
|
||||
reg = <0x100ff000 0x1000>,
|
||||
<0x10084000 0x4000>;
|
||||
|
||||
status = "disabled";
|
||||
qcom,transaction_timeout = <0>;
|
||||
|
||||
reg-names = "dcc-base", "dcc-ram-base";
|
||||
dcc-ram-offset = <0x4000>;
|
||||
};
|
||||
|
||||
mem_dump {
|
||||
compatible = "qcom,mem-dump";
|
||||
memory-region = <&dump_mem>;
|
||||
|
||||
static_dump {
|
||||
qcom,static-mem-dump;
|
||||
|
||||
c0_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x0>;
|
||||
};
|
||||
|
||||
c100_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x1>;
|
||||
};
|
||||
|
||||
c200_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x2>;
|
||||
};
|
||||
|
||||
c300_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x3>;
|
||||
};
|
||||
|
||||
c400_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x4>;
|
||||
};
|
||||
|
||||
c500_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x5>;
|
||||
};
|
||||
|
||||
c600_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x6>;
|
||||
};
|
||||
|
||||
c700_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x7>;
|
||||
};
|
||||
|
||||
l1_icache0 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x60>;
|
||||
};
|
||||
|
||||
l1_icache100 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x61>;
|
||||
};
|
||||
|
||||
l1_icache200 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x62>;
|
||||
};
|
||||
|
||||
l1_icache300 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x63>;
|
||||
};
|
||||
|
||||
l1_icache400 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x64>;
|
||||
};
|
||||
|
||||
l1_icache500 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x65>;
|
||||
};
|
||||
|
||||
l1_icache600 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x66>;
|
||||
};
|
||||
|
||||
l1_icache700 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x67>;
|
||||
};
|
||||
|
||||
l1_dcache0 {
|
||||
qcom,dump-size = <0x12100>;
|
||||
qcom,dump-id = <0x80>;
|
||||
};
|
||||
|
||||
l1_dcache100 {
|
||||
qcom,dump-size = <0x12100>;
|
||||
qcom,dump-id = <0x81>;
|
||||
};
|
||||
|
||||
l1_dcache200 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x82>;
|
||||
};
|
||||
|
||||
l1_dcache300 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x83>;
|
||||
};
|
||||
|
||||
l1_dcache400 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x84>;
|
||||
};
|
||||
|
||||
l1_dcache500 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x85>;
|
||||
};
|
||||
|
||||
l1_dcache600 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x86>;
|
||||
};
|
||||
|
||||
l1_dcache700 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x87>;
|
||||
};
|
||||
|
||||
l1_itlb700 {
|
||||
qcom,dump-size = <0x600>;
|
||||
qcom,dump-id = <0x27>;
|
||||
};
|
||||
|
||||
l1_dtlb700 {
|
||||
qcom,dump-size = <0xa00>;
|
||||
qcom,dump-id = <0x47>;
|
||||
};
|
||||
|
||||
l2_cache0 {
|
||||
qcom,dump-size = <0x90100>;
|
||||
qcom,dump-id = <0xc0>;
|
||||
};
|
||||
|
||||
l2_cache100 {
|
||||
qcom,dump-size = <0x90100>;
|
||||
qcom,dump-id = <0xc1>;
|
||||
};
|
||||
|
||||
l2_cache200 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc2>;
|
||||
};
|
||||
|
||||
l2_cache300 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc3>;
|
||||
};
|
||||
|
||||
l2_cache400 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc4>;
|
||||
};
|
||||
|
||||
l2_cache500 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc5>;
|
||||
};
|
||||
|
||||
l2_cache600 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc6>;
|
||||
};
|
||||
|
||||
l2_cache700 {
|
||||
qcom,dump-size = <0x340100>;
|
||||
qcom,dump-id = <0xc7>;
|
||||
};
|
||||
|
||||
l2_tlb0 {
|
||||
qcom,dump-size = <0xf700>;
|
||||
qcom,dump-id = <0x120>;
|
||||
};
|
||||
|
||||
l2_tlb100 {
|
||||
qcom,dump-size = <0xf700>;
|
||||
qcom,dump-id = <0x121>;
|
||||
};
|
||||
|
||||
l2_tlb700 {
|
||||
qcom,dump-size = <0xa900>;
|
||||
qcom,dump-id = <0x127>;
|
||||
};
|
||||
|
||||
l1dcdirty0 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x170>;
|
||||
};
|
||||
|
||||
l1dcdirty100 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x171>;
|
||||
};
|
||||
|
||||
l1dcmte0 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x180>;
|
||||
};
|
||||
|
||||
l1dcmte100 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x181>;
|
||||
};
|
||||
|
||||
l2dcmte0 {
|
||||
qcom,dump-size = <0x10100>;
|
||||
qcom,dump-id = <0x190>;
|
||||
};
|
||||
|
||||
l2dcmte100 {
|
||||
qcom,dump-size = <0x10100>;
|
||||
qcom,dump-id = <0x191>;
|
||||
};
|
||||
|
||||
l0mopca700 {
|
||||
qcom,dump-size = <0x4100>;
|
||||
qcom,dump-id = <0x1a7>;
|
||||
};
|
||||
|
||||
l2victim700 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x1e7>;
|
||||
};
|
||||
|
||||
l2tldtcsp200 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x202>;
|
||||
};
|
||||
|
||||
l2tldtcsp300 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x203>;
|
||||
};
|
||||
|
||||
l2tldtcsp400 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x204>;
|
||||
};
|
||||
|
||||
l2tldtcsp500 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x205>;
|
||||
};
|
||||
|
||||
l2tldtcsp600 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x206>;
|
||||
};
|
||||
|
||||
l2tldtcmp200 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x212>;
|
||||
};
|
||||
|
||||
l2tldtcmp300 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x213>;
|
||||
};
|
||||
|
||||
l2tldtcmp400 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x214>;
|
||||
};
|
||||
|
||||
l2tldtcmp500 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x215>;
|
||||
};
|
||||
|
||||
l2tldtcmp600 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x216>;
|
||||
};
|
||||
|
||||
rpmh {
|
||||
qcom,dump-size = <0x400000>;
|
||||
qcom,dump-id = <0xec>;
|
||||
};
|
||||
|
||||
rpm_sw {
|
||||
qcom,dump-size = <0x28000>;
|
||||
qcom,dump-id = <0xea>;
|
||||
};
|
||||
|
||||
pmic {
|
||||
qcom,dump-size = <0x200000>;
|
||||
qcom,dump-id = <0xe4>;
|
||||
};
|
||||
|
||||
fcm {
|
||||
qcom,dump-size = <0x8400>;
|
||||
qcom,dump-id = <0xee>;
|
||||
};
|
||||
|
||||
etf_swao {
|
||||
qcom,dump-size = <0x10000>;
|
||||
qcom,dump-id = <0xf1>;
|
||||
};
|
||||
|
||||
etr_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x100>;
|
||||
};
|
||||
|
||||
etfswao_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x102>;
|
||||
};
|
||||
|
||||
etr1_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x105>;
|
||||
};
|
||||
|
||||
misc_data {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0xe8>;
|
||||
};
|
||||
|
||||
etf_slpi {
|
||||
qcom,dump-size = <0x4000>;
|
||||
qcom,dump-id = <0xf3>;
|
||||
};
|
||||
|
||||
etfslpi_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x103>;
|
||||
};
|
||||
|
||||
etf_lpass {
|
||||
qcom,dump-size = <0x4000>;
|
||||
qcom,dump-id = <0xf4>;
|
||||
};
|
||||
|
||||
etflpass_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x104>;
|
||||
};
|
||||
|
||||
osm_reg {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x163>;
|
||||
};
|
||||
|
||||
pcu_reg {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x164>;
|
||||
};
|
||||
|
||||
fsm_data {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x165>;
|
||||
};
|
||||
|
||||
scandump_smmu {
|
||||
qcom,dump-size = <0x40000>;
|
||||
qcom,dump-id = <0x220>;
|
||||
};
|
||||
};
|
||||
|
||||
dynamic_mem_dump {
|
||||
qcom,dynamic-mem-dump;
|
||||
|
||||
scandump_gpu {
|
||||
scandump_gpu {
|
||||
qcom,dump-size = <0x300000>;
|
||||
qcom,dump-id = <0x221>;
|
||||
};
|
||||
};
|
||||
|
||||
cpuss_reg {
|
||||
cpuss_reg {
|
||||
qcom,dump-size = <0x36000>;
|
||||
qcom,dump-id = <0xef>;
|
||||
};
|
||||
};
|
||||
|
||||
spr {
|
||||
spr_cpu0 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f0>;
|
||||
};
|
||||
|
||||
spr_cpu1 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f1>;
|
||||
};
|
||||
|
||||
spr_cpu2 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f2>;
|
||||
};
|
||||
|
||||
spr_cpu3 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f3>;
|
||||
};
|
||||
|
||||
spr_cpu4 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f4>;
|
||||
};
|
||||
|
||||
spr_cpu5 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f5>;
|
||||
};
|
||||
|
||||
spr_cpu6 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f6>;
|
||||
};
|
||||
|
||||
spr_cpu7 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -2,3 +2,83 @@
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
&qupv3_se4_i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "ok";
|
||||
qcom,touch-active = "st,fts";
|
||||
|
||||
st_fts@49 {
|
||||
compatible = "st,fts";
|
||||
reg = <0x49>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <176 0x2008>;
|
||||
vdd-supply = <&L1D>;
|
||||
avdd-supply = <&L22B>;
|
||||
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
|
||||
pinctrl-0 = <&ts_active>;
|
||||
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
|
||||
st,irq-gpio = <&tlmm 176 0x2008>;
|
||||
st,irq-flags = <8>;
|
||||
st,reset-gpio = <&tlmm 189 0x00>;
|
||||
st,regulator_dvdd = "vdd";
|
||||
st,regulator_avdd = "avdd";
|
||||
|
||||
st,touch-type = "primary";
|
||||
st,qts_en;
|
||||
qts,trusted-touch-mode = "vm_mode";
|
||||
qts,touch-environment = "pvm";
|
||||
qts,trusted-touch-type = "primary";
|
||||
qts,trusted-touch-spi-irq = <658>;
|
||||
qts,trusted-touch-io-bases = <0xa90000>;
|
||||
qts,trusted-touch-io-sizes = <0x1000>;
|
||||
qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0
|
||||
&tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>;
|
||||
};
|
||||
};
|
||||
|
||||
&ufsphy_mem {
|
||||
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
|
||||
|
||||
/* VDDA_UFS_CORE */
|
||||
vdda-phy-supply = <&L1F>;
|
||||
vdda-phy-max-microamp = <213100>;
|
||||
/*
|
||||
* Platforms supporting Gear 5 && Rate B require a different
|
||||
* voltage supply. Check the Power Grid document.
|
||||
*/
|
||||
vdda-phy-min-microvolt = <912000>;
|
||||
|
||||
/* VDDA_UFS_0_1P2 */
|
||||
vdda-pll-supply = <&L4B>;
|
||||
vdda-pll-max-microamp = <18340>;
|
||||
|
||||
/* Phy GDSC for VDD_MX, always on */
|
||||
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
|
||||
|
||||
/* Qref power supply, Refer Qref diagram */
|
||||
vdda-qref-supply = <&L2B>;
|
||||
vdda-qref-max-microamp = <64500>;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ufshc_mem {
|
||||
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
|
||||
|
||||
vcc-supply = <&L12B>;
|
||||
vcc-max-microamp = <1200000>;
|
||||
|
||||
vccq-supply = <&L3F>;
|
||||
vccq-max-microamp = <1200000>;
|
||||
|
||||
/* VDD_PX10 is voted for the ufs_reset_n */
|
||||
qcom,vddp-ref-clk-supply = <&L5B>;
|
||||
qcom,vddp-ref-clk-max-microamp = <100>;
|
||||
|
||||
qcom,vccq-parent-supply = <&S2B>;
|
||||
qcom,vccq-parent-max-microamp = <210000>;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
17
qcom/tuna-oemvm-atp.dts
Normal file
17
qcom/tuna-oemvm-atp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-atp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM ATP";
|
||||
compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap",
|
||||
"qcom,atp";
|
||||
|
||||
qcom,board-id = <33 0>;
|
||||
};
|
||||
7
qcom/tuna-oemvm-atp.dtsi
Normal file
7
qcom/tuna-oemvm-atp.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
17
qcom/tuna-oemvm-cdp.dts
Normal file
17
qcom/tuna-oemvm-cdp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM CDP";
|
||||
compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap",
|
||||
"qcom,cdp";
|
||||
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
7
qcom/tuna-oemvm-cdp.dtsi
Normal file
7
qcom/tuna-oemvm-cdp.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-oemvm-mtp-kiwi.dts
Normal file
16
qcom/tuna-oemvm-mtp-kiwi.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-mtp-kiwi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM MTP + kiwi WLAN";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,board-id = <8 2>;
|
||||
};
|
||||
7
qcom/tuna-oemvm-mtp-kiwi.dtsi
Normal file
7
qcom/tuna-oemvm-mtp-kiwi.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-oemvm-mtp-qmp1000.dts
Normal file
16
qcom/tuna-oemvm-mtp-qmp1000.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-mtp-qmp1000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM MTP QMP1000";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,board-id = <8 1>;
|
||||
};
|
||||
7
qcom/tuna-oemvm-mtp-qmp1000.dtsi
Normal file
7
qcom/tuna-oemvm-mtp-qmp1000.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-oemvm-mtp.dts
Normal file
16
qcom/tuna-oemvm-mtp.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM MTP";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
7
qcom/tuna-oemvm-mtp.dtsi
Normal file
7
qcom/tuna-oemvm-mtp.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-oemvm-qrd.dts
Normal file
16
qcom/tuna-oemvm-qrd.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM QRD";
|
||||
compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap",
|
||||
"qcom,qrd";
|
||||
qcom,board-id = <11 0>;
|
||||
};
|
||||
7
qcom/tuna-oemvm-qrd.dtsi
Normal file
7
qcom/tuna-oemvm-qrd.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-oemvm-rcm-kiwi.dts
Normal file
16
qcom/tuna-oemvm-rcm-kiwi.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-rcm-kiwi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM RCM + kiwi WLAN";
|
||||
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
|
||||
"qcom,rcm";
|
||||
qcom,board-id = <21 1>;
|
||||
};
|
||||
7
qcom/tuna-oemvm-rcm-kiwi.dtsi
Normal file
7
qcom/tuna-oemvm-rcm-kiwi.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-oemvm-rcm.dts
Normal file
16
qcom/tuna-oemvm-rcm.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-rcm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM RCM";
|
||||
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
|
||||
"qcom,rcm";
|
||||
qcom,board-id = <21 0>;
|
||||
};
|
||||
7
qcom/tuna-oemvm-rcm.dtsi
Normal file
7
qcom/tuna-oemvm-rcm.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
15
qcom/tuna-oemvm-rumi.dts
Normal file
15
qcom/tuna-oemvm-rumi.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-oemvm.dtsi"
|
||||
#include "tuna-oemvm-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna OEMVM RUMI";
|
||||
compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi";
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
8
qcom/tuna-oemvm-rumi.dtsi
Normal file
8
qcom/tuna-oemvm-rumi.dtsi
Normal file
@@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&arch_timer {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
218
qcom/tuna-oemvm.dtsi
Normal file
218
qcom/tuna-oemvm.dtsi
Normal file
@@ -0,0 +1,218 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
qcom,msm-id = <655 0x10000>;
|
||||
interrupt-parent = <&vgic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,vm-config {
|
||||
compatible = "qcom,vm-1.0";
|
||||
vm-type = "aarch64-guest";
|
||||
boot-config = "fdt,unified";
|
||||
os-type = "linux";
|
||||
kernel-entry-segment = "kernel";
|
||||
kernel-entry-offset = <0x0 0x0>;
|
||||
vendor = "QTI";
|
||||
image-name = "qcom,oemvm";
|
||||
qcom,pasid = <0x0 0x22>;
|
||||
qcom,qtee-config-info = "p=3,9,39,7C,8F,97,159,7F1,CDF;";
|
||||
qcom,secdomain-ids = <49>;
|
||||
qcom,primary-vm-index = <0>;
|
||||
vm-uri = "vmuid/oemvm";
|
||||
vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0";
|
||||
qcom,sensitive;
|
||||
|
||||
vm-attrs = "context-dump", "crash-restart";
|
||||
|
||||
memory {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
/*
|
||||
* IPA address linux image is loaded at. Must be within
|
||||
* first 1GB due to memory hotplug requirement.
|
||||
*/
|
||||
base-address = <0x0 0x88800000 >;
|
||||
};
|
||||
|
||||
segments {
|
||||
config_cpio = <2>;
|
||||
};
|
||||
|
||||
vcpus {
|
||||
config = "/cpus";
|
||||
affinity = "proxy";
|
||||
affinity-map = <0x5 0x6>;
|
||||
sched-priority = <0>; /* relative to PVM */
|
||||
sched-timeslice = <2000>; /* in ms */
|
||||
};
|
||||
|
||||
interrupts {
|
||||
config = &vgic;
|
||||
};
|
||||
|
||||
vdevices {
|
||||
generate = "/hypervisor";
|
||||
|
||||
minidump {
|
||||
vdevice-type = "minidump";
|
||||
push-compatible = "qcom,minidump_rm";
|
||||
minidump_allowed;
|
||||
};
|
||||
|
||||
rm-rpc {
|
||||
vdevice-type = "rm-rpc";
|
||||
generate = "/hypervisor/qcom,resource-mgr";
|
||||
console-dev;
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
qcom,label = <0x1>;
|
||||
};
|
||||
|
||||
virtio-mmio@0 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x1>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x0>;
|
||||
memory {
|
||||
qcom,label = <0x16>; //for persist.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xFFEFC000>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@1 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x2>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x4000>;
|
||||
memory {
|
||||
qcom,label = <0x13>; //for system.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xFFF00000>;
|
||||
};
|
||||
};
|
||||
|
||||
swiotlb-shm {
|
||||
vdevice-type = "shm";
|
||||
generate = "/swiotlb";
|
||||
push-compatible = "swiotlb";
|
||||
peer-default;
|
||||
dma_base = <0x0 0x8000>;
|
||||
memory {
|
||||
qcom,label = <0x14>;
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xFFF04000>;
|
||||
};
|
||||
};
|
||||
|
||||
vrtc {
|
||||
vdevice-type = "vrtc-pl031";
|
||||
peer-default;
|
||||
allocate-base;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
firmware: firmware {
|
||||
qcom_scm: scm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
vgic: interrupt-controller@17100000 {
|
||||
compatible = "arm,gic-v3";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x40000>;
|
||||
reg = <0x17100000 0x10000>, /* GICD */
|
||||
<0x17180000 0x200000>; /* GICR * 8 */
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
always-on;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
qcom_smcinvoke {
|
||||
compatible = "qcom,smcinvoke";
|
||||
};
|
||||
|
||||
qtee_shmbridge {
|
||||
compatible = "qcom,tee-shared-memory-bridge";
|
||||
qcom,custom-bridge-size = <512>;
|
||||
qcom,support-hypervisor;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -2,3 +2,87 @@
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&qupv3_se4_spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "ok";
|
||||
qcom,touch-active = "st,fts";
|
||||
qcom,la-vm;
|
||||
|
||||
st_fts@0 {
|
||||
compatible = "st,fts";
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <176 0x2008>;
|
||||
vdd-supply = <&L1D>;
|
||||
avdd-supply = <&L22B>;
|
||||
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
|
||||
pinctrl-0 = <&ts_active>;
|
||||
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
|
||||
st,irq-gpio = <&tlmm 176 0x2008>;
|
||||
st,irq-flags = <8>;
|
||||
st,reset-gpio = <&tlmm 189 0x00>;
|
||||
st,regulator_dvdd = "vdd";
|
||||
st,regulator_avdd = "avdd";
|
||||
|
||||
st,touch-type = "primary";
|
||||
st,qts_en;
|
||||
qts,trusted-touch-mode = "vm_mode";
|
||||
qts,touch-environment = "pvm";
|
||||
qts,trusted-touch-type = "primary";
|
||||
qts,trusted-touch-spi-irq = <658>;
|
||||
qts,trusted-touch-io-bases = <0xa90000>;
|
||||
qts,trusted-touch-io-sizes = <0x1000>;
|
||||
qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0
|
||||
&tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
&ufsphy_mem {
|
||||
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
|
||||
|
||||
/* VDDA_UFS_CORE */
|
||||
vdda-phy-supply = <&L1F>;
|
||||
vdda-phy-max-microamp = <213100>;
|
||||
/*
|
||||
* Platforms supporting Gear 5 && Rate B require a different
|
||||
* voltage supply. Check the Power Grid document.
|
||||
*/
|
||||
vdda-phy-min-microvolt = <912000>;
|
||||
|
||||
/* VDDA_UFS_0_1P2 */
|
||||
vdda-pll-supply = <&L4B>;
|
||||
vdda-pll-max-microamp = <18340>;
|
||||
|
||||
/* Phy GDSC for VDD_MX, always on */
|
||||
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
|
||||
|
||||
/* Qref power supply, Refer Qref diagram */
|
||||
vdda-qref-supply = <&L2B>;
|
||||
vdda-qref-max-microamp = <64500>;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ufshc_mem {
|
||||
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
|
||||
|
||||
vcc-supply = <&L12B>;
|
||||
vcc-max-microamp = <1200000>;
|
||||
|
||||
vccq-supply = <&L3F>;
|
||||
vccq-max-microamp = <1200000>;
|
||||
|
||||
/* VDD_PX10 is voted for the ufs_reset_n */
|
||||
qcom,vddp-ref-clk-supply = <&L5B>;
|
||||
qcom,vddp-ref-clk-max-microamp = <100>;
|
||||
|
||||
qcom,vccq-parent-supply = <&S2B>;
|
||||
qcom,vccq-parent-max-microamp = <210000>;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
@@ -4,7 +4,62 @@
|
||||
*/
|
||||
|
||||
&soc {
|
||||
/* QUPv3_1 Wrapper Instance */
|
||||
/* QUPv3 SE Instances
|
||||
* Qup1 0: SE 0
|
||||
* Qup1 1: SE 1
|
||||
* Qup1 2: SE 2
|
||||
* Qup1 3: SE 3
|
||||
* Qup1 4: SE 4
|
||||
* Qup1 5: SE 5
|
||||
* Qup1 6: SE 6
|
||||
* Qup1 7: SE 7
|
||||
* Qup2 0: SE 8
|
||||
* Qup2 1: SE 9
|
||||
* Qup2 2: SE 10
|
||||
* Qup2 3: SE 11
|
||||
* Qup2 4: SE 12
|
||||
* Qup2 5: SE 13
|
||||
* Qup2 6: SE 14
|
||||
* Qup2 7: SE 15
|
||||
*/
|
||||
|
||||
qup1_gpi_iommu_region: qup1_gpi_iommu_region {
|
||||
iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>;
|
||||
};
|
||||
|
||||
/* GPI Instance */
|
||||
gpi_dma1: qcom,gpi-dma@a00000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0xa00000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0xb6 0x0>;
|
||||
qcom,max-num-gpii = <12>;
|
||||
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0x1f>;
|
||||
qcom,ev-factor = <1>;
|
||||
memory-region = <&qup1_gpi_iommu_region>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
qup1_se_iommu_region: qup1_se_iommu_region {
|
||||
iommu-addresses = <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>;
|
||||
};
|
||||
|
||||
/* QUPv3_1 wrapper instance */
|
||||
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0xac0000 0x2000>;
|
||||
@@ -13,9 +68,319 @@
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0xa3 0x0>;
|
||||
memory-region = <&qup1_se_iommu_region>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
dma-coherent;
|
||||
ranges;
|
||||
status = "ok";
|
||||
|
||||
qupv3_se0_i2c: i2c@a80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 0 3 64 0>,
|
||||
<&gpi_dma1 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_spi: spi@a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
|
||||
<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se0_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 0 1 64 0>,
|
||||
<&gpi_dma1 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_i2c: i2c@a84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 1 3 64 0>,
|
||||
<&gpi_dma1 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_spi: spi@a84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
|
||||
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se1_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 1 1 64 0>,
|
||||
<&gpi_dma1 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_i2c: i2c@a88000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 2 3 64 0>,
|
||||
<&gpi_dma1 1 2 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_spi: spi@a88000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
|
||||
<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se2_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 2 1 64 0>,
|
||||
<&gpi_dma1 1 2 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se3_i2c: i2c@a8c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 3 3 64 0>,
|
||||
<&gpi_dma1 1 3 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se4_i2c: i2c@a90000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 3 64 0>,
|
||||
<&gpi_dma1 1 4 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se4_spi: spi@a90000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
|
||||
<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se4_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 1 64 0>,
|
||||
<&gpi_dma1 1 4 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_i2c: i2c@a94000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa94000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 5 3 1024 0>,
|
||||
<&gpi_dma1 1 5 3 1024 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,shared;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_spi: spi@a94000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa94000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
|
||||
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 5 1 64 0>,
|
||||
<&gpi_dma1 1 5 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_i2c: i2c@a98000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa98000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 6 3 64 0>,
|
||||
<&gpi_dma1 1 6 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_spi: spi@a98000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa98000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
|
||||
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 6 1 64 0>,
|
||||
<&gpi_dma1 1 6 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Debug UART Instance */
|
||||
qupv3_se7_2uart: qcom,qup_uart@a9c000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
@@ -30,4 +395,389 @@
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
qup2_gpi_iommu_region: qup2_gpi_iommu_region {
|
||||
iommu-addresses = <&gpi_dma2 0x0 0x100000>, <&gpi_dma2 0x200000 0xffe00000>;
|
||||
};
|
||||
|
||||
/* GPI Instance */
|
||||
gpi_dma2: qcom,gpi-dma@800000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0x800000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0x436 0x0>;
|
||||
qcom,max-num-gpii = <12>;
|
||||
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0x1f>;
|
||||
qcom,ev-factor = <1>;
|
||||
memory-region = <&qup2_gpi_iommu_region>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
qup2_se_iommu_region: qup2_se_iommu_region {
|
||||
iommu-addresses = <&qupv3_2 0x0 0x40000000>, <&qupv3_2 0x50000000 0xb0000000>;
|
||||
};
|
||||
|
||||
/* QUPv3_2 wrapper instance */
|
||||
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x8c0000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x423 0x0>;
|
||||
memory-region = <&qup2_se_iommu_region>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
dma-coherent;
|
||||
ranges;
|
||||
status = "ok";
|
||||
|
||||
qupv3_se8_i2c: i2c@880000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x880000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
||||
dmas = <&gpi_dma2 0 0 3 64 0>,
|
||||
<&gpi_dma2 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se8_spi: spi@880000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x880000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
|
||||
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se8_spi_sleep>;
|
||||
dmas = <&gpi_dma2 0 0 1 64 0>,
|
||||
<&gpi_dma2 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_i2c: i2c@884000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x884000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
||||
dmas = <&gpi_dma2 0 1 3 64 0>,
|
||||
<&gpi_dma2 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se10_i2c: i2c@888000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x888000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
|
||||
dmas = <&gpi_dma2 0 2 3 64 0>,
|
||||
<&gpi_dma2 1 2 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se10_spi: spi@888000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x888000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>,
|
||||
<&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se10_spi_sleep>;
|
||||
dmas = <&gpi_dma2 0 2 1 64 0>,
|
||||
<&gpi_dma2 1 2 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se11_i2c: i2c@88c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x88c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
|
||||
dmas = <&gpi_dma2 0 3 3 64 0>,
|
||||
<&gpi_dma2 1 3 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se11_spi: spi@88c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x88c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>,
|
||||
<&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se11_spi_sleep>;
|
||||
dmas = <&gpi_dma2 0 3 1 64 0>,
|
||||
<&gpi_dma2 1 3 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se12_i2c: i2c@890000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x890000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
|
||||
dmas = <&gpi_dma2 0 4 3 64 0>,
|
||||
<&gpi_dma2 1 4 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se12_spi: spi@890000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x890000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>,
|
||||
<&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se12_spi_sleep>;
|
||||
dmas = <&gpi_dma2 0 4 1 64 0>,
|
||||
<&gpi_dma2 1 4 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se13_i2c: i2c@894000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x894000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se13_i2c_sda_active>, <&qupv3_se13_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se13_i2c_sleep>;
|
||||
dmas = <&gpi_dma2 0 5 3 64 0>,
|
||||
<&gpi_dma2 1 5 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se13_spi: spi@894000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x894000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se13_spi_mosi_active>, <&qupv3_se13_spi_miso_active>,
|
||||
<&qupv3_se13_spi_clk_active>, <&qupv3_se13_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se13_spi_sleep>;
|
||||
dmas = <&gpi_dma2 0 5 1 64 0>,
|
||||
<&gpi_dma2 1 5 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* HS UART Instance */
|
||||
qupv3_se14_4uart: qcom,qup_uart@898000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0x898000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts-extended = <&intc GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "active", "sleep", "shutdown";
|
||||
pinctrl-0 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
|
||||
<&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
|
||||
pinctrl-1 = <&qupv3_se14_cts>, <&qupv3_se14_rts>,
|
||||
<&qupv3_se14_tx>, <&qupv3_se14_rx_active>;
|
||||
pinctrl-2 = <&qupv3_se14_cts>, <&qupv3_se14_rts>,
|
||||
<&qupv3_se14_tx>, <&qupv3_se14_rx_wake>;
|
||||
pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
|
||||
<&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
qcom,suspend-ignore-children;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se15_i2c: i2c@89c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x89c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
|
||||
dmas = <&gpi_dma2 0 7 3 64 0>,
|
||||
<&gpi_dma2 1 7 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se15_spi: spi@89c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x89c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
|
||||
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>,
|
||||
<&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se15_spi_sleep>;
|
||||
dmas = <&gpi_dma2 0 7 1 64 0>,
|
||||
<&gpi_dma2 1 7 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -65,6 +65,11 @@
|
||||
reg = <0x0 0x81ce4000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
chipinfo_mem: chipinfo_region@81cf4000 {
|
||||
no-map;
|
||||
reg = <0x0 0x81cf4000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
smem_mem: smem_region@81d00000 {
|
||||
compatible = "qcom,smem";
|
||||
reg = <0x0 0x81d00000 0x0 0x200000>;
|
||||
|
||||
17
qcom/tuna-vm-atp.dts
Normal file
17
qcom/tuna-vm-atp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-atp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM ATP";
|
||||
compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap",
|
||||
"qcom,atp";
|
||||
|
||||
qcom,board-id = <33 0>;
|
||||
};
|
||||
7
qcom/tuna-vm-atp.dtsi
Normal file
7
qcom/tuna-vm-atp.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
17
qcom/tuna-vm-cdp.dts
Normal file
17
qcom/tuna-vm-cdp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM CDP";
|
||||
compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap",
|
||||
"qcom,cdp";
|
||||
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
7
qcom/tuna-vm-cdp.dtsi
Normal file
7
qcom/tuna-vm-cdp.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-vm-mtp-kiwi.dts
Normal file
16
qcom/tuna-vm-mtp-kiwi.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-mtp-kiwi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,board-id = <8 2>;
|
||||
};
|
||||
7
qcom/tuna-vm-mtp-kiwi.dtsi
Normal file
7
qcom/tuna-vm-mtp-kiwi.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-vm-mtp-qmp1000.dts
Normal file
16
qcom/tuna-vm-mtp-qmp1000.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-mtp-qmp1000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM MTP QMP1000";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,board-id = <8 1>;
|
||||
};
|
||||
7
qcom/tuna-vm-mtp-qmp1000.dtsi
Normal file
7
qcom/tuna-vm-mtp-qmp1000.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-vm-mtp.dts
Normal file
16
qcom/tuna-vm-mtp.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM MTP";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
7
qcom/tuna-vm-mtp.dtsi
Normal file
7
qcom/tuna-vm-mtp.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-vm-qrd.dts
Normal file
16
qcom/tuna-vm-qrd.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM QRD";
|
||||
compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap",
|
||||
"qcom,qrd";
|
||||
qcom,board-id = <11 0>;
|
||||
};
|
||||
7
qcom/tuna-vm-qrd.dtsi
Normal file
7
qcom/tuna-vm-qrd.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-vm-rcm-kiwi.dts
Normal file
16
qcom/tuna-vm-rcm-kiwi.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-rcm-kiwi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM RCM + kiwi WLAN";
|
||||
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
|
||||
"qcom,rcm";
|
||||
qcom,board-id = <21 1>;
|
||||
};
|
||||
7
qcom/tuna-vm-rcm-kiwi.dtsi
Normal file
7
qcom/tuna-vm-rcm-kiwi.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
16
qcom/tuna-vm-rcm.dts
Normal file
16
qcom/tuna-vm-rcm.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-rcm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM RCM";
|
||||
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
|
||||
"qcom,rcm";
|
||||
qcom,board-id = <21 0>;
|
||||
};
|
||||
7
qcom/tuna-vm-rcm.dtsi
Normal file
7
qcom/tuna-vm-rcm.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
};
|
||||
15
qcom/tuna-vm-rumi.dts
Normal file
15
qcom/tuna-vm-rumi.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna-vm.dtsi"
|
||||
#include "tuna-vm-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna SVM RUMI";
|
||||
compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi";
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
8
qcom/tuna-vm-rumi.dtsi
Normal file
8
qcom/tuna-vm-rumi.dtsi
Normal file
@@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&arch_timer {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
253
qcom/tuna-vm.dtsi
Normal file
253
qcom/tuna-vm.dtsi
Normal file
@@ -0,0 +1,253 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-tuna.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>;
|
||||
interrupt-parent = <&vgic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,vm-config {
|
||||
compatible = "qcom,vm-1.0";
|
||||
vm-type = "aarch64-guest";
|
||||
boot-config = "fdt,unified";
|
||||
os-type = "linux";
|
||||
kernel-entry-segment = "kernel";
|
||||
kernel-entry-offset = <0x0 0x0>;
|
||||
vendor = "QTI";
|
||||
image-name = "qcom,trustedvm";
|
||||
qcom,pasid = <0x0 0x1c>;
|
||||
qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;";
|
||||
qcom,secdomain-ids = <45>;
|
||||
qcom,primary-vm-index = <0>;
|
||||
vm-uri = "vmuid/trusted-ui";
|
||||
vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
|
||||
qcom,sensitive;
|
||||
|
||||
vm-attrs = "context-dump", "crash-restart";
|
||||
|
||||
/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
|
||||
* QUP1_SE4: GPII5 : IRQ_316
|
||||
* QUP2_SE7: GPII5 : IRQ_625
|
||||
*/
|
||||
gic-irq-ranges = <316 316
|
||||
625 625 /* PVM->SVM IRQ transfer */
|
||||
279 279>;
|
||||
|
||||
memory {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
/*
|
||||
* IPA address linux image is loaded at. Must be within
|
||||
* first 1GB due to memory hotplug requirement.
|
||||
*/
|
||||
base-address = <0x0 0x88800000 >;
|
||||
};
|
||||
|
||||
segments {
|
||||
config_cpio = <2>;
|
||||
};
|
||||
|
||||
vcpus {
|
||||
config = "/cpus";
|
||||
affinity = "proxy";
|
||||
affinity-map = <0x5 0x6>;
|
||||
sched-priority = <0>; /* relative to PVM */
|
||||
sched-timeslice = <2000>; /* in ms */
|
||||
};
|
||||
|
||||
interrupts {
|
||||
config = &vgic;
|
||||
};
|
||||
|
||||
vdevices {
|
||||
generate = "/hypervisor";
|
||||
|
||||
minidump {
|
||||
vdevice-type = "minidump";
|
||||
push-compatible = "qcom,minidump_rm";
|
||||
minidump_allowed;
|
||||
};
|
||||
|
||||
rm-rpc {
|
||||
vdevice-type = "rm-rpc";
|
||||
generate = "/hypervisor/qcom,resource-mgr";
|
||||
console-dev;
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
qcom,label = <0x1>;
|
||||
};
|
||||
|
||||
virtio-mmio@0 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x1>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x0>;
|
||||
memory {
|
||||
qcom,label = <0x11>; //for persist.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA6F8000>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@1 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x2>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x4000>;
|
||||
memory {
|
||||
qcom,label = <0x10>; //for system.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA6FC000>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@2 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
patch = "/soc/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x3>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x8000>;
|
||||
memory {
|
||||
qcom,label = <0x15>; //for virtio-vsock
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA700000>;
|
||||
};
|
||||
};
|
||||
|
||||
swiotlb-shm {
|
||||
vdevice-type = "shm";
|
||||
generate = "/swiotlb";
|
||||
push-compatible = "swiotlb";
|
||||
peer-default;
|
||||
dma_base = <0x0 0x14000>;
|
||||
memory {
|
||||
qcom,label = <0x12>;
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA70c000>;
|
||||
};
|
||||
};
|
||||
|
||||
vrtc {
|
||||
vdevice-type = "vrtc-pl031";
|
||||
peer-default;
|
||||
allocate-base;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
firmware: firmware {
|
||||
qcom_scm: qcom_scm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,dummycc";
|
||||
clock-output-names = "gcc_clocks";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
virtio-mmio {
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
vgic: interrupt-controller@17100000 {
|
||||
compatible = "arm,gic-v3";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x40000>;
|
||||
reg = <0x17100000 0x10000>, /* GICD */
|
||||
<0x17180000 0x200000>; /* GICR * 8 */
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
always-on;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
qcom_smcinvoke {
|
||||
compatible = "qcom,smcinvoke";
|
||||
};
|
||||
|
||||
qtee_shmbridge {
|
||||
compatible = "qcom,tee-shared-memory-bridge";
|
||||
qcom,custom-bridge-size = <64>;
|
||||
qcom,support-hypervisor;
|
||||
};
|
||||
};
|
||||
851
qcom/tuna.dtsi
851
qcom/tuna.dtsi
File diff suppressed because it is too large
Load Diff
13
qcom/tuna7.dts
Normal file
13
qcom/tuna7.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tuna7.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna 7 SoC";
|
||||
compatible = "qcom,tuna";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
11
qcom/tuna7.dtsi
Normal file
11
qcom/tuna7.dtsi
Normal file
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna 7";
|
||||
compatible = "qcom,tuna";
|
||||
qcom,msm-id = <681 0x10000>;
|
||||
};
|
||||
@@ -11,7 +11,7 @@
|
||||
|
||||
qcom,tui {
|
||||
qcom,dma-heap-name = "qcom,tui";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CARVEOUT>;
|
||||
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
|
||||
qcom,dynamic-heap;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -20,10 +20,11 @@
|
||||
|
||||
qcom,mem-buf-msgq {
|
||||
compatible = "qcom,mem-buf-msgq";
|
||||
qcom,msgq-names = "trusted_vm";
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable root=/dev/ram rw init=/init";
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable root=/dev/vda init=/sbin/init";
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
||||
Reference in New Issue
Block a user