From dcefaa95eb7547f2617d315c97cdbbe4b2338ae6 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 25 Jul 2024 18:17:22 +0800 Subject: [PATCH 01/67] ARM: dts: msm: rename "dynamic_clk" to "atclk" Rename "dynamic_clk" to "atclk", using atclk mode to handle this clock. Change-Id: I9284156854366657594728ebc7815ebe7a533281 Signed-off-by: Yuanfang Zhang --- qcom/sun-coresight.dtsi | 68 ++++++++++++++++++++--------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/qcom/sun-coresight.dtsi b/qcom/sun-coresight.dtsi index 6f0233e8..5c18f218 100644 --- a/qcom/sun-coresight.dtsi +++ b/qcom/sun-coresight.dtsi @@ -1765,7 +1765,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1788,7 +1788,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1811,7 +1811,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1834,7 +1834,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1857,7 +1857,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1880,7 +1880,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1903,7 +1903,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1926,7 +1926,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1949,7 +1949,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1972,7 +1972,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -1995,7 +1995,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -2018,7 +2018,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; out-ports { port { @@ -2055,7 +2055,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; in-ports { #address-cells = <1>; @@ -2251,7 +2251,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2360,7 +2360,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2469,7 +2469,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2578,7 +2578,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2687,7 +2687,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2796,7 +2796,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2833,7 +2833,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2927,7 +2927,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2962,7 +2962,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2999,7 +2999,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -3044,7 +3044,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -3149,7 +3149,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3257,7 +3257,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3294,7 +3294,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3356,7 +3356,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3391,7 +3391,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3428,7 +3428,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3473,7 +3473,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3506,7 +3506,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; in-ports { #address-cells = <1>; @@ -5627,7 +5627,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; }; cti@12195000 { @@ -5641,7 +5641,7 @@ clocks = <&aoss_qmp>, <&scmi_clk 0>; clock-names = "apb_pclk", - "dynamic_clk"; + "atclk"; }; cti@10a05000 { From ebb646f4b77d7ee3f315bb30e9c834615f38ebbf Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Fri, 6 Sep 2024 16:40:05 -0700 Subject: [PATCH 02/67] ARM: dts: msm: Align rcu expedited parameters for sunvm Use the same rcu configuration values on both PVM and QTVM. This reduces latency of synchronize_rcu(). Change-Id: If023ae452c56e6172c33ccb2b14767376f86268b Signed-off-by: Patrick Daly --- qcom/sun-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 494c5e9c..a380cb32 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -15,7 +15,7 @@ interrupt-parent = <&vgic>; chosen { - bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force"; + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force rcupdate.rcu_expedited=1 rcu_nocbs=0-1"; }; cpus { From 054c4aaedd5863fa76cde970b392be6ef5077180 Mon Sep 17 00:00:00 2001 From: songchai Date: Thu, 12 Sep 2024 16:56:34 +0800 Subject: [PATCH 03/67] ARM: dts: msm: Add debug component device tree for Kera Add debug component device tree for Kera. Change-Id: Iaf8453afc5659216c52a67fd1778645f2c960185 Signed-off-by: songchai --- qcom/kera-debug.dtsi | 461 +++++++++++++++++++++++++++++++++++++++++++ qcom/kera.dtsi | 2 +- 2 files changed, 462 insertions(+), 1 deletion(-) create mode 100644 qcom/kera-debug.dtsi diff --git a/qcom/kera-debug.dtsi b/qcom/kera-debug.dtsi new file mode 100644 index 00000000..da91ef64 --- /dev/null +++ b/qcom/kera-debug.dtsi @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dump_mem: mem_dump_region { + alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; + size = <0x0 0x1800000>; + }; +}; + +&soc { + dcc: dcc_v2@100ff000 { + compatible = "qcom,dcc-v2"; + reg = <0x100ff000 0x1000>, + <0x10084000 0x4000>; + + status = "disabled"; + qcom,transaction_timeout = <0>; + + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x4000>; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + static_dump { + qcom,static-mem-dump; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + l1_icache0 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb700 { + qcom,dump-size = <0x600>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb700 { + qcom,dump-size = <0xa00>; + qcom,dump-id = <0x47>; + }; + + l2_cache0 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc0>; + }; + + l2_cache100 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc1>; + }; + + l2_cache200 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc2>; + }; + + l2_cache300 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc3>; + }; + + l2_cache400 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x340100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x121>; + }; + + l2_tlb700 { + qcom,dump-size = <0xa900>; + qcom,dump-id = <0x127>; + }; + + l1dcdirty0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x170>; + }; + + l1dcdirty100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x171>; + }; + + l1dcmte0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x180>; + }; + + l1dcmte100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x181>; + }; + + l2dcmte0 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x190>; + }; + + l2dcmte100 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x191>; + }; + + l0mopca700 { + qcom,dump-size = <0x4100>; + qcom,dump-id = <0x1a7>; + }; + + l2victim700 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x1e7>; + }; + + l2tldtcsp200 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x202>; + }; + + l2tldtcsp300 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x203>; + }; + + l2tldtcsp400 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x204>; + }; + + l2tldtcsp500 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x205>; + }; + + l2tldtcsp600 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x206>; + }; + + l2tldtcmp200 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x212>; + }; + + l2tldtcmp300 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x213>; + }; + + l2tldtcmp400 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x214>; + }; + + l2tldtcmp500 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x215>; + }; + + l2tldtcmp600 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x216>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_slpi { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf3>; + }; + + etfslpi_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x103>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + + scandump_smmu { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x220>; + }; + }; + + dynamic_mem_dump { + qcom,dynamic-mem-dump; + + scandump_gpu { + scandump_gpu { + qcom,dump-size = <0x300000>; + qcom,dump-id = <0x221>; + }; + }; + + cpuss_reg { + cpuss_reg { + qcom,dump-size = <0x36000>; + qcom,dump-id = <0xef>; + }; + }; + + spr { + spr_cpu0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f0>; + }; + + spr_cpu1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f1>; + }; + + spr_cpu2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f2>; + }; + + spr_cpu3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f3>; + }; + + spr_cpu4 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f4>; + }; + + spr_cpu5 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f5>; + }; + + spr_cpu6 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f6>; + }; + + spr_cpu7 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f7>; + }; + }; + }; + }; +}; + diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 0fbeb4e6..4f53563d 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -746,7 +746,7 @@ size = <0x0 0x4800000>; }; }; - +#include "kera-debug.dtsi" #include "kera-pinctrl.dtsi" #include "kera-usb.dtsi" #include "kera-qupv3.dtsi" From 2d7a523cc41652e93ce930b8495379038a58a599 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 16 Sep 2024 11:43:20 +0530 Subject: [PATCH 04/67] ARM: dts: msm: Add secure-buffer device for kera Add the secure-buffer device, which supports hypervisor operations to change the stage 2 permissions of memory. Change-Id: If7a38ffd1cfa769b26b8f1d05b676f9e7eb33cf8 Signed-off-by: Vijayanand Jitta --- qcom/kera.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index bd553f2e..bf1e2f51 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -319,6 +319,11 @@ }; }; + qcom,secure-buffer { + compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + apps_rsc: rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From 25fa36375485ab07566cc173b2135654686c2a5c Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 16 Sep 2024 14:23:59 +0530 Subject: [PATCH 05/67] ARM: dts: msm: Add smmu ACLTR values for kera Configure per-context bank pre-fetch settings using actlr for kera. Change-Id: Ice9f79801b8ff0f7ae73f720c87c27cb9d531141 Signed-off-by: Vijayanand Jitta --- qcom/msm-arm-smmu-kera.dtsi | 46 +++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/qcom/msm-arm-smmu-kera.dtsi b/qcom/msm-arm-smmu-kera.dtsi index a18d50fe..106a073f 100644 --- a/qcom/msm-arm-smmu-kera.dtsi +++ b/qcom/msm-arm-smmu-kera.dtsi @@ -44,6 +44,10 @@ , ; + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x000 0x3ff 0x32B>; + gpu_qtb: gpu_qtb@03de8000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; reg = <0x3de8000 0x1000>; @@ -179,6 +183,48 @@ , ; + qcom,actlr = + /* CAM_HF:Camera */ + <0x1c00 0x0000 0x00000001>, + + /* Mnoc_HF_23:Display */ + <0x0800 0x0002 0x00000001>, + <0x0801 0x0000 0x00000001>, + + /* NSP:Compute */ + <0x0c01 0x0000 0x00000303>, + <0x0c02 0x0000 0x00000303>, + <0x0c03 0x0000 0x00000303>, + <0x0c04 0x0000 0x00000303>, + <0x0c05 0x0000 0x00000303>, + <0x0c06 0x0000 0x00000303>, + <0x0c07 0x0000 0x00000303>, + <0x0c08 0x0000 0x00000303>, + <0x0c09 0x0000 0x00000303>, + <0x0c0c 0x0000 0x00000303>, + <0x0c0d 0x0000 0x00000303>, + <0x0c0e 0x0000 0x00000303>, + + /* SF:Camera */ + <0x1800 0x00c0 0x00000001>, + <0x1820 0x0000 0x00000001>, + <0x1860 0x0000 0x00000103>, + <0x18a0 0x0000 0x00000103>, + <0x18e0 0x0000 0x00000103>, + <0x1980 0x0000 0x00000001>, + + /* SF:EVA */ + <0x1900 0x0020 0x00000103>, + <0x1904 0x0020 0x00000103>, + <0x1923 0x0000 0x00000103>, + + /* SF:Video */ + <0x1940 0x0000 0x00000103>, + <0x1941 0x0004 0x00000103>, + <0x1943 0x0000 0x00000103>, + <0x1944 0x0000 0x00000103>, + <0x1947 0x0000 0x00000103>; + anoc_1_qtb: anoc_1_qtb@16f2000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; reg = <0x16f2000 0x1000>; From 7cb884c241db67c18a16f0ec2c8d433a0a4fbfbf Mon Sep 17 00:00:00 2001 From: Prasanna S Date: Wed, 28 Aug 2024 15:12:38 +0530 Subject: [PATCH 06/67] ARM: dts: msm: Add QUPv3 and GPI DT nodes on tuna Add QUPv3(I2C, SPI and UART) and GPI DT nodes on tuna. Change-Id: Ic5da9c0b56a51dca90368db65458a2e075efe5c1 Signed-off-by: Prasanna S --- qcom/tuna-pinctrl.dtsi | 1536 ++++++++++++++++++++++++++++++++++++++++ qcom/tuna-qupv3.dtsi | 752 +++++++++++++++++++- qcom/tuna.dtsi | 27 + 3 files changed, 2314 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-pinctrl.dtsi b/qcom/tuna-pinctrl.dtsi index 83a10696..ad6406c2 100644 --- a/qcom/tuna-pinctrl.dtsi +++ b/qcom/tuna-pinctrl.dtsi @@ -4,6 +4,714 @@ */ &tlmm { + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio52"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio53"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio52"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio53"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio54"; + function = "qup1_se0_l2"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup1_se0_l3"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { + mux { + pins = "gpio4"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { + mux { + pins = "gpio5"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { + mux { + pins = "gpio4"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { + mux { + pins = "gpio5"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup1_se1_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup1_se1_l3"; + }; + + config { + pins = "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio10"; + function = "qup1_se2_l2"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio11"; + function = "qup1_se2_l3"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio60"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio61"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio60", "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { + mux { + pins = "gpio16"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { + mux { + pins = "gpio17"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { + mux { + pins = "gpio16"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { + mux { + pins = "gpio17"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active { + mux { + pins = "gpio18"; + function = "qup1_se4_l2"; + }; + + config { + pins = "gpio18"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active { + mux { + pins = "gpio19"; + function = "qup1_se4_l3"; + }; + + config { + pins = "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio12"; + function = "qup1_se5_l0"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio13"; + function = "qup1_se5_l1"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active { + mux { + pins = "gpio12"; + function = "qup1_se5_l0"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active { + mux { + pins = "gpio13"; + function = "qup1_se5_l1"; + }; + + config { + pins = "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active { + mux { + pins = "gpio14"; + function = "qup1_se5_l2"; + }; + + config { + pins = "gpio14"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active { + mux { + pins = "gpio15"; + function = "qup1_se5_l3"; + }; + + config { + pins = "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio24"; + function = "qup1_se6_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio25"; + function = "qup1_se6_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio24"; + function = "qup1_se6_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio25"; + function = "qup1_se6_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio26"; + function = "qup1_se6_l2"; + }; + + config { + pins = "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio27"; + function = "qup1_se6_l3"; + }; + + config { + pins = "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + qupv3_se7_2uart_pins: qupv3_se7_2uart_pins { qupv3_se7_2uart_tx_active: qupv3_se7_2uart_tx_active { mux { @@ -44,4 +752,832 @@ }; }; }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active { + mux { + pins = "gpio0"; + function = "qup2_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active { + mux { + pins = "gpio1"; + function = "qup2_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active { + mux { + pins = "gpio0"; + function = "qup2_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active { + mux { + pins = "gpio1"; + function = "qup2_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active { + mux { + pins = "gpio2"; + function = "qup2_se0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active { + mux { + pins = "gpio3"; + function = "qup2_se0_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active { + mux { + pins = "gpio179"; + function = "qup2_se1_l0"; + }; + + config { + pins = "gpio179"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active { + mux { + pins = "gpio180"; + function = "qup2_se1_l1"; + }; + + config { + pins = "gpio180"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio179", "gpio180"; + function = "gpio"; + }; + + config { + pins = "gpio179", "gpio180"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_sda_active: qupv3_se10_i2c_sda_active { + mux { + pins = "gpio56"; + function = "qup2_se2_l0"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se10_i2c_scl_active: qupv3_se10_i2c_scl_active { + mux { + pins = "gpio57"; + function = "qup2_se2_l1"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_miso_active: qupv3_se10_spi_miso_active { + mux { + pins = "gpio56"; + function = "qup2_se2_l0"; + }; + + config { + pins = "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_mosi_active: qupv3_se10_spi_mosi_active { + mux { + pins = "gpio57"; + function = "qup2_se2_l1"; + }; + + config { + pins = "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_clk_active: qupv3_se10_spi_clk_active { + mux { + pins = "gpio58"; + function = "qup2_se2_l2"; + }; + + config { + pins = "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_cs_active: qupv3_se10_spi_cs_active { + mux { + pins = "gpio59"; + function = "qup2_se2_l3"; + }; + + config { + pins = "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_sda_active: qupv3_se11_i2c_sda_active { + mux { + pins = "gpio36"; + function = "qup2_se3_l0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se11_i2c_scl_active: qupv3_se11_i2c_scl_active { + mux { + pins = "gpio37"; + function = "qup2_se3_l1"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_miso_active: qupv3_se11_spi_miso_active { + mux { + pins = "gpio36"; + function = "qup2_se3_l0"; + }; + + config { + pins = "gpio36"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_mosi_active: qupv3_se11_spi_mosi_active { + mux { + pins = "gpio37"; + function = "qup2_se3_l1"; + }; + + config { + pins = "gpio37"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_clk_active: qupv3_se11_spi_clk_active { + mux { + pins = "gpio38"; + function = "qup2_se3_l2"; + }; + + config { + pins = "gpio38"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_cs_active: qupv3_se11_spi_cs_active { + mux { + pins = "gpio39"; + function = "qup2_se3_l3"; + }; + + config { + pins = "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_sda_active: qupv3_se12_i2c_sda_active { + mux { + pins = "gpio32"; + function = "qup2_se4_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se12_i2c_scl_active: qupv3_se12_i2c_scl_active { + mux { + pins = "gpio33"; + function = "qup2_se4_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_miso_active: qupv3_se12_spi_miso_active { + mux { + pins = "gpio32"; + function = "qup2_se4_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_mosi_active: qupv3_se12_spi_mosi_active { + mux { + pins = "gpio33"; + function = "qup2_se4_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_clk_active: qupv3_se12_spi_clk_active { + mux { + pins = "gpio34"; + function = "qup2_se4_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_cs_active: qupv3_se12_spi_cs_active { + mux { + pins = "gpio35"; + function = "qup2_se4_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_sda_active: qupv3_se13_i2c_sda_active { + mux { + pins = "gpio20"; + function = "qup2_se5_l0"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se13_i2c_scl_active: qupv3_se13_i2c_scl_active { + mux { + pins = "gpio21"; + function = "qup2_se5_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_miso_active: qupv3_se13_spi_miso_active { + mux { + pins = "gpio20"; + function = "qup2_se5_l0"; + }; + + config { + pins = "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_mosi_active: qupv3_se13_spi_mosi_active { + mux { + pins = "gpio21"; + function = "qup2_se5_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_clk_active: qupv3_se13_spi_clk_active { + mux { + pins = "gpio22"; + function = "qup2_se5_l2"; + }; + + config { + pins = "gpio22"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_cs_active: qupv3_se13_spi_cs_active { + mux { + pins = "gpio23"; + function = "qup2_se5_l3"; + }; + + config { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_4uart_pins: qupv3_se14_4uart_pins { + qupv3_se14_default_cts: qupv3_se14_default_cts { + mux { + pins = "gpio40"; + function = "gpio"; + }; + + config { + pins = "gpio40"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_default_rts: qupv3_se14_default_rts { + mux { + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_default_tx: qupv3_se14_default_tx { + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_default_rx: qupv3_se14_default_rx { + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_cts: qupv3_se14_cts { + mux { + pins = "gpio40"; + function = "qup2_se6_l0"; + }; + + config { + pins = "gpio40"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_rts: qupv3_se14_rts { + mux { + pins = "gpio41"; + function = "qup2_se6_l1"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_tx: qupv3_se14_tx { + mux { + pins = "gpio42"; + function = "qup2_se6_l2"; + }; + + config { + pins = "gpio42"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_rx_active: qupv3_se14_rx_active { + mux { + pins = "gpio43"; + function = "qup2_se6_l3"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* RX to be in gpio mode for sleep config */ + qupv3_se14_rx_wake: qupv3_se14_rx_wake { + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_sda_active: qupv3_se15_i2c_sda_active { + mux { + pins = "gpio44"; + function = "qup2_se7_l0"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se15_i2c_scl_active: qupv3_se15_i2c_scl_active { + mux { + pins = "gpio45"; + function = "qup2_se7_l1"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_miso_active: qupv3_se15_spi_miso_active { + mux { + pins = "gpio44"; + function = "qup2_se7_l0"; + }; + + config { + pins = "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_mosi_active: qupv3_se15_spi_mosi_active { + mux { + pins = "gpio45"; + function = "qup2_se7_l1"; + }; + + config { + pins = "gpio45"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_clk_active: qupv3_se15_spi_clk_active { + mux { + pins = "gpio46"; + function = "qup2_se7_l2"; + }; + + config { + pins = "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_cs_active: qupv3_se15_spi_cs_active { + mux { + pins = "gpio47"; + function = "qup2_se7_l3"; + }; + + config { + pins = "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; diff --git a/qcom/tuna-qupv3.dtsi b/qcom/tuna-qupv3.dtsi index f7100943..8e7e3077 100644 --- a/qcom/tuna-qupv3.dtsi +++ b/qcom/tuna-qupv3.dtsi @@ -4,7 +4,62 @@ */ &soc { - /* QUPv3_1 Wrapper Instance */ + /* QUPv3 SE Instances + * Qup1 0: SE 0 + * Qup1 1: SE 1 + * Qup1 2: SE 2 + * Qup1 3: SE 3 + * Qup1 4: SE 4 + * Qup1 5: SE 5 + * Qup1 6: SE 6 + * Qup1 7: SE 7 + * Qup2 0: SE 8 + * Qup2 1: SE 9 + * Qup2 2: SE 10 + * Qup2 3: SE 11 + * Qup2 4: SE 12 + * Qup2 5: SE 13 + * Qup2 6: SE 14 + * Qup2 7: SE 15 + */ + + qup1_gpi_iommu_region: qup1_gpi_iommu_region { + iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x1f>; + qcom,ev-factor = <1>; + memory-region = <&qup1_gpi_iommu_region>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + qup1_se_iommu_region: qup1_se_iommu_region { + iommu-addresses = <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>; + }; + + /* QUPv3_1 wrapper instance */ qupv3_1: qcom,qupv3_1_geni_se@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0xac0000 0x2000>; @@ -13,9 +68,319 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xa3 0x0>; + memory-region = <&qup1_se_iommu_region>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; ranges; status = "ok"; + qupv3_se0_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, + <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, + <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma1 0 5 3 1024 0>, + <&gpi_dma1 1 5 3 1024 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + qupv3_se5_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, + <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a98000 { + compatible = "qcom,spi-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + /* Debug UART Instance */ qupv3_se7_2uart: qcom,qup_uart@a9c000 { compatible = "qcom,geni-debug-uart"; @@ -30,4 +395,389 @@ status = "disabled"; }; }; + qup2_gpi_iommu_region: qup2_gpi_iommu_region { + iommu-addresses = <&gpi_dma2 0x0 0x100000>, <&gpi_dma2 0x200000 0xffe00000>; + }; + + /* GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x436 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x1f>; + qcom,ev-factor = <1>; + memory-region = <&qup2_gpi_iommu_region>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + qup2_se_iommu_region: qup2_se_iommu_region { + iommu-addresses = <&qupv3_2 0x0 0x40000000>, <&qupv3_2 0x50000000 0xb0000000>; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x423 0x0>; + memory-region = <&qup2_se_iommu_region>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + qupv3_se8_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma2 0 0 3 64 0>, + <&gpi_dma2 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se8_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, + <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + dmas = <&gpi_dma2 0 0 1 64 0>, + <&gpi_dma2 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma2 0 1 3 64 0>, + <&gpi_dma2 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + dmas = <&gpi_dma2 0 2 3 64 0>, + <&gpi_dma2 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se10_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>, + <&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + dmas = <&gpi_dma2 0 2 1 64 0>, + <&gpi_dma2 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + dmas = <&gpi_dma2 0 3 3 64 0>, + <&gpi_dma2 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se11_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>, + <&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + dmas = <&gpi_dma2 0 3 1 64 0>, + <&gpi_dma2 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + dmas = <&gpi_dma2 0 4 3 64 0>, + <&gpi_dma2 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se12_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>, + <&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + dmas = <&gpi_dma2 0 4 1 64 0>, + <&gpi_dma2 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_sda_active>, <&qupv3_se13_i2c_scl_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + dmas = <&gpi_dma2 0 5 3 64 0>, + <&gpi_dma2 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se13_spi: spi@894000 { + compatible = "qcom,spi-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_mosi_active>, <&qupv3_se13_spi_miso_active>, + <&qupv3_se13_spi_clk_active>, <&qupv3_se13_spi_cs_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + dmas = <&gpi_dma2 0 5 1 64 0>, + <&gpi_dma2 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se14_4uart: qcom,qup_uart@898000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 43 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>, + <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>; + pinctrl-1 = <&qupv3_se14_cts>, <&qupv3_se14_rts>, + <&qupv3_se14_tx>, <&qupv3_se14_rx_active>; + pinctrl-2 = <&qupv3_se14_cts>, <&qupv3_se14_rts>, + <&qupv3_se14_tx>, <&qupv3_se14_rx_wake>; + pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>, + <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>; + qcom,wakeup-byte = <0xFD>; + qcom,suspend-ignore-children; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + dmas = <&gpi_dma2 0 7 3 64 0>, + <&gpi_dma2 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se15_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>, + <&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + dmas = <&gpi_dma2 0 7 1 64 0>, + <&gpi_dma2 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; }; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 620dacd7..d8680303 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -50,6 +50,33 @@ aliases { serial0 = &qupv3_se7_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + hsuart0 = &qupv3_se14_4uart; + i2c0 = &qupv3_se0_i2c; + i2c1 = &qupv3_se1_i2c; + i2c2 = &qupv3_se2_i2c; + i2c3 = &qupv3_se3_i2c; + i2c4 = &qupv3_se4_i2c; + i2c5 = &qupv3_se5_i2c; + i2c6 = &qupv3_se6_i2c; + i2c8 = &qupv3_se8_i2c; + i2c9 = &qupv3_se9_i2c; + i2c10 = &qupv3_se10_i2c; + i2c11 = &qupv3_se11_i2c; + i2c12 = &qupv3_se12_i2c; + i2c13 = &qupv3_se13_i2c; + i2c15 = &qupv3_se15_i2c; + spi0 = &qupv3_se0_spi; + spi1 = &qupv3_se1_spi; + spi2 = &qupv3_se2_spi; + spi4 = &qupv3_se4_spi; + spi5 = &qupv3_se5_spi; + spi6 = &qupv3_se6_spi; + spi8 = &qupv3_se8_spi; + spi10 = &qupv3_se10_spi; + spi11 = &qupv3_se11_spi; + spi12 = &qupv3_se12_spi; + spi13 = &qupv3_se13_spi; + spi15 = &qupv3_se15_spi; }; cpus { From 4b0c79c3b43c2984fce8c97f7fa7807bc3d71f20 Mon Sep 17 00:00:00 2001 From: Balaji Vekatesh Kalkonda Date: Fri, 13 Sep 2024 12:13:13 +0530 Subject: [PATCH 07/67] ARM: dts: qcom: add goodix touch support for Parrot RCM platform Add goodix touch support for Parrot RCM platform. Change-Id: I0a23d64fae1425be07903d9b8ed04b363db22c2c Signed-off-by: Balaji Vekatesh Kalkonda --- qcom/parrot-idp-wcn3990-amoled-rcm.dtsi | 4 ++++ qcom/parrot-idp-wcn6750-amoled-rcm.dtsi | 4 ++++ qcom/parrot-idp-wcn6750-amoled.dtsi | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/qcom/parrot-idp-wcn3990-amoled-rcm.dtsi b/qcom/parrot-idp-wcn3990-amoled-rcm.dtsi index b21bcc8f..43fedf7a 100644 --- a/qcom/parrot-idp-wcn3990-amoled-rcm.dtsi +++ b/qcom/parrot-idp-wcn3990-amoled-rcm.dtsi @@ -17,8 +17,10 @@ #size-cells = <0>; status = "ok"; qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; goodix-berlin@0 { + compatible = "goodix,gt9916S"; reg = <0>; spi-max-frequency = <1000000>; @@ -42,6 +44,8 @@ pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; pinctrl-2 = <&ts_spi_release>; + goodix,touch-type = "primary"; + goodix,qts_en; qcom,touch-environment = "pvm"; }; }; diff --git a/qcom/parrot-idp-wcn6750-amoled-rcm.dtsi b/qcom/parrot-idp-wcn6750-amoled-rcm.dtsi index b21bcc8f..50b658bc 100644 --- a/qcom/parrot-idp-wcn6750-amoled-rcm.dtsi +++ b/qcom/parrot-idp-wcn6750-amoled-rcm.dtsi @@ -17,8 +17,10 @@ #size-cells = <0>; status = "ok"; qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; goodix-berlin@0 { + compatible = "goodix,gt9916S"; reg = <0>; spi-max-frequency = <1000000>; @@ -41,6 +43,8 @@ pinctrl-0 = <&ts_spi_active>; pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; pinctrl-2 = <&ts_spi_release>; + goodix,touch-type = "primary"; + goodix,qts_en; qcom,touch-environment = "pvm"; }; diff --git a/qcom/parrot-idp-wcn6750-amoled.dtsi b/qcom/parrot-idp-wcn6750-amoled.dtsi index b21bcc8f..43fedf7a 100644 --- a/qcom/parrot-idp-wcn6750-amoled.dtsi +++ b/qcom/parrot-idp-wcn6750-amoled.dtsi @@ -17,8 +17,10 @@ #size-cells = <0>; status = "ok"; qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; goodix-berlin@0 { + compatible = "goodix,gt9916S"; reg = <0>; spi-max-frequency = <1000000>; @@ -42,6 +44,8 @@ pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; pinctrl-2 = <&ts_spi_release>; + goodix,touch-type = "primary"; + goodix,qts_en; qcom,touch-environment = "pvm"; }; }; From 595cfd532244025675bb589c60a7217225639484 Mon Sep 17 00:00:00 2001 From: Krishna Chaithanya Reddy G Date: Tue, 17 Sep 2024 13:44:43 +0530 Subject: [PATCH 08/67] ARM: dts: msm: Add SPS node for sdxkova Add SPS module to device tree. SPS (Smart Peripheral System) enables the support of all BAMs in the system which provide DMA functionality to various peripherals for Niobe. Change-Id: I54640b7c444744f527414280021186fd90e0acf5 Signed-off-by: Krishna Chaithanya Reddy G --- qcom/sdxkova.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index 48818679..bf209812 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -1317,6 +1317,11 @@ cap-based-alloc-and-pwr-collapse; }; + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + qcom,msm-imem@14680000 { compatible = "qcom,msm-imem"; reg = <0x0 0x14680000 0x0 0x1000>; From 72084502209a6dc179575157ea1048c8ab4193db Mon Sep 17 00:00:00 2001 From: Balaji Vekatesh Kalkonda Date: Fri, 30 Aug 2024 10:58:08 +0530 Subject: [PATCH 09/67] ARM: dts: qcom: Enable touch for ravelin QRD The addition of compatible string enables touch for ravelin QRD device. Change-Id: I3a02ae436c7214c0f71a0abd3a6f1854ba62f219 Signed-off-by: Balaji Vekatesh Kalkonda --- qcom/ravelin-qrd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/ravelin-qrd.dtsi b/qcom/ravelin-qrd.dtsi index c7264dfd..bfc40dbc 100644 --- a/qcom/ravelin-qrd.dtsi +++ b/qcom/ravelin-qrd.dtsi @@ -20,7 +20,7 @@ focaltech@38 { status = "ok"; reg = <0x38>; - + compatible = "focaltech,fts_ts"; interrupt-parent = <&tlmm>; interrupts = <13 0x2008>; focaltech,reset-gpio = <&tlmm 12 0x00>; From 5b85a5f24346372320b7ba99644855ce2e23b62c Mon Sep 17 00:00:00 2001 From: Varshitha H N Date: Wed, 11 Sep 2024 16:19:05 +0530 Subject: [PATCH 10/67] dt-bindings: regulator: Add bindings for qpnp-lcdb-regulator device Add bindings for qpnp-lcdb-regulator devices. Change-Id: Ie707a7b048c4b259e909b20364ae182ac95673d3 Signed-off-by: Varshitha H N --- .../regulator/qcom,qpnp-lcdb-regulator.yaml | 291 ++++++++++++++++++ 1 file changed, 291 insertions(+) create mode 100644 bindings/regulator/qcom,qpnp-lcdb-regulator.yaml diff --git a/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml b/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml new file mode 100644 index 00000000..4b7cbd70 --- /dev/null +++ b/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/qcom,qpnp-lcdb-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QPNP LCDB (LCD Bias) Regulator + +maintainers: + - Jishnu Prakash + +description: | + QPNP LCDB module provides voltage bias to the LCD display panel. The biases + are positive (VDISP - supported by LDO) and negative (VDISN - supported by + NCP) voltage signals. The module also supports TTW (touch-to-wake) capability. + +properties: + compatible: + enum: + - qcom,qpnp-lcdb-regulator + - qcom,lcdb-pm660 + - qcom,lcdb-pmi632 + - qcom,lcdb-pm6150l + - qcom,lcdb-pm7325b + + reg: + description: Base address of the LCDB SPMI peripheral. + + qcom,voltage-step-ramp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Required only if the voltage needs to be set in the + steps of 500 mV starting from the 4500 mV. This needs + to be enabled only on platforms where voltage needs to + be ramped up with multiple steps. + + qcom,pwrdn-delay-ms: + description: Required to control the LDO power down delay. + Possible values are 0, 1, 4, 8. + + qcom,pwrup-delay-ms: + description: Required to control the LDO power up delay. + Possible values are 0, 1, 4, 8. + + qcom,pwrup-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Controls the order of powering up BOOST, LDO AND NCP + blocks. Appilcable for PM7325B. Possible values are 0, 1, 2, 3, 4. + 0 - Boost, LDO, NCP + 1 - Boost, LDO + 2 - Boost, NCP + 3 - Boost only + 4 - Boost, NCP, LDO + + qcom,ttw-enable: + type: boolean + description: Touch to wake-up support enabled. + + qcom,ttw-mode-sw: + type: boolean + description: Touch to wake supported in SW mode. + If not defined, ttw is enabled by HW pin. + + qcom,attw-toff-ms: + maxItems: 1 + description: Off time (in mS) for the VDISP/VDISN signals. + Possible values are 4, 8, 16, 32. + + qcom,attw-ton-ms: + maxItems: 1 + description: ON time (in mS) for the VDISP/VDISN signals. + Possible values are 4, 8, 16, 32. + +patternProperties: + "^lcdb_[0-9a-f]+$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + description: LDO and NCP bias common properties + + properties: + label: + description: | + A string used to describe the bias type. + Possible values are ldo, ncp, bst. + $ref: /schemas/types.yaml#/definitions/string + + regulator-name: + $ref: /schemas/types.yaml#/definitions/string + description: | + Load current in uA which corresponds to the minimum load + which requires the regulator to be in high power mode. + + regulator-min-microvolt: + description: | + Minimum voltage (in uV) supported by the bias. + + regulator-max-microvolt: + description: | + Maximum voltage (in uV) supported by the bias. + + "^lcdb_ldo_[0-9a-f]+$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + description: LDO bias specific properties + + properties: + qcom,ldo-voltage-mv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Voltage (in mV) progammed for the LDO (VDISP). + Possile values are 4000mV to 6000mV. The range + 4000mV to 4900mV is in 100mV steps and 4900mV to + 6000mV is in 50mV steps. + + qcom,ldo-pd: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Pull-down configuration of LDO. Possible values are + 1 - Enable pull-down + 0 - Disable pull-down + + qcom,ldo-pd-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Pull-down strength. Possible values are + 0 - Weak pull-down + 1 - Strong pull-down + + qcom,ldo-ilim-ma: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current limit (in mA) of the LDO bias. For PM7325B, possible + values are 35, 175, 280, 420, 455, 595, 700, 840. For other PMICs, + possible values are 110, 160, 210, 260, 310, 360, 410, 460. + + qcom,ldo-soft-start-us: + description: | + Soft-start time (in uS) of the LDO bias. + Possible values are 0, 500, 1000, 2000. + + "^lcdb_ncp_[0-9a-f]+$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + description: NCP bias specific properties + + properties: + qcom,ncp-voltage-mv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Voltage (in mV) progammed for the NCP (VDISN). + Possile values are 4000mV to 6000mV. The range + 4000mV to 4900mV is in 100mV steps and 4900mV to + 6000mV is in 50mV steps. + + qcom,ncp-pd: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Pull-down configuration of NCP. Possible values are + 1 - Enable pull-down + 0 - Disable pull-down + + qcom,ncp-pd-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Pull-down strength. Possible values are + 0 - Weak pull-down + 1 - Strong pull-down + + qcom,ncp-ilim-ma: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current limit (in mA) of the NCP bias. For PM7325B, possible + values are 700, 80, 900, 1000. For other PMICs, possible values + are 260, 460, 640, 810. + + qcom,ncp-soft-start-us: + description: | + Soft-start time (in uS) of the NCP bias. + Possible values are 0, 500, 1000, 2000. + + "^lcdb_bst[0-9a-f]+$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + description: BOOST subnode specific properties + + properties: + qcom,bst-pd: + type: boolean + description: Pull-down configuration of BOOST. Possible values are + 1 - Enable pull-down + 0 - Disable pull-down + + qcom,bst-pd-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Pull-down strength. Possible values are + 0 - Weak pull-down + 1 - Strong pull-down + + qcom,bst-ps: + description: | + Pulse-skip configuration for boost. Possible values are + 1 - Enable Pulse-skip + 0 - Disable Pulse-skip + + qcom,bst-ps-threshold-ma: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current threshold (in mA) at which pulse-skip is entered. + Possible values are 50, 60, 70, 80. + + qcom,bst-ps-threshold-mv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current threshold (in mv) at which pulse-skip is entered. + Applicable for PM7325B. Possible values are 360, 384, 408, 432, + 456, 480, 504, 528. + + qcom,bst-ilim-ma: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current limit (in mA) of the BOOST rail. For PM7325B, possible + possible values are 1130 to 2250mA in 160mA steps. For other PMICs, + possible values are 200 to 1600mA in 200mA steps. + + qcom,bst-headroom-mv: + $ref: /schemas/types.yaml#/definitions/uint16 + description: | + Headroom of the boost (in mV). If not specified, then the + default value is 200 mV (PM660L) or 150 mV (for PM8150L or PMI632). + + required: + - label + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + +required: + - compatible + - reg + - qcom,ttw-enable + +additionalProperties: false + +examples: + - | + + pm660l_lcdb: qpnp-lcdb@ec00 { + compatible = "qcom,qpnp-lcdb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xec00 0x100>; + + qcom,ttw-enable; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + + qcom,ldo-voltage-mv = <5400>; + qcom,ldo-pd = <1>; + qcom,ldo-pd-strength = <1>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + + qcom,ncp-voltage-mv = <5400>; + qcom,ncp-pd = <1>; + qcom,ncp-pd-strength = <1>; + }; + + lcdb_bst: bst { + label = "bst"; + + qcom,bst-pd = <1>; + qcom,bst-pd-strength = <1>; + qcom,bst-ps = <1>; + qcom,bst-ps-threshold-ma = <50>; + qcom,bst-headroom-mv = <200>; + }; + }; + From 579617980cc4bdc704201be2ece34b147d29dbfc Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Tue, 17 Sep 2024 20:20:44 -0700 Subject: [PATCH 11/67] ARM: dts: msm: Update transaction timeout for sun Update DCC transaction timeout value to 0x80. Change-Id: I11271d05416b49f8c7c9055de71273c4d36bc3f9 Signed-off-by: Mao Jinlong --- qcom/sun-debug.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun-debug.dtsi b/qcom/sun-debug.dtsi index 29705889..e47d5f8d 100644 --- a/qcom/sun-debug.dtsi +++ b/qcom/sun-debug.dtsi @@ -23,7 +23,7 @@ <0x10080800 0x7800>; reg-names = "dcc-base", "dcc-ram-base"; - qcom,transaction_timeout = <0>; + qcom,transaction_timeout = <0x80>; dcc-ram-offset = <0x800>; link_list_0 { From 33de48bd13aaae357cfdc1dce8776772c6798917 Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Tue, 16 Jul 2024 16:56:35 +0530 Subject: [PATCH 12/67] ARM: dts: msm: Enable flash, PON, PWM & other nodes for Ravelin Add compatible strings to PON, PWM-LPG, VIBRATOR, FLASH-V2 and PMI632 gpio DT nodes for Ravelin. These were removed from the bulk DT porting for Ravelin on qcom-6.6 device-tree branch. Change-Id: I5e9d6a98fe537b805174b520239f12bfbf676a52 Signed-off-by: Shilpa Suresh --- qcom/pmi632.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi index 81017af1..ab5b1805 100644 --- a/qcom/pmi632.dtsi +++ b/qcom/pmi632.dtsi @@ -20,6 +20,7 @@ #size-cells = <0>; pmi632_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; reg = <0x800>; }; @@ -143,6 +144,7 @@ }; pmi632_gpios: pinctrl@c000 { + compatible = "qcom,pmi632-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; @@ -186,12 +188,14 @@ #size-cells = <0>; pmi632_vib: qcom,vibrator@5700 { + compatible = "qcom,qpnp-vibrator-ldo"; reg = <0x5700>; qcom,vib-ldo-volt-uv = <3000000>; qcom,disable-overdrive; }; pmi632_pwm: qcom,pwms@b300 { + compatible = "qcom,pwm-lpg"; reg = <0xb300>; reg-names = "lpg-base"; #pwm-cells = <2>; @@ -256,6 +260,7 @@ pmi632_lcdb: qpnp-lcdb@ec00 { status = "disabled"; + compatible = "qcom,lcdb-pmi632"; #address-cells = <1>; #size-cells = <0>; reg = <0xec00>; @@ -287,6 +292,7 @@ }; flash_led: qcom,leds@d300 { + compatible = "qcom,pmi632-flash-led-v2"; reg = <0xd300>; label = "flash"; interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, From 275cefb5be4c096c92a86d8334b4b4e4734713ae Mon Sep 17 00:00:00 2001 From: songchai Date: Wed, 18 Sep 2024 18:03:52 +0800 Subject: [PATCH 13/67] ARM: dts: msm: add memory dump entry for tuna Add memory dump entry for tuna to collect dump data. Change-Id: I53bd8e4b2d4ae180eff5b8f8dd46010901b7f401 Signed-off-by: songchai --- qcom/tuna-debug.dtsi | 461 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 461 insertions(+) create mode 100644 qcom/tuna-debug.dtsi diff --git a/qcom/tuna-debug.dtsi b/qcom/tuna-debug.dtsi new file mode 100644 index 00000000..da91ef64 --- /dev/null +++ b/qcom/tuna-debug.dtsi @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dump_mem: mem_dump_region { + alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; + size = <0x0 0x1800000>; + }; +}; + +&soc { + dcc: dcc_v2@100ff000 { + compatible = "qcom,dcc-v2"; + reg = <0x100ff000 0x1000>, + <0x10084000 0x4000>; + + status = "disabled"; + qcom,transaction_timeout = <0>; + + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x4000>; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + static_dump { + qcom,static-mem-dump; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + l1_icache0 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb700 { + qcom,dump-size = <0x600>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb700 { + qcom,dump-size = <0xa00>; + qcom,dump-id = <0x47>; + }; + + l2_cache0 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc0>; + }; + + l2_cache100 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc1>; + }; + + l2_cache200 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc2>; + }; + + l2_cache300 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc3>; + }; + + l2_cache400 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x340100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x121>; + }; + + l2_tlb700 { + qcom,dump-size = <0xa900>; + qcom,dump-id = <0x127>; + }; + + l1dcdirty0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x170>; + }; + + l1dcdirty100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x171>; + }; + + l1dcmte0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x180>; + }; + + l1dcmte100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x181>; + }; + + l2dcmte0 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x190>; + }; + + l2dcmte100 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x191>; + }; + + l0mopca700 { + qcom,dump-size = <0x4100>; + qcom,dump-id = <0x1a7>; + }; + + l2victim700 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x1e7>; + }; + + l2tldtcsp200 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x202>; + }; + + l2tldtcsp300 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x203>; + }; + + l2tldtcsp400 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x204>; + }; + + l2tldtcsp500 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x205>; + }; + + l2tldtcsp600 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x206>; + }; + + l2tldtcmp200 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x212>; + }; + + l2tldtcmp300 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x213>; + }; + + l2tldtcmp400 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x214>; + }; + + l2tldtcmp500 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x215>; + }; + + l2tldtcmp600 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x216>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_slpi { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf3>; + }; + + etfslpi_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x103>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + + scandump_smmu { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x220>; + }; + }; + + dynamic_mem_dump { + qcom,dynamic-mem-dump; + + scandump_gpu { + scandump_gpu { + qcom,dump-size = <0x300000>; + qcom,dump-id = <0x221>; + }; + }; + + cpuss_reg { + cpuss_reg { + qcom,dump-size = <0x36000>; + qcom,dump-id = <0xef>; + }; + }; + + spr { + spr_cpu0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f0>; + }; + + spr_cpu1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f1>; + }; + + spr_cpu2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f2>; + }; + + spr_cpu3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f3>; + }; + + spr_cpu4 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f4>; + }; + + spr_cpu5 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f5>; + }; + + spr_cpu6 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f6>; + }; + + spr_cpu7 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f7>; + }; + }; + }; + }; +}; + From 9d9da82a77d0934ff1b3ed6e06eee370ae304572 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Mon, 16 Sep 2024 14:20:05 +0530 Subject: [PATCH 14/67] ARM: dts: msm: Add necessary device nodes for Kera SoC Add IMEM, debug kinfo, qcom-ramoops, minidump, va-minidump nodes for Kera SoC. Change-Id: Ib5e4e5b4bd47bb3ba35450f27c4b38f49d362bfc Signed-off-by: Mukesh Ojha Signed-off-by: Souradeep Chowdhury --- qcom/kera.dtsi | 106 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index bd553f2e..39ea8ec3 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -232,6 +232,25 @@ size = <0x0 0x2000000>; linux,cma-default; }; + + kinfo_mem: debug_kinfo_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; + + va_md_mem: va_md_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x1000000>; + }; + + ramoops_mem: ramoops-region { + alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; + size = <0x0 0x200000>; + no-map; + }; }; &soc { @@ -632,6 +651,64 @@ interrupt-names = "smp2p-sleepstate-in"; }; + qcom,msm-imem@14680000 { + compatible = "qcom,msm-imem"; + reg = <0x14680000 0x1000>; + ranges = <0x0 0x14680000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + + modem_dsm@c98 { + compatible = "qcom,msm-imem-mss-dsm"; + reg = <0xc98 0x10>; + }; + + sys_dbg@af8 { + compatible = "qcom,msm-imem-gpu-dump-skip"; + reg = <0xb0c 0x4>; + }; + }; + eud: qcom,msm-eud@88e0000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; @@ -645,6 +722,35 @@ status = "ok"; }; + google,debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&kinfo_mem>; + }; + + mini_dump_mode { + compatible = "qcom,minidump"; + status = "ok"; + }; + + va_mini_dump { + compatible = "qcom,va-minidump"; + memory-region = <&va_md_mem>; + status = "ok"; + }; + + qcom_ramoops { + compatible = "qcom,ramoops"; + memory-region = <&ramoops_mem>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + qcom,msm-adsprpc-mem { compatible = "qcom,msm-adsprpc-mem-region"; memory-region = <&adsp_mem_heap>; From 6c403cade8dbd71dffcce1a2b103ca96175c5ec8 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Mon, 16 Sep 2024 17:20:19 +0530 Subject: [PATCH 15/67] ARM: dts: msm: Enable PMU on Kera Add dt node for PMU on kera SoC. Change-Id: Iffc910eead033b8d15881aeb14fc1aa71299aae3 Signed-off-by: Souradeep Chowdhury --- qcom/kera.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index bd553f2e..53f3aff9 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -624,6 +624,11 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + qcom,smp2p_sleepstate { compatible = "qcom,smp2p-sleepstate"; qcom,smem-states = <&sleepstate_smp2p_out 0>; From 26aa19bfd03f3b930c492b10e53c04259a48e6d2 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Thu, 19 Sep 2024 12:37:25 +0530 Subject: [PATCH 16/67] ARM: dts: msm: Add reserve GPIOs in Tuna TLMM node Add list of GPIOs reserved for CXM UART1(82,83), CXM UART2(111,112) and QUP 1 SE 1(4,5,6,7). Change-Id: I06ad98537aa01ab812a9cd311ec3156074af7247 Signed-off-by: Souradeep Chowdhury --- qcom/tuna.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 1bfe94a4..ac2fc1d1 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -718,7 +718,7 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; - qcom,gpios-reserved = <54>; + qcom,gpios-reserved = <54 4 5 6 7 82 83 111 112>; }; tcsr_mutex_block: syscon@1f40000 { From a3c7be7f79de8fdb8bc4476cee7c3e474dd68126 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Thu, 12 Sep 2024 11:43:14 +0530 Subject: [PATCH 17/67] ARM: dts: msm: Update root and init mount points Update root and init mount points for parrot. Change-Id: I942794c6bcb929cd0d6c2f784341fcbba694e9a9 Signed-off-by: Swetha Chikkaboraiah --- qcom/waipio-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi index 7e9220d5..e233f4db 100644 --- a/qcom/waipio-vm.dtsi +++ b/qcom/waipio-vm.dtsi @@ -23,7 +23,7 @@ }; chosen { - bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable root=/dev/ram rw init=/init"; + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable root=/dev/vda init=/sbin/init"; }; cpus { From 60c016bb2f8e6770c9d0478cb1edfe17d3362960 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Thu, 19 Sep 2024 16:19:22 +0530 Subject: [PATCH 18/67] ARM: dts: msm: Add reserve GPIOs in Kera TLMM node Add list of GPIOs reserved for QUP 2 SE 6(20,21,22,23), CXM UART1(111,112) and CXM UART2(110,116). Change-Id: If501f5da5f732c5270438066525389001d345321 Signed-off-by: Souradeep Chowdhury --- qcom/kera.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index bd553f2e..b1d09dc3 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -403,6 +403,7 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qcom,gpios-reserved = <20 21 22 23 100 111 112 116>; }; tcsr_mutex_block: syscon@1f40000 { From 242ce39759ab096fcf5c99a9c884346f4cedb114 Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Thu, 19 Sep 2024 18:35:03 +0530 Subject: [PATCH 19/67] dt-bindings: clock: qcom: add DEBUGCC bindings on tuna Add debug clock controller bindings on tuna device. Change-Id: I60a1a4c41d59591127b38e88e46e531cbc0a79dc Signed-off-by: Ajit Pandey --- bindings/clock/qcom,debugcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index abdaa90e..1a7c7670 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -22,6 +22,7 @@ properties: - qcom,sdx75-debugcc - qcom,sm4450-debugcc - qcom,monaco-debugcc + - qcom,tuna-debugcc clocks: items: From d080de7f290e48313e161b3ae811a59a476cd307 Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Tue, 17 Sep 2024 14:27:04 +0530 Subject: [PATCH 20/67] dt-bindings: clock: qcom: add CAMCC bindings on kera Add camera clock controller bindings on kera device. Change-Id: Iba3b84e9ef3e4260388817c29d90c8c942e252aa Signed-off-by: Ajit Pandey --- bindings/clock/qcom,camcc-sun.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,camcc-sun.yaml b/bindings/clock/qcom,camcc-sun.yaml index 40d1b15d..fa8156bb 100644 --- a/bindings/clock/qcom,camcc-sun.yaml +++ b/bindings/clock/qcom,camcc-sun.yaml @@ -21,6 +21,7 @@ properties: enum: - qcom,sun-camcc - qcom,tuna-camcc + - qcom,kera-camcc clocks: items: From fb5ce2b78a523a7b5847b66588443874f77d908f Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Tue, 6 Aug 2024 16:22:24 +0530 Subject: [PATCH 21/67] ARM: dts: msm: Add support for display clock controller on TUNA Add support for display clock controller and move correspondin gdsc's from dummy to real on Tuna platform. Change-Id: I3949ba5bc798d5a62d891c151115bd616004a466 Signed-off-by: Anaadi Mishra --- qcom/tuna.dtsi | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index b7a1524e..acaa6248 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1103,9 +1103,26 @@ #reset-cells = <1>; }; + dispcc_crm: syscon@af27800 { + compatible = "syscon"; + reg = <0xaf27800 0x2000>; + }; + dispcc: clock-controller@af00000 { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + compatible = "qcom,tuna-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; + qcom,dispcc_crm-crmc = <&dispcc_crm>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1719,12 +1736,14 @@ }; &disp_cc_mdss_core_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; status = "ok"; }; From 2ade629af307929ce96719ec8cd35748f2133803 Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Thu, 19 Sep 2024 21:14:12 +0530 Subject: [PATCH 22/67] ARM: dts: msm: Add support for DEBUGCC on Tuna platform Add support for debug clock controller nodes on Tuna platform. While at it add stubs clock support nodes for gxclkctl. Change-Id: I80e490feaaf9577a099990bda57fe660e8009222 Signed-off-by: Ajit Pandey --- qcom/tuna.dtsi | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 07467382..e6b5ad06 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1195,6 +1195,13 @@ #reset-cells = <1>; }; + gxclkctl: clock-controller@3d68024 { + compatible = "qcom,dummycc"; + clock-output-names = "gxclkctl_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + tcsrcc: clock-controller@1fbf000 { compatible = "qcom,tuna-tcsrcc", "syscon"; reg = <0x1fbf000 0x14>; @@ -1221,6 +1228,46 @@ #reset-cells = <1>; }; + apsscc: syscon@17a80000 { + compatible = "syscon"; + reg = <0x17a80000 0x31000>; + }; + + mccc: syscon@240ba000 { + compatible = "syscon"; + reg = <0x240ba000 0x54>; + }; + + gxclkctldebugcc: syscon@3d64000 { + compatible = "syscon"; + reg = <0x3d64000 0x6000>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,tuna-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,cambistmclkcc = <&cambistmclkcc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,evacc = <&evacc>; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,gxclkctl = <&gxclkctldebugcc>; + qcom,videocc = <&videocc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&cambistmclkcc 0>, + <&camcc 0>, <&dispcc 0>, + <&evacc 0>, <&gcc 0>, + <&gpucc 0>, <&gxclkctl 0>, + <&videocc 0>; + clock-names = "xo_clk_src", "cambistmclkcc", + "camcc", "dispcc", + "evacc", "gcc", + "gpucc", "gxclkctl", + "videocc"; + #clock-cells = <1>; + }; + tcsr: syscon@1fc0000 { compatible = "syscon"; reg = <0x1fc0000 0x30000>; From 627807ed09f5631cf892550e004ba0a1ea2b76cd Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Thu, 19 Sep 2024 22:03:52 +0530 Subject: [PATCH 23/67] ARM: dts: msm: Update msgq-names for mem-buf-msgq node Update msgq-names for mem-buf-msgq node for waipio vm. Change-Id: Iae6080718d78c3be34ebd7fc158e906ab6109226 Signed-off-by: Swetha Chikkaboraiah --- qcom/waipio-vm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi index 7e9220d5..0f78e69f 100644 --- a/qcom/waipio-vm.dtsi +++ b/qcom/waipio-vm.dtsi @@ -20,6 +20,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; }; chosen { From ed4772646db3792d2d110f9fd91db467b35fbaf9 Mon Sep 17 00:00:00 2001 From: Ankur Bansal Date: Wed, 4 Sep 2024 20:00:20 +0530 Subject: [PATCH 24/67] ARM: dts: msm: update dcc sram offset for Sun update dcc sram offset for Sun. Change-Id: I36065724df8429428a6a613ffb187b4b84b04940 Signed-off-by: Ankur Bansal --- qcom/sun-debug.dtsi | 1889 +------------------------------------------ 1 file changed, 2 insertions(+), 1887 deletions(-) diff --git a/qcom/sun-debug.dtsi b/qcom/sun-debug.dtsi index e47d5f8d..6123612a 100644 --- a/qcom/sun-debug.dtsi +++ b/qcom/sun-debug.dtsi @@ -20,1897 +20,12 @@ dcc: dcc@100ff000 { compatible = "qcom,dcc-v2"; reg = <0x100ff000 0x1000>, - <0x10080800 0x7800>; + <0x10084000 0x4000>; reg-names = "dcc-base", "dcc-ram-base"; qcom,transaction_timeout = <0x80>; - dcc-ram-offset = <0x800>; + dcc-ram-offset = <0x4000>; - link_list_0 { - qcom,curr-link-list = <6>; - qcom,data-sink = "sram"; - qcom,ap-qad-override; - qcom,link-list = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - 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, - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - link_list_1 { - qcom,curr-link-list = <4>; - qcom,data-sink = "sram"; - qcom,ap-qad-override; - qcom,link-list = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; }; mem_dump { From b132c01ab87bfcd8ed53ebf8018603f374519aba Mon Sep 17 00:00:00 2001 From: songchai Date: Wed, 18 Sep 2024 18:01:08 +0800 Subject: [PATCH 25/67] ARM: dts: msm: Add coresight components for tuna Add coresight components to enable TMC/STM/CTI/TPDM/ETM functions. Change-Id: I5a3a11041f03660376fe709366ffb71fcbc694e6 Signed-off-by: songchai --- qcom/tuna-coresight.dtsi | 4833 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 4833 insertions(+) create mode 100644 qcom/tuna-coresight.dtsi diff --git a/qcom/tuna-coresight.dtsi b/qcom/tuna-coresight.dtsi new file mode 100644 index 00000000..a43b3421 --- /dev/null +++ b/qcom/tuna-coresight.dtsi @@ -0,0 +1,4833 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + ipcb_tgu: tgu@10b0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + reg = <0x10b0e000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu0: tgu@10b0f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b0f000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu1: tgu@10b10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b10000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + csr: csr@10001000 { + compatible = "qcom,coresight-csr"; + reg = <0x10001000 0x1000>; + reg-names = "csr-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + coresight-name = "coresight-csr"; + + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + qcom,blk-size = <1>; + }; + + swao_csr: csr@10b11000 { + compatible = "qcom,coresight-csr"; + reg = <0x10b11000 0x1000>, + <0x10b110f8 0x78>; + reg-names = "csr-base", "msr-base"; + + coresight-name = "coresight-swao-csr"; + + qcom,timestamp-support; + qcom,msr-support; + qcom,blk-size = <1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm_gfx: tpdm@10900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10900000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_gfx_out_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_in_tpdm_gfx>; + }; + }; + }; + }; + + + funnel_gfx: funnel@10963000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10963000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + funnel_gfx_out_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_in_funnel_gfx>; + }; + }; + }; + }; + + funnel_gfx_dl: funnel@10902000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10902000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx_dl"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_dl_in_tpdm_gfx: endpoint { + remote-endpoint = + <&tpdm_gfx_out_funnel_gfx_dl>; + }; + }; + + port@1 { + reg = <1>; + funnel_gfx_dl_in_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_out_funnel_gfx_dl>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_dl_out_tpda_dl3: endpoint { + remote-endpoint = + <&tpda_dl3_in_funnel_gfx_dl>; + source = <&tpdm_gfx>; + }; + }; + + port@1 { + reg = <1>; + funnel_gfx_dl_out_funnel_dl3: endpoint { + remote-endpoint = + <&funnel_dl3_in_funnel_gfx_dl>; + }; + }; + }; + }; + + tpdm_dl3: tpdm@10c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10C28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_dl3_out_tpda_dl3: endpoint { + remote-endpoint = + <&tpda_dl3_in_tpdm_dl3>; + }; + }; + }; + }; + + tpda_dl3: tpda@10c2c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10c2c000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-dl3"; + + qcom,dsb-elem-size = <0 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl3_in_funnel_video: endpoint { + remote-endpoint = + <&funnel_video_out_tpda_dl3>; + }; + }; + + port@2 { + reg = <2>; + tpda_dl3_in_funnel_eva: endpoint { + remote-endpoint = + <&funnel_eva_out_tpda_dl3>; + }; + }; + + port@b { + reg = <11>; + tpda_dl3_in_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_out_tpda_dl3>; + }; + }; + + port@1b { + reg = <27>; + tpda_dl3_in_tpdm_dl3: endpoint { + remote-endpoint = + <&tpdm_dl3_out_tpda_dl3>; + }; + }; + }; + + out-ports { + port { + tpda_dl3_out_funnel_dl3: endpoint { + remote-endpoint = + <&funnel_dl3_in_tpda_dl3>; + }; + }; + }; + }; + + funnel_dl3: funnel@10c2d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10c2d000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl3_in_tpda_dl3: endpoint { + remote-endpoint = + <&tpda_dl3_out_funnel_dl3>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl3_in_funnel_video: endpoint { + remote-endpoint = + <&funnel_video_out_funnel_dl3>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl3_in_funnel_eva: endpoint { + remote-endpoint = + <&funnel_eva_out_funnel_dl3>; + }; + }; + + port@5 { + reg = <5>; + funnel_dl3_in_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_out_funnel_dl3>; + }; + }; + }; + + out-ports { + port { + funnel_dl3_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_funnel_dl3>; + }; + }; + }; + }; + + tpdm_video: tpdm@10830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-video"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_video_out_funnel_video: endpoint { + remote-endpoint = + <&funnel_video_in_tpdm_video>; + }; + }; + }; + }; + + funnel_video: funnel@10832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10832000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-video"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_video_in_tpdm_video: endpoint { + remote-endpoint = + <&tpdm_video_out_funnel_video>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_video_out_tpda_dl3: endpoint { + remote-endpoint = + <&tpda_dl3_in_funnel_video>; + }; + }; + + port@1 { + reg = <1>; + funnel_video_out_funnel_dl3: endpoint { + remote-endpoint = + <&funnel_dl3_in_funnel_video>; + }; + }; + }; + }; + + tpdm_eva: tpdm@109c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-eva"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_eva_out_funnel_eva: endpoint { + remote-endpoint = + <&funnel_eva_in_tpdm_eva>; + }; + }; + }; + }; + + funnel_eva: funnel@109c2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x109c2000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-eva"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_eva_in_tpdm_eva: endpoint { + remote-endpoint = + <&tpdm_eva_out_funnel_eva>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_eva_out_tpda_dl3: endpoint { + remote-endpoint = + <&tpda_dl3_in_funnel_eva>; + }; + }; + + port@1 { + reg = <1>; + funnel_eva_out_funnel_dl3: endpoint { + remote-endpoint = + <&funnel_dl3_in_funnel_eva>; + }; + }; + }; + }; + + tpdm_mdss: tpdm@10c60000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c60000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_mdss_out_funnel_mdss: endpoint { + remote-endpoint = + <&funnel_mdss_in_tpdm_mdss>; + }; + }; + }; + }; + + tpdm_mdss_rscc: tpdm@10c61000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c61000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mdss-rscc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_mdss_rscc_out_funnel_mdss: endpoint { + remote-endpoint = + <&funnel_mdss_in_tpdm_mdss_rscc>; + }; + }; + }; + }; + + funnel_mdss: funnel@10c63000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10c63000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-mdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_mdss_in_tpdm_mdss: endpoint { + remote-endpoint = + <&tpdm_mdss_out_funnel_mdss>; + }; + }; + + port@1 { + reg = <1>; + funnel_mdss_in_tpdm_mdss_rscc: endpoint { + remote-endpoint = + <&tpdm_mdss_rscc_out_funnel_mdss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_mdss_out_tpda_dl5: endpoint { + remote-endpoint = + <&tpda_dl5_in_funnel_mdss>; + }; + }; + }; + }; + + tpda_dl5: tpda@10c08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10c08000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-dl5"; + + qcom,cmb-elem-size = <0 32>, + <1 32>, + <2 32>, + <3 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl5_in_funnel_mdss: endpoint { + remote-endpoint = + <&funnel_mdss_out_tpda_dl5>; + }; + }; + }; + + out-ports { + port { + tpda_dl5_out_funnel_dl5: endpoint { + remote-endpoint = + <&funnel_dl5_in_tpda_dl5>; + }; + }; + }; + }; + + funnel_dl5: funnel@10c09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10c09000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl5"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl5_in_tpda_dl5: endpoint { + remote-endpoint = + <&tpda_dl5_out_funnel_dl5>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl5_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_funnel_dl5>; + }; + }; + }; + }; + + tpdm_soccp: tpdm@10ba4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10ba4000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-soccp"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_soccp_out_tn_soccp: endpoint { + remote-endpoint = + <&tn_soccp_in_tpdm_soccp>; + }; + }; + }; + }; + + tn_soccp: traceNoc@10ba0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000f0c00>; + reg = <0x10ba0000 0x1000>; + reg-names = "traceNoc-base"; + + coresight-name = "coresight-tracenoc-soccp"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,interconnect-trace-noc; + + in-ports { + port { + tn_soccp_in_tpdm_soccp: endpoint { + remote-endpoint = + <&tpdm_soccp_out_tn_soccp>; + }; + }; + }; + + out-ports { + port { + tn_soccp_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tn_soccp>; + }; + }; + }; + }; + + tpdm_turing: tpdm@10980000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10980000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + }; + + tpdm_turing_llm: tpdm@10981000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10980000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_turing_llm_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing_llm>; + }; + }; + }; + }; + + funnel_turing: funnel@10983000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10983000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_in_tpdm_turing_llm: endpoint { + remote-endpoint = + <&tpdm_turing_llm_out_funnel_turing>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_out_tpda_dl4_16: endpoint { + remote-endpoint = + <&tpda_dl4_16_in_funnel_turing>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_out_tpda_dl4_17: endpoint { + remote-endpoint = + <&tpda_dl4_17_in_funnel_turing>; + }; + }; + + port@2 { + reg = <2>; + funnel_turing_out_funnel_dl4: endpoint { + remote-endpoint = + <&funnel_dl4_in_funnel_turing>; + }; + }; + }; + }; + + tpda_dl4: tpda@10c14000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10c14000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-dl4"; + + qcom,cmb-elem-size = <0 32>, + <1 32>, + <2 32>, + <3 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@10 { + reg = <16>; + tpda_dl4_16_in_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_out_tpda_dl4_16>; + }; + }; + + port@11 { + reg = <17>; + tpda_dl4_17_in_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_out_tpda_dl4_17>; + }; + }; + }; + + out-ports { + port { + tpda_dl4_out_funnel_dl4: endpoint { + remote-endpoint = + <&funnel_dl4_in_tpda_dl4>; + }; + }; + }; + }; + + funnel_dl4: funnel@10c15000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10c15000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl4"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl4_in_tpda_dl4: endpoint { + remote-endpoint = + <&tpda_dl4_out_funnel_dl4>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl4_in_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_out_funnel_dl4>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl4_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_funnel_dl4>; + }; + }; + }; + }; + + tpdm_modem0: tpdm@10800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10800000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_modem0_out_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_in_tpdm_modem0>; + }; + }; + }; + }; + + tpdm_modem1: tpdm@10801000 { + compatible = "qcom,coresight-static-tpdm"; + + coresight-name = "coresight-tpdm-modem-1"; + + out-ports { + port { + tpdm_modem1_out_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_in_tpdm_modem1>; + }; + }; + }; + }; + + tpdm_modem_rscc: tpdm@1080d000 { + compatible = "qcom,coresight-static-tpdm"; + + coresight-name = "coresight-tpdm-modem-rscc"; + + out-ports { + port { + tpdm_modem_rscc_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_tpdm_modem_rscc>; + }; + }; + }; + }; + + modem-etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,atid-num = <2>; + atid = <36 37>; + trace-name = "modem-etm0"; + qcom,secure-component; + + out-ports { + port@0 { + reg = <0>; + modem_etm0_out_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_in_modem_etm0>; + }; + }; + + port@1 { + reg = <1>; + modem_etm0_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_modem_etm0>; + }; + }; + }; + }; + + modem2-etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem2-etm0"; + qcom,atid-num = <1>; + atid = <39>; + trace-name = "modem2-etm0"; + + out-ports { + port@0 { + reg = <0>; + modem2_etm0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_modem2_etm0>; + }; + }; + + port@1 { + reg = <1>; + modem2_etm0_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_modem2_etm0>; + }; + }; + }; + }; + + modem_diag: modem_diag { + compatible = "arm,coresight-dummy-source"; + + coresight-name = "coresight-modem-diag"; + atid = <50>; + + out-ports { + port { + modem_diag_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_modem_diag>; + }; + }; + }; + }; + + tpda_modem: tpda@10803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10803000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem"; + + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_modem_in_tpdm_modem0: endpoint { + remote-endpoint = + <&tpdm_modem0_out_tpda_modem>; + }; + }; + + port@1 { + reg = <1>; + tpda_modem_in_tpdm_modem1: endpoint { + remote-endpoint = + <&tpdm_modem1_out_tpda_modem>; + }; + }; + }; + + out-ports { + port { + tpda_modem_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_tpda_modem>; + }; + }; + }; + }; + + funnel_modem_q6_dup: funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x1080d000 0x1000>, + <0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-modem_q6_dup"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_q6_dup_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_modem_q6_dup>; + }; + }; + }; + + out-ports { + port { + funnel_modem_q6_dup_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_funnel_modem_q6_dup>; + }; + }; + }; + }; + + funnel_modem_q6: funnel@1080c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x1080c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem_q6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_modem_q6_in_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_out_funnel_modem_q6>; + }; + }; + + port@2 { + reg = <2>; + funnel_modem_q6_in_modem_diag: endpoint { + remote-endpoint = + <&modem_diag_out_funnel_modem_q6>; + }; + }; + + port@3 { + funnel_modem_q6_in_tpdm_modem_rscc: endpoint { + remote-endpoint = + <&tpdm_modem_rscc_out_funnel_modem_q6>; + }; + }; + + }; + + out-ports { + + port { + funnel_modem_q6_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_funnel_modem_q6>; + }; + }; + }; + }; + + funnel_modem_dl: funnel@10804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem_dl"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_dl_in_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_out_funnel_modem_dl>; + }; + }; + + port@1 { + reg = <1>; + funnel_modem_in_modem2_etm0: endpoint { + remote-endpoint = + <&modem2_etm0_out_funnel_modem>; + }; + }; + + port@3 { + reg = <3>; + funnel_modem_dl_in_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_out_funnel_modem_dl>; + }; + }; + }; + + out-ports { + + port { + funnel_modem_dl_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_funnel_modem_dl>; + }; + }; + }; + }; + + tpdm_tmess_prng: tpdm@10cc9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc9000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-tmess-prng"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_prng_out_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_in_tpdm_tmess_prng>; + }; + }; + }; + }; + + tpdm_tmess0: tpdm@10cc0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-tmess-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,hw-enable-check; + status = "disabled"; + + out-ports { + port { + tpdm_tmess0_out_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_in_tpdm_tmess0>; + }; + }; + }; + }; + + tpdm_tmess1: tpdm@10cc1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc1000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-tmess-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,hw-enable-check; + + out-ports { + port { + tpdm_tmess1_out_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_in_tpdm_tmess1>; + }; + }; + }; + }; + + tpda_tmess: tpda@10cc4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10cc4000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-tmess"; + + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 32>, + <1 32>, + <2 64>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_tmess_in_tpdm_tmess_prng: endpoint { + remote-endpoint = + <&tpdm_tmess_prng_out_tpda_tmess>; + }; + }; + + port@1 { + reg = <1>; + tpda_tmess_in_tpdm_tmess0: endpoint { + remote-endpoint = + <&tpdm_tmess0_out_tpda_tmess>; + }; + }; + + port@2 { + reg = <2>; + tpda_tmess_in_tpdm_tmess1: endpoint { + remote-endpoint = + <&tpdm_tmess1_out_tpda_tmess>; + }; + }; + }; + + out-ports { + port { + tpda_tmess_out_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_in_tpda_tmess>; + }; + }; + }; + }; + + funnel_tmess: funnel@10cc5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10cc5000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-tmess"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_tmess_in_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_out_funnel_tmess>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_tmess_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_funnel_tmess>; + }; + }; + }; + }; + + tpdm_titan: tpdm@10a04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10a04000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-titan-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + static = "disabled"; + + out-ports { + port { + tpdm_titan_dsb_out_tn_titan: endpoint { + remote-endpoint = + <&tn_titan_in_tpdm_titan_dsb>; + }; + }; + }; + }; + + tpdm_titan_rscc: tpdm@10a0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10a0e000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-titan-rscc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_titan_rscc_out_tpda_titan: endpoint { + remote-endpoint = + <&tpda_titan_in_tpdm_titan_rscc>; + }; + }; + }; + }; + + tpda_titan: tpda@10a0f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10a0f000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-titan"; + + qcom,cmb-elem-size = <0 64>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_titan_in_tpdm_titan_rscc: endpoint { + remote-endpoint = + <&tpdm_titan_rscc_out_tpda_titan>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_titan_out_tn_titan: endpoint { + remote-endpoint = + <&tn_titan_in_tpda_titan>; + }; + }; + }; + }; + + tn_titan: tn@10a00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000f0c00>; + reg = <0x10a00000 0x1000>; + reg-names = "traceNoc-base"; + + coresight-name = "coresight-tracenoc-titan"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,trace-noc-v2; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + tn_titan_in_tpda_titan: endpoint { + remote-endpoint = + <&tpda_titan_out_tn_titan>; + }; + }; + + port@5 { + reg = <5>; + tn_titan_in_tpdm_titan_dsb: endpoint { + remote-endpoint = + <&tpdm_titan_dsb_out_tn_titan>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tn_titan_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tn_titan>; + }; + }; + }; + }; + + tpdm_rscc: tpdm@10c70000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c70000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pcie-rscc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_rscc_out_tpda_rscc: endpoint { + remote-endpoint = + <&tpda_rscc_in_tpdm_rscc>; + }; + }; + }; + }; + + tpda_pcie_rscc: tpda@10c71000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10c71000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-pcie-rscc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-elem-size = <0 8>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_rscc_in_tpdm_rscc: endpoint { + remote-endpoint = + <&tpdm_rscc_out_tpda_rscc>; + }; + }; + }; + + out-ports { + port { + tpda_pcie_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpda_pcie>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@138a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x138a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_llm_silver_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_silver>; + }; + }; + }; + }; + + tpdm_llm_gold: tpdm@138b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x138b0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-gold"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_llm_gold_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_gold>; + }; + }; + }; + }; + + tpdm_llm_ext: tpdm@138c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x138c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-ext"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_llm_ext_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_ext>; + }; + }; + }; + }; + + tpdm_llm_apc2: tpdm@13880000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13880000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-apc2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_llm_apc2_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_apc2>; + }; + }; + }; + }; + + tpdm_apc2: tpdm@13890000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13890000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apc2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_apc2_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apc2>; + }; + }; + }; + }; + + tpdm_int_cmb0:tpdm@13860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-int-cmb0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_int_cmb0_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_int_cmb0>; + }; + }; + }; + }; + + tpdm_int_cmb1:tpdm@13861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13861000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-int-cmb1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_int_cmb1_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_int_cmb1>; + }; + }; + }; + }; + + tpdm_int_dsb: tpdm@13862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13862000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-int-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_int_dsb_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_int_dsb>; + }; + }; + }; + }; + + ete0 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU0>; + + coresight-name = "coresight-ete0"; + qcom,skip-power-up; + atid = <1>; + out-ports { + port { + ete0_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete0>; + }; + }; + }; + }; + + ete1 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU1>; + + coresight-name = "coresight-ete1"; + qcom,skip-power-up; + atid = <2>; + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + ete2 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU2>; + + coresight-name = "coresight-ete2"; + qcom,skip-power-up; + atid = <3>; + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + ete3 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU3>; + + coresight-name = "coresight-ete3"; + qcom,skip-power-up; + atid = <4>; + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + ete4 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU4>; + + coresight-name = "coresight-ete4"; + qcom,skip-power-up; + atid = <5>; + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + ete5 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU5>; + + coresight-name = "coresight-ete5"; + qcom,skip-power-up; + atid = <6>; + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + ete6 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU6>; + + coresight-name = "coresight-ete6"; + qcom,skip-power-up; + atid = <7>; + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + ete7 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU7>; + + coresight-name = "coresight-ete7"; + qcom,skip-power-up; + atid = <8>; + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete7>; + }; + }; + }; + }; + + funnel_ete { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-ete"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ete_in_ete0: endpoint { + remote-endpoint = + <&ete0_out_funnel_ete>; + }; + }; + + port@1 { + reg = <1>; + funnel_ete_in_ete1: endpoint { + remote-endpoint = + <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg = <2>; + funnel_ete_in_ete2: endpoint { + remote-endpoint = + <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg = <3>; + funnel_ete_in_ete3: endpoint { + remote-endpoint = + <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg = <4>; + funnel_ete_in_ete4: endpoint { + remote-endpoint = + <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg = <5>; + funnel_ete_in_ete5: endpoint { + remote-endpoint = + <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg = <6>; + funnel_ete_in_ete6: endpoint { + remote-endpoint = + <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg = <7>; + funnel_ete_in_ete7: endpoint { + remote-endpoint = + <&ete7_out_funnel_ete>; + }; + }; + }; + + out-ports { + port { + funnel_ete_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_funnel_ete>; + }; + }; + }; + + }; + + tpda_apss: tpda@13864000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x13864000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,cmb-elem-size = <0 32>, + <1 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_apss_in_tpdm_llm_silver: endpoint { + remote-endpoint = + <&tpdm_llm_silver_out_tpda_apss>; + }; + }; + + port@1 { + reg = <1>; + tpda_apss_in_tpdm_llm_gold: endpoint { + remote-endpoint = + <&tpdm_llm_gold_out_tpda_apss>; + }; + }; + + port@2 { + reg = <2>; + tpda_apss_in_tpdm_llm_ext: endpoint { + remote-endpoint = + <&tpdm_llm_ext_out_tpda_apss>; + }; + }; + + port@3 { + reg = <3>; + tpda_apss_in_tpdm_llm_apc2: endpoint { + remote-endpoint = + <&tpdm_llm_apc2_out_tpda_apss>; + }; + }; + + port@5 { + reg = <5>; + tpda_apss_in_tpdm_apc2: endpoint { + remote-endpoint = + <&tpdm_apc2_out_tpda_apss>; + }; + }; + + port@6 { + reg = <6>; + tpda_apss_in_tpdm_int_cmb0: endpoint { + remote-endpoint = + <&tpdm_int_cmb0_out_tpda_apss>; + }; + }; + + port@7 { + reg = <7>; + tpda_apss_in_tpdm_int_cmb1: endpoint { + remote-endpoint = + <&tpdm_int_cmb1_out_tpda_apss>; + }; + }; + + port@8 { + reg = <8>; + tpda_apss_in_tpdm_int_dsb: endpoint { + remote-endpoint = + <&tpdm_int_dsb_out_tpda_apss>; + }; + }; + + }; + + out-ports { + port { + tpda_apss_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_tpda_apss>; + }; + }; + }; + }; + + funnel_apss: funnel@13810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x13810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_in_funnel_ete: endpoint { + remote-endpoint = + <&funnel_ete_out_funnel_apss>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_in_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_out_funnel_apss>; + }; + }; + }; + + out-ports { + port { + funnel_apss_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_funnel_apss>; + }; + }; + }; + }; + + tpdm_ddr_lpi: tpdm@10b34000 { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-tpdm-ddr-lpi"; + trace-name = "tracenoc-ddr-lpi"; + + out-ports { + port { + tpdm_ddr_lpi_out_tn_ddr_lpi: endpoint { + remote-endpoint = + <&tn_ddr_lpi_in_tpdm_ddr_lpi>; + }; + }; + }; + }; + + tn_ddr_lpi: TN@10b30000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000f0c00>; + reg = <0x10d00000 0x1000>; + reg-names = "traceNoc-base"; + + coresight-name = "coresight-tracenoc-ddr-lpi"; + qcom,interconnect-trace-noc; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tn_ddr_lpi_in_tpdm_ddr_lpi: endpoint { + remote-endpoint = + <&tpdm_ddr_lpi_out_tn_ddr_lpi>; + }; + }; + + + }; + + out-ports { + port { + tn_ddr_lpi_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_tn_ddr_lpi>; + }; + }; + }; + }; + + tpdm_ddr_llcc0: tpdm@10f82000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10f82000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-llcc0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_llcc0_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_tpdm_ddr_llcc0>; + }; + }; + }; + }; + + tpdm_ddr_llcc1: tpdm@10f84000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10f84000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-llcc1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_llcc1_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_tpdm_ddr_llcc1>; + }; + }; + }; + }; + + tpdm_ddr_llcc2: tpdm@10f83000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10f83000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-llcc2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_llcc2_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_tpdm_ddr_llcc2>; + }; + }; + }; + }; + + tpdm_ddr_llcc3: tpdm@10f85000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10f85000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-llcc3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_llcc3_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_tpdm_ddr_llcc3>; + }; + }; + }; + }; + + tpdm_ddr_dpm: tpdm@10d04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d04000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-dpm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_ddr_dpm_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_tpdm_ddr_dpm>; + }; + }; + }; + }; + + tpdm_ddr_shrm: tpdm@10d03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d03000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-shrm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_ddr_shrm_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_tpdm_ddr_shrm>; + }; + }; + }; + }; + + tpdm_ddr_ch02: tpdm@10d06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d06000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-ch02"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_ch02_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_tpdm_ddr_ch02>; + }; + }; + }; + }; + + tpdm_ddr_ch13: tpdm@10d08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d08000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-ch13"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_ch13_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_tpdm_ddr_ch13>; + }; + }; + }; + }; + + gladiator { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-gladiator"; + atid = <96>; + + out-ports { + port { + gladiator_out_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_in_gladiator>; + }; + }; + }; + }; + + ddr_tn: TN@10d00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000f0c00>; + reg = <0x10d00000 0x1000>; + reg-names = "traceNoc-base"; + + coresight-name = "coresight-tracenoc-ddr"; + qcom,interconnect-trace-noc; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + tn_ddr_in_gladiator: endpoint { + remote-endpoint = + <&gladiator_out_tn_ddr>; + }; + }; + + port@9 { + reg = <9>; + tn_ddr_in_tpdm_ddr_llcc0: endpoint { + remote-endpoint = + <&tpdm_ddr_llcc0_out_tn_ddr>; + }; + }; + + port@a { + reg = <10>; + tn_ddr_in_tpdm_ddr_llcc1: endpoint { + remote-endpoint = + <&tpdm_ddr_llcc1_out_tn_ddr>; + }; + }; + + port@b { + reg = <11>; + tn_ddr_in_tpdm_ddr_llcc2: endpoint { + remote-endpoint = + <&tpdm_ddr_llcc2_out_tn_ddr>; + }; + }; + + port@c { + reg = <12>; + tn_ddr_in_tpdm_ddr_llcc3: endpoint { + remote-endpoint = + <&tpdm_ddr_llcc3_out_tn_ddr>; + }; + }; + + port@d { + reg = <13>; + tn_ddr_in_tpdm_ddr_shrm: endpoint { + remote-endpoint = + <&tpdm_ddr_shrm_out_tn_ddr>; + }; + }; + + port@e { + reg = <14>; + tn_ddr_in_tpdm_ddr_dpm: endpoint { + remote-endpoint = + <&tpdm_ddr_dpm_out_tn_ddr>; + }; + }; + + port@f { + reg = <15>; + tn_ddr_in_tpdm_ddr_ch02: endpoint { + remote-endpoint = + <&tpdm_ddr_ch02_out_tn_ddr>; + }; + }; + + port@10 { + reg = <16>; + tn_ddr_in_tpdm_ddr_ch13: endpoint { + remote-endpoint = + <&tpdm_ddr_ch13_out_tn_ddr>; + }; + }; + }; + + out-ports { + port { + tn_ddr_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tn_ddr>; + }; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,atid-num = <2>; + trace-name = "audio-etm0"; + atid = <40 41>; + + out-ports { + port@0 { + reg = <0>; + audio_etm0_out_funnel_lpass_lpi_0: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_0_in_audio_etm0>; + }; + }; + + port@1 { + reg = <1>; + audio_etm0_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_audio_etm0>; + }; + }; + }; + }; + + tpdm_lpass_lpi: tpdm@10b46000 { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-tpdm-lpass-lpi"; + + trace-name = "tpda-lpass-lpi"; + + out-ports { + port@0 { + reg = <0>; + tpdm_lpass_lpi_out_funnel_lpass_lpi_1: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_1_in_tpdm_lpass_lpi>; + }; + }; + + port@1 { + reg = <1>; + lpass_lpi_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_lpass_lpi>; + }; + }; + }; + }; + + tpdm_lpass_rscc: tpdm@10b52000 { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-tpdm-lpass-rscc"; + + trace-name = "tpda-lpass-rscc"; + + out-ports { + port@0 { + reg = <0>; + tpdm_lpass_rscc_out_funnel_lpass_lpi_1: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_1_in_tpdm_lpass_rscc>; + }; + }; + + port@1 { + reg = <1>; + lpass_rscc_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_lpass_rscc>; + }; + }; + }; + }; + + tpdm_lpass_audio: tpdm@10b54000 { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-tpdm-lpass-audio"; + + trace-name = "tpda-lpass-audio"; + status = "disabled"; + + out-ports { + port@0 { + reg = <0>; + tpdm_lpass_audio_out_funnel_lpass_lpi_1: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_1_in_tpdm_lpass_audio>; + }; + }; + + port@1 { + reg = <1>; + lpass_audio_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_lpass_audio>; + }; + }; + }; + }; + + tpdm_lpass_crdl: tpdm@10b84000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x108b4000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-lpass-crdl"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_lpass_crdl_out_tn_lpass: endpoint { + remote-endpoint = + <&tn_lpass_in_tpdm_lpass_crdl>; + }; + }; + }; + }; + + tn_lpass: TN@10b80000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000f0c00>; + reg = <0x10b80000 0x3400>; + reg-names = "traceNoc-base"; + + coresight-name = "coresight-tracenoc-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,interconnect-trace-noc; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tn_lpass_in_tpdm_lpass_crdl: endpoint { + remote-endpoint = + <&tpdm_lpass_crdl_out_tn_lpass>; + }; + }; + }; + + out-ports { + port { + tn_lpass_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tn_lpass>; + }; + }; + }; + }; + + lpass_stm: lpass-stm { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-lpass-stm"; + trace-name = "lpass-stm"; + atid = <25>; + + out-ports { + port@0 { + reg = <0>; + lpass_stm_out_funnel_lpass_lpi_1: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_1_in_lpass_stm>; + }; + }; + + port@1 { + reg = <1>; + lpass_stm_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_lpass_stm>; + }; + }; + + }; + }; + + funnel_lpass_lpi_1: funnel@10b50000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass_lpi_1"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_1_in_lpass_stm: endpoint { + remote-endpoint = + <&lpass_stm_out_funnel_lpass_lpi_1>; + }; + }; + + port@1 { + reg = <1>; + funnel_lpass_lpi_1_in_tpdm_lpass_lpi: endpoint { + remote-endpoint = + <&tpdm_lpass_lpi_out_funnel_lpass_lpi_1>; + }; + }; + + port@4 { + reg = <4>; + funnel_lpass_lpi_1_in_tpdm_lpass_rscc: endpoint { + remote-endpoint = + <&tpdm_lpass_rscc_out_funnel_lpass_lpi_1>; + }; + }; + + port@5 { + reg = <5>; + funnel_lpass_lpi_1_in_tpdm_lpass_audio: endpoint { + remote-endpoint = + <&tpdm_lpass_audio_out_funnel_lpass_lpi_1>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_lpi_1_out_funnel_lpass_lpi_0: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_0_in_funnel_lpass_lpi_1>; + }; + }; + }; + }; + + funnel_lpass_lpi_0: funnel@10b44000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass_lpi_0"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_0_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_funnel_lpass_lpi_0>; + }; + }; + + port@7 { + reg = <7>; + funnel_lpass_lpi_0_in_funnel_lpass_lpi_1: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_1_out_funnel_lpass_lpi_0>; + }; + }; + }; + + out-ports { + port { + funnel_lpass_lpi_0_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_lpass_lpi_0>; + }; + }; + }; + }; + + stm: stm@10002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + reg = <0x10002000 0x1000>, + <0x37280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + atid = <16>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_stm>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@10003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10003000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dcc_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_tpdm_dcc>; + }; + }; + }; + }; + + tpdm_ufs: tpdm@10c23000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c23000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ufs"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_ufs_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_ufs>; + }; + }; + }; + }; + + tpdm_sdcc5_2: tpdm@10c20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c20000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-sdcc2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_sdcc5_2_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_sdcc5_2>; + }; + }; + }; + }; + + tpdm_ipa: tpdm@10c22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c22000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ipa"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_ipa_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_ipa>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@10840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + status = "disabled"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_vsense_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_vsense>; + }; + }; + }; + }; + + tpdm_qm: tpdm@109d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qm_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_qm>; + }; + }; + }; + }; + + tpdm_prng: tpdm@10841000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10841000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_prng>; + }; + }; + }; + }; + + tpdm_gcc: tpdm@1082c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1082c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_gcc_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_gcc>; + }; + }; + }; + }; + + tpdm_dl_mm: tpdm@109a4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109a4000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dlmm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dl_mm_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_dl_mm>; + }; + }; + }; + }; + + tpdm_north: tpdm@109a6000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109a6000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-north-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_north_dsb_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_north_dsb>; + }; + }; + }; + }; + + tpdm_south: tpdm@109a5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109a5000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-south-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_south_dsb_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_south_dsb>; + }; + }; + }; + }; + + tpdm_ipcc_cmb: tpdm@109ab000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109ab000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ipcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_ipcc_cmb>; + }; + }; + }; + }; + + tpdm_pmu: tpdm@109aa000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109aa000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pmu"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_pmu_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_pmu>; + }; + }; + }; + }; + + tpdm_rdpm_cmb0: tpdm@109a7000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109a7000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-rdpm-cmb0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_rdpm_cmb0_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_rdpm_cmb0>; + }; + }; + }; + }; + + tpdm_rdpm_cmb1: tpdm@109a9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109a9000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-rdpm-cmb1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_rdpm_cmb1_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_rdpm_cmb1>; + }; + }; + }; + }; + + tpdm_rdpm_cmb2: tpdm@109a8000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109a8000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-rdpm-cmb2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_rdpm_cmb2_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_rdpm_cmb2>; + }; + }; + }; + }; + + tpdm_dch: tpdm@109ad000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109ad000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dch"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_dch_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_dch>; + }; + }; + }; + }; + + tpdm_channel: tpdm@109ae000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109ae000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-channel"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_channel_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_tpdm_channel>; + }; + }; + }; + }; + + tn_ag: tn@109a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000f0c00>; + reg = <0x109a0000 0x3080>; + reg-names = "traceNoc-base"; + + coresight-name = "coresight-tracenoc-ag"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,trace-noc-v2; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + tn_ag_in_tpda_pcie: endpoint { + remote-endpoint = + <&tpda_pcie_out_tn_ag>; + }; + }; + + port@b { + reg = <11>; + tn_ag_in_tn_titan: endpoint { + remote-endpoint = + <&tn_titan_out_tn_ag>; + }; + }; + + port@c { + reg = <12>; + tn_ag_in_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_out_tn_ag>; + }; + }; + + port@d { + reg = <13>; + tn_ag_in_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_out_tn_ag>; + }; + }; + + port@11 { + reg = <17>; + tn_ag_in_tpdm_gcc: endpoint { + remote-endpoint = + <&tpdm_gcc_out_tn_ag>; + }; + }; + + port@12 { + reg = <18>; + tn_ag_in_tpdm_prng: endpoint { + remote-endpoint = + <&tpdm_prng_out_tn_ag>; + }; + }; + + port@13 { + reg = <19>; + tn_ag_in_tpdm_qm: endpoint { + remote-endpoint = + <&tpdm_prng_out_tn_ag>; + }; + }; + + port@14 { + reg = <20>; + tn_ag_in_tpdm_vsense: endpoint { + remote-endpoint = + <&tpdm_vsense_out_tn_ag>; + }; + }; + + port@15 { + reg = <21>; + tn_ag_in_tpdm_ipa: endpoint { + remote-endpoint = + <&tpdm_ipa_out_tn_ag>; + }; + }; + + port@16 { + reg = <22>; + tn_ag_in_tpdm_sdcc5_2: endpoint { + remote-endpoint = + <&tpdm_sdcc5_2_out_tn_ag>; + }; + }; + + port@18 { + reg = <24>; + tn_ag_in_tpdm_ufs: endpoint { + remote-endpoint = + <&tpdm_ufs_out_tn_ag>; + }; + }; + + port@19 { + reg = <25>; + tn_ag_in_tpdm_dl_mm: endpoint { + remote-endpoint = + <&tpdm_dl_mm_out_tn_ag>; + }; + }; + + port@1a { + reg = <26>; + tn_ag_in_tpdm_north_dsb: endpoint { + remote-endpoint = + <&tpdm_north_dsb_out_tn_ag>; + }; + }; + + port@1b { + reg = <27>; + tn_ag_in_tpdm_south_dsb: endpoint { + remote-endpoint = + <&tpdm_south_dsb_out_tn_ag>; + }; + }; + + port@1c { + reg = <28>; + tn_ag_in_tpdm_ipcc_cmb: endpoint { + remote-endpoint = + <&tpdm_ipcc_cmb_out_tn_ag>; + }; + }; + + port@1d { + reg = <29>; + tn_ag_in_tpdm_pmu: endpoint { + remote-endpoint = + <&tpdm_pmu_out_tn_ag>; + }; + }; + + port@1e { + reg = <30>; + tn_ag_in_tpdm_rdpm_cmb0: endpoint { + remote-endpoint = + <&tpdm_rdpm_cmb0_out_tn_ag>; + }; + }; + + port@1f { + reg = <31>; + tn_ag_in_tpdm_rdpm_cmb1: endpoint { + remote-endpoint = + <&tpdm_rdpm_cmb1_out_tn_ag>; + }; + }; + + port@20 { + reg = <32>; + tn_ag_in_tpdm_rdpm_cmb2: endpoint { + remote-endpoint = + <&tpdm_rdpm_cmb2_out_tn_ag>; + }; + }; + + port@21 { + reg = <33>; + tn_ag_in_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_out_tn_ag>; + }; + }; + + port@23 { + reg = <35>; + tn_ag_in_tpdm_dch: endpoint { + remote-endpoint = + <&tpdm_dch_out_tn_ag>; + }; + }; + + port@24 { + reg = <36>; + tn_ag_in_tpdm_channel: endpoint { + remote-endpoint = + <&tpdm_channel_out_tn_ag>; + }; + }; + + port@26 { + reg = <38>; + tn_ag_in_funnel_dl5: endpoint { + remote-endpoint = + <&funnel_dl5_out_tn_ag>; + }; + }; + + port@2c { + reg = <44>; + tn_ag_in_funnel_dl2: endpoint { + remote-endpoint = + <&funnel_dl2_out_tn_ag>; + }; + }; + + port@2d { + reg = <45>; + tn_ag_in_funnel_dl3: endpoint { + remote-endpoint = + <&funnel_dl3_out_tn_ag>; + }; + }; + + port@2e { + reg = <46>; + tn_ag_in_funnel_dl4: endpoint { + remote-endpoint = + <&funnel_dl4_out_tn_ag>; + }; + }; + + port@4a { + reg = <74>; + tn_ag_in_tn_ddr: endpoint { + remote-endpoint = + <&tn_ddr_out_tn_ag>; + }; + }; + + port@5f { + reg = <95>; + tn_ag_in_tn_lpass: endpoint { + remote-endpoint = + <&tn_lpass_out_tn_ag>; + }; + }; + + port@61 { + reg = <97>; + tn_ag_in_tn_soccp: endpoint { + remote-endpoint = + <&tn_soccp_out_tn_ag>; + }; + }; + }; + + out-ports { + port { + tn_ag_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tn_ag>; + }; + }; + }; + }; + + tpdm_spdm: tpdm@1000f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1000f000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_spdm_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_tpdm_spdm>; + }; + }; + }; + }; + + tpda_qdss: tpda@10004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-qdss"; + + qcom,cmb-elem-size = <0 32>, + <1 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss>; + }; + }; + + port@1 { + reg = <1>; + tpda_qdss_in_tpdm_spdm: endpoint { + remote-endpoint = + <&tpdm_spdm_out_tpda_qdss>; + }; + }; + + }; + + out-ports { + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + }; + }; + + funnel_in0: funnel@10041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_in_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_out_funnel_in0>; + }; + }; + + port@6 { + reg = <6>; + funnel_in0_in_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_in0>; + }; + }; + }; + }; + + tpdm_swao_prio0: tpdm@10b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b09000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio0_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao_prio0>; + }; + }; + }; + }; + + tpdm_swao_prio1: tpdm@10b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0a000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio1_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao_prio1>; + }; + }; + }; + }; + + tpdm_swao_prio2: tpdm@10b0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0b000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio2_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao_prio2>; + }; + }; + }; + }; + + tpdm_swao_prio3: tpdm@10b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio3_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao_prio3>; + }; + }; + }; + }; + + tpdm_swao: tpdm@10b0d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0d000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao>; + }; + }; + }; + }; + + tpda_aoss: tpda@10b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10b08000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-aoss"; + + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 64>, + <3 64>; + + qcom,dsb-elem-size = <4 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_aoss_in_tpdm_swao_prio0: endpoint { + remote-endpoint = + <&tpdm_swao_prio0_out_tpda_aoss>; + }; + }; + + port@1 { + reg = <1>; + tpda_aoss_in_tpdm_swao_prio1: endpoint { + remote-endpoint = + <&tpdm_swao_prio1_out_tpda_aoss>; + }; + }; + + port@2 { + reg = <2>; + tpda_aoss_in_tpdm_swao_prio2: endpoint { + remote-endpoint = + <&tpdm_swao_prio2_out_tpda_aoss>; + }; + }; + + port@3 { + reg = <3>; + tpda_aoss_in_tpdm_swao_prio3: endpoint { + remote-endpoint = + <&tpdm_swao_prio3_out_tpda_aoss>; + }; + }; + + port@4 { + reg = <4>; + tpda_aoss_in_tpdm_swao: endpoint { + remote-endpoint = + <&tpdm_swao_out_tpda_aoss>; + }; + }; + + }; + + out-ports { + port { + tpda_aoss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_tpda_aoss>; + }; + }; + }; + }; + + funnel_aoss: funnel@10b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10b04000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-aoss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + funnel_aoss_in_tn_ddr_lpi: endpoint { + remote-endpoint = + <&tn_ddr_lpi_out_funnel_aoss>; + }; + }; + + port@5 { + reg = <5>; + funnel_aoss_in_funnel_lpass_lpi_0: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_0_out_funnel_aoss>; + }; + }; + + port@6 { + reg = <6>; + funnel_aoss_in_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_out_funnel_aoss>; + }; + }; + + port@7 { + reg = <7>; + funnel_aoss_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_aoss>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_aoss>; + }; + }; + }; + }; + + tmc_etf: tmc@10b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_out_tmc_etf>; + }; + }; + }; + + out-ports { + port { + tmc_etf_out_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_in_tmc_etf>; + }; + }; + }; + }; + + replicator_swao: replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_swao"; + + qcom,replicator-loses-context; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_swao_in_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_out_replicator_swao>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_swao_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_replicator_swao>; + }; + }; + + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + }; + }; + + dummy_eud: dummy-eud { + compatible = "arm,coresight-dummy-sink"; + + coresight-name = "coresight-eud"; + + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + }; + + replicator_qdss: replicator@10046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x10046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_qdss_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_replicator_qdss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_qdss_out_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_in_replicator_qdss>; + }; + }; + }; + }; + + replicator_etr: replicator@1004e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x1004e000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_etr"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_etr_in_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_out_replicator_etr>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_etr_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_etr>; + }; + }; + + port@1 { + reg = <1>; + replicator_etr_out_replicator_dummy: endpoint { + remote-endpoint = + <&replicator_dummy_in_replicator_etr>; + }; + }; + }; + }; + + etr1-replicator { + compatible = "arm,coresight-static-replicator"; + + coresight-name = "coresight-replicator-etr1"; + + in-ports { + port { + replicator_dummy_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_replicator_dummy>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_dummy_out_tmc_modem: endpoint { + remote-endpoint = + <&tmc_modem_in_replicator_dummy>; + }; + }; + + port@1 { + reg = <1>; + replicator_dummy_out_tmc_etr1: endpoint { + remote-endpoint = + <&tmc_etr1_in_replicator_dummy>; + }; + }; + }; + }; + + tmc_modem: tmc-modem { + compatible = "qcom,coresight-secure-etr"; + + coresight-name = "coresight-modem-etr1"; + + real-name = "coresight-tmc-etr1"; + qdss,buffer-size = <0x2000000>; + qcom,secure-component; + /* memory-region = <&qdss_apps_mem>;*/ + coresight-csr = <&csr>; + csr-atid-offset = <0x108>; + csr-irqctrl-offset = <0x70>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_modem_in_replicator_dummy: endpoint { + remote-endpoint = + <&replicator_dummy_out_tmc_modem>; + }; + }; + }; + + out-ports { + port { + tmc_modem_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_tmc_modem>; + }; + }; + }; + }; + + tmc_etr: tmc@10048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x10048000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etr"; + + qcom,iommu-dma = "bypass"; + iommus = <&apps_smmu 0x04e0 0x0>; + dma-coherent; + arm,scatter-gather; + + //usb_bamless_support; + qcom,sw-usb; + coresight-csr = <&csr>; + csr-atid-offset = <0xf8>; + csr-irqctrl-offset = <0x6c>; + byte-cntr-name = "byte-cntr"; + byte-cntr-class-name = "coresight-tmc-etr-stream"; + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_tmc_etr>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x1004f000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etr1"; + + iommus = <&apps_smmu 0x0500 0x0>; + dma-coherent; + arm,scatter-gather; + + coresight-csr = <&csr>; + csr-atid-offset = <0x108>; + csr-irqctrl-offset = <0x70>; + byte-cntr-name = "byte-cntr1"; + byte-cntr-class-name = "coresight-tmc-etr1-stream"; + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr1_in_replicator_dummy: endpoint { + remote-endpoint = + <&replicator_dummy_out_tmc_etr1>; + }; + }; + }; + }; + + tpdm_wpss: tpdm@10880000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10880000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-wpss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss>; + }; + }; + }; + }; + + tpdm_wpss1: tpdm@10881000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10881000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-wpss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss1_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss1>; + }; + }; + }; + }; + + funnel_wpss: funnel@10883000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10883000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-wpss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wpss_in_tpdm_wpss: endpoint { + remote-endpoint = + <&tpdm_wpss_out_funnel_wpss>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_in_tpdm_wpss1: endpoint { + remote-endpoint = + <&tpdm_wpss1_out_funnel_wpss>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wpss_out_tpda_dl2_4: endpoint { + remote-endpoint = + <&tpda_dl2_4_in_funnel_wpss>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_out_tpda_dl2_5: endpoint { + remote-endpoint = + <&tpda_dl2_5_in_funnel_wpss>; + }; + }; + + port@2 { + reg = <2>; + funnel_wpss_out_funnel_dl2: endpoint { + remote-endpoint = + <&funnel_dl2_in_funnel_wpss>; + }; + }; + }; + }; + + tpda_dl2: tpda@10c34000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x10c34000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-dl2"; + + qcom,dsb-elem-size = <0 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + tpda_dl2_4_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda_dl2_4>; + }; + }; + + port@5 { + reg = <5>; + tpda_dl2_5_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda_dl2_5>; + }; + }; + }; + + out-ports { + port { + tpda_dl2_out_funnel_dl2: endpoint { + remote-endpoint = + <&funnel_dl2_in_tpda_dl2>; + }; + }; + }; + }; + + funnel_dl2: funnel@10c35000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10c2d000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl2_in_tpda_dl2: endpoint { + remote-endpoint = + <&tpda_dl2_out_funnel_dl2>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl2_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_funnel_dl2>; + }; + }; + + }; + + out-ports { + port { + funnel_dl2_out_tn_ag: endpoint { + remote-endpoint = + <&tn_ag_in_funnel_dl2>; + }; + }; + }; + }; + + audio-qmi { + compatible = "qcom,coresight-qmi"; + + coresight-name = "coresight-qmi-auido"; + qcom,inst-id = <5>; + + in-ports { + port@0 { + reg = <0>; + qmi_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_qmi>; + }; + }; + + port@1 { + reg = <1>; + qmi_in_lpass_stm: endpoint { + remote-endpoint = + <&lpass_stm_out_qmi>; + }; + }; + + port@2 { + reg = <2>; + qmi_in_lpass_lpi: endpoint { + remote-endpoint = + <&lpass_lpi_out_qmi>; + }; + }; + + port@3 { + reg = <3>; + qmi_in_lpass_rscc: endpoint { + remote-endpoint = + <&lpass_rscc_out_qmi>; + }; + }; + + port@4 { + reg = <4>; + qmi_in_lpass_audio: endpoint { + remote-endpoint = + <&lpass_audio_out_qmi>; + }; + }; + }; + }; + + modem0-qmi { + compatible = "qcom,coresight-qmi"; + + coresight-name = "coresight-qmi-modem0"; + qcom,inst-id = <2>; + + in-ports { + port@0 { + reg = <0>; + qmi_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_qmi>; + }; + }; + + port@1 { + reg = <1>; + qmi_in_tmc_modem: endpoint { + remote-endpoint = + <&tmc_modem_out_qmi>; + }; + }; + }; + }; + + modem2-qmi { + compatible = "qcom,coresight-qmi"; + + coresight-name = "coresight-qmi-modem2"; + qcom,inst-id = <11>; + + in-ports { + port { + qmi_in_modem2_etm0: endpoint { + remote-endpoint = + <&modem2_etm0_out_qmi>; + }; + }; + }; + }; + + cti@10010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10010000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-qdss"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wpss_cti: cti@10882000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10882000 0x1000>; + + status = "disabled"; + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wpss"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@1088b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1088b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wpss-q6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + swao_cti: cti@10b00000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b00000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-swao"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10b21000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b21000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-aoss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10a05000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10a05000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-camera"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1098b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_qdsp"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10982000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10982000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10c32000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c32000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl2-cti0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10c33000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c33000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl2-cti1"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10d21000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d21000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_shrm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10b35000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b35000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_lpi"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10d05000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d05000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_center"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10d07000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d07000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_chhm02"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10d09000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d09000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_chhm13"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10c62000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c62000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mdss"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10961000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10961000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-a6x_isdb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10962000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10962000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-a6x_gpmu"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10901000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10901000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-a6x_dragonlink"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10b42000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b42000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10b4b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b4b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi_qdsp"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10b41000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b41000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi_cti_1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10b51000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b51000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi_cti_3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10b85000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b85000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10813000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10813000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_vdsp6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@1080b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1080b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_qdsp6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10802000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10802000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@10cd1000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cd1000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_rvss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@10cc2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_dragonlink_cti0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + status = "disabled"; + }; + + cti@10cc3000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc3000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_dragonlink_cti1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + status = "disabled"; + }; + + cti@109b0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109b0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-trace_noc_cti0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@109b1000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109b1000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-trace_noc_cti1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@109b2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109b2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-trace_noc_cti2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@109c1000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109c1000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-eva"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@10ba5000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10ba5000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-soccp"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@10831000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10831000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-venus"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@10c2a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c2a000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@10c2b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c2b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl3-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@10c12000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c12000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl4"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@10c13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c13000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl4-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@13863000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x13863000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss-dl"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cti@138e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x138e0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti_0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@138e1000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x138e1000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti_3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@138e2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x138e2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti_4"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@138f0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x138f0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti_1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + cti@13900000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x13900000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti_2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + }; +}; + From 62c67d65fd35de4b9d5da30ef6d821051d3264a5 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Fri, 20 Sep 2024 14:33:05 +0530 Subject: [PATCH 26/67] ARM: dts: msm: Add SD card support for tuna Add SD card support for tuna target. Change-Id: Iff912a5b284cae6ef6026918e3124f483cfe9802 Signed-off-by: Manish Pandey --- qcom/tuna-pinctrl.dtsi | 58 ++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 75 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 133 insertions(+) diff --git a/qcom/tuna-pinctrl.dtsi b/qcom/tuna-pinctrl.dtsi index ad6406c2..cfd44251 100644 --- a/qcom/tuna-pinctrl.dtsi +++ b/qcom/tuna-pinctrl.dtsi @@ -1580,4 +1580,62 @@ }; }; }; + + sdc2_on: sdc2_on { + clk { + pins = "gpio62"; + function = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "gpio51"; + function = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "gpio63", "gpio120", "gpio48", "gpio49"; + function = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio39"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "gpio62"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "gpio63", "gpio120", "gpio48", "gpio49"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio39"; + bias-pull-up; + drive-strength = <2>; + }; + }; }; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 07467382..7f067b3d 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -50,6 +50,7 @@ aliases { serial0 = &qupv3_se7_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ hsuart0 = &qupv3_se14_4uart; i2c0 = &qupv3_se0_i2c; i2c1 = &qupv3_se1_i2c; @@ -1355,6 +1356,80 @@ qcom,client-id = <0x00000001>; }; + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <104000 0>; + }; + }; + + sdhc_2_dma_resv: sdhc_2_dma_resv_region { + /* + * Restrict IOVA mappings for SDHC2 buffers to the 256 MB region + * from 0x40000000 - 0x4fffffff. + */ + iommu-addresses = <&sdhc_2 0x0 0x40000000>, + <&sdhc_2 0x50000000 0xb0000000>; + }; + + sdhc_2: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + no-mmc; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + /* + * DLL HSR settings. Refer go/hsr - DLL settings. + * Note that the DLL_CONFIG_2 value is not passed from the + * device tree, but it is calculated in the driver. + */ + qcom,dll-hsr-list = <0x0007442C 0x0 0x10 + 0x090106C0 0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + memory-region = <&sdhc_2_dma_resv>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + qos0 { + mask = <0xc0>; + vote = <44>; + }; + + qos1 { + mask = <0x3f>; + vote = <44>; + }; + }; + ufsphy_mem: ufsphy_mem@1d80000 { reg = <0x1d80000 0x2000>; reg-names = "phy_mem"; From 9ada1c9254d82af6bb9493a9977e29936569d152 Mon Sep 17 00:00:00 2001 From: Ankit Sharma Date: Fri, 20 Sep 2024 15:34:31 +0530 Subject: [PATCH 27/67] ARM: dts: msm: tuna: Add capacity and DPC properties The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn is used by EAS to take placement decisions. Change-Id: Iac04bf0b435d6741fd6b5ae10c4cc38675ac5170 Signed-off-by: Ankit Sharma --- qcom/tuna.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 07467382..0adf9746 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -93,6 +93,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -115,6 +117,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -133,6 +137,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_2>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_2: l2-cache { compatible = "cache"; cache-level = <2>; @@ -150,6 +156,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_3>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_3: l2-cache { compatible = "cache"; cache-level = <2>; @@ -167,6 +175,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_4>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_4: l2-cache { compatible = "cache"; cache-level = <2>; @@ -184,6 +194,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_5>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_5: l2-cache { compatible = "cache"; cache-level = <2>; @@ -201,6 +213,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_6>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_6: l2-cache { compatible = "cache"; cache-level = <2>; @@ -218,6 +232,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_7>; + capacity-dmips-mhz = <1935>; + dynamic-power-coefficient = <295>; L2_7: l2-cache { compatible = "cache"; cache-level = <2>; From b01eca59b8069251f69586ed5daffa13ef00c440 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Mon, 16 Sep 2024 12:54:02 +0530 Subject: [PATCH 28/67] ARM: dts: msm: Remove duplicate cmd-db mapping for tuna This change removes duplicate cmd_db mapping, since it is mapped twice in reserved-memory section. Change-Id: Ied3b2c6a572ff9fac61c2c50bf9eb781ccf37626 Signed-off-by: Sneh Mankad --- qcom/tuna.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 1bfe94a4..89f06440 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1774,12 +1774,6 @@ reg = <0x0 0x80e00000 0x0 0x400000>; }; - aop_cmd_db_mem: aop_cmd_db_region@81c60000 { - compatible = "qcom,cmd-db"; - no-map; - reg = <0x0 0x81c60000 0x0 0x20000>; - }; - adsp_mem_heap: adsp_heap_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; From b998d88cde194b1d8146b03bad9b51cec1b8a74d Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 23 Sep 2024 12:31:37 +0530 Subject: [PATCH 29/67] bindings: Add Pinctrl documentation for Tuna VM Add documentation describing the pinctrl devicetree properties for Tuna VM. Change-Id: Ib0372ed8bf383e1af067aba5d75ad00907f72882 Signed-off-by: Hrishabh Rajput --- bindings/pinctrl/qcom,tuna-vm-tlmm.yaml | 190 ++++++++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 bindings/pinctrl/qcom,tuna-vm-tlmm.yaml diff --git a/bindings/pinctrl/qcom,tuna-vm-tlmm.yaml b/bindings/pinctrl/qcom,tuna-vm-tlmm.yaml new file mode 100644 index 00000000..9903ed28 --- /dev/null +++ b/bindings/pinctrl/qcom,tuna-vm-tlmm.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,tuna-vm-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SUN VM TLMM block + +maintainers: + - Murali Nalajala + - Satya Durga Srinivasu Prabhala + +description: | + This binding describes the Top Level Mode Multiplexer block for VM. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,tuna-vm-tlmm + + reg: + maxItems: 1 + + interrupts-extended: true + interrupt-controller: true + '#interrupt-cells': true + + gpio-controller: true + '#gpio-cells': true + gpio-ranges: true + gpios: + description: array of gpio pin number required by VM TLMM clients + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-tuna-vm-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-tuna-vm-tlmm-state" + additionalProperties: false + +$defs: + qcom-tuna-vm-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3, + atest_char_start, atest_usb0, atest_usb00, atest_usb01, + atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1, + audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk, + cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0, + cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4, + cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2, + cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0, + cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx, + coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, + gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0, + i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0, + i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0, + i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0, + i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0, + i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, + i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1, + mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, + mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, + nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1, + phase_flag10, phase_flag11, phase_flag12, phase_flag13, + phase_flag14, phase_flag15, phase_flag16, phase_flag17, + phase_flag18, phase_flag19, phase_flag2, phase_flag20, + phase_flag21, phase_flag22, phase_flag23, phase_flag24, + phase_flag25, phase_flag26, phase_flag27, phase_flag28, + phase_flag29, phase_flag3, phase_flag30, phase_flag31, + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2, + qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3, + qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4, + qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2, + qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3, + qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0, + qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1, + qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2, + qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3, + qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4, + qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2, + qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3, + qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6, + qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0, + qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40, + sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, + tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, + vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + then: + required: + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible = "qcom,tuna-vm-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = ; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup1_se7_l0"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup1_se7_l1"; + bias-disable; + }; + }; + }; +... From c5b6b69b4d8c679db3ead430e33ae93ee459930b Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 23 Sep 2024 13:37:47 +0530 Subject: [PATCH 30/67] ARM: dts: msm: Add CPUSYS_VM support for Kera Add support for CPUSYS_VM for Kera target. Change-Id: I7c8f0656ff69cc4f117b8a1c17baa86fd6ec8eb5 Signed-off-by: Hrishabh Rajput --- qcom/kera.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index bd553f2e..76a73991 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -764,6 +764,15 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + gh-secure-vm-loader@2 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <35>; + qcom,vmid = <50>; + qcom,firmware-name = "cpusys_vm"; + memory-region = <&cpusys_vm_mem>; + }; + }; #include "tuna-gdsc.dtsi" From eaa7efe742a265234778b2253f6326f7d6f629dc Mon Sep 17 00:00:00 2001 From: Jigyanshu Mani Date: Mon, 23 Sep 2024 11:58:19 +0530 Subject: [PATCH 31/67] ARM: dts: msm: Spilt memdump entries to static and dynamic Spilt memdump entries to static and dynamic dumps. Static dumps are enabled by default. Dynamic mem dumps are enabled/disabled using sysfs nodes and it's disabled in perf build. Change-Id: I0d0e7fa1602626f59ec1eed2d2337a88a3d76730 Signed-off-by: Jigyanshu Mani --- qcom/ravelin-debug.dtsi | 497 ++++++++++++++++++++++------------------ 1 file changed, 271 insertions(+), 226 deletions(-) diff --git a/qcom/ravelin-debug.dtsi b/qcom/ravelin-debug.dtsi index c0b1e3eb..c4210ebc 100644 --- a/qcom/ravelin-debug.dtsi +++ b/qcom/ravelin-debug.dtsi @@ -11,9 +11,7 @@ ranges; dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; alignment = <0x0 0x400000>; size = <0x0 0xc00000>; }; @@ -1312,273 +1310,320 @@ }; + + mem_dump { compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; - c0_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x0>; + static_mem_dump { + qcom,static-mem-dump; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; }; - c100_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x1>; - }; + dynamic_mem_dump { + qcom,dynamic-mem-dump; - c200_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x2>; - }; + cpuss_reg { + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + }; - c300_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x3>; - }; + l1 { + l1_icache0 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x60>; + }; - c400_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x4>; - }; + l1_icache100 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x61>; + }; - c500_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x5>; - }; + l1_icache200 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x62>; + }; - c600_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x6>; - }; + l1_icache300 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x63>; + }; - c700_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x7>; - }; + l1_icache400 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x64>; + }; - cpuss_reg { - qcom,dump-size = <0x30000>; - qcom,dump-id = <0xef>; - }; + l1_icache500 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x65>; + }; - l1_icache0 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x60>; - }; + l1_icache600 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x66>; + }; - l1_icache100 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x61>; - }; + l1_icache700 { + qcom,dump-size = <0x32100>; + qcom,dump-id = <0x67>; + }; - l1_icache200 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x62>; - }; + l1_dcache0 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x80>; + }; - l1_icache300 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x63>; - }; + l1_dcache100 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x81>; + }; - l1_icache400 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x64>; - }; + l1_dcache200 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x82>; + }; - l1_icache500 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x65>; - }; + l1_dcache300 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x83>; + }; - l1_icache600 { - qcom,dump-size = <0x15100>; - qcom,dump-id = <0x66>; - }; + l1_dcache400 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x84>; + }; - l1_icache700 { - qcom,dump-size = <0x15100>; - qcom,dump-id = <0x67>; - }; + l1_dcache500 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x85>; + }; - l1_dcache0 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x80>; - }; + l1_dcache600 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x86>; + }; - l1_dcache100 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x81>; - }; + l1_dcache700 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x87>; + }; - l1_dcache200 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x82>; - }; + l1_itlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x24>; + }; - l1_dcache300 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x83>; - }; + l1_itlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x25>; + }; - l1_dcache400 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x84>; - }; + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; - l1_dcache500 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x85>; - }; + l1_itlb700 { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x27>; + }; - l1_dcache600 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x86>; - }; + l1_dtlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x44>; + }; - l1_dcache700 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x87>; - }; + l1_dtlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x45>; + }; - l1_itlb600 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x26>; - }; + l1_dtlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x46>; + }; - l1_itlb700 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x27>; - }; + l1_dtlb700 { + qcom,dump-size = <0x3a0>; + qcom,dump-id = <0x47>; + }; + }; - l1_dtlb600 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x46>; - }; + l2 { + l2_cache400 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc4>; + }; - l1_dtlb700 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x47>; - }; + l2_cache500 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc5>; + }; - l2_cache600 { - qcom,dump-size = <0x48100>; - qcom,dump-id = <0xc6>; - }; + l2_cache600 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc6>; + }; - l2_cache700 { - qcom,dump-size = <0x48100>; - qcom,dump-id = <0xc7>; - }; + l2_cache700 { + qcom,dump-size = <0x120100>; + qcom,dump-id = <0xc7>; + }; - l2_tlb0 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x120>; - }; + l2_tlb0 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x120>; + }; - l2_tlb100 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x121>; - }; + l2_tlb100 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x121>; + }; - l2_tlb200 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x122>; - }; + l2_tlb200 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x122>; + }; - l2_tlb300 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x123>; - }; + l2_tlb300 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x123>; + }; - l2_tlb400 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x124>; - }; + l2_tlb400 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x124>; + }; - l2_tlb500 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x125>; - }; + l2_tlb500 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x125>; + }; - l2_tlb600 { - qcom,dump-size = <0x6100>; - qcom,dump-id = <0x126>; - }; + l2_tlb600 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x126>; + }; - l2_tlb700 { - qcom,dump-size = <0x6100>; - qcom,dump-id = <0x127>; - }; - - rpmh { - qcom,dump-size = <0x400000>; - qcom,dump-id = <0xec>; - }; - - rpm_sw { - qcom,dump-size = <0x28000>; - qcom,dump-id = <0xea>; - }; - - pmic { - qcom,dump-size = <0x200000>; - qcom,dump-id = <0xe4>; - }; - - fcm { - qcom,dump-size = <0x8400>; - qcom,dump-id = <0xee>; - }; - - etf_swao { - qcom,dump-size = <0x10000>; - qcom,dump-id = <0xf1>; - }; - - etr_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x100>; - }; - - etfswao_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x102>; - }; - - etr1_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x105>; - }; - - misc_data { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0xe8>; - }; - - etf_lpass { - qcom,dump-size = <0x4000>; - qcom,dump-id = <0xf4>; - }; - - etflpass_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x104>; - }; - - osm_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x163>; - }; - - pcu_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x164>; - }; - - fsm_data { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x165>; + l2_tlb700 { + qcom,dump-size = <0xc100>; + qcom,dump-id = <0x127>; + }; + }; }; }; }; + From a2a1c398f5a3c7661845cacccf0a988db2738125 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Tue, 17 Sep 2024 11:58:48 +0530 Subject: [PATCH 32/67] bindings: spmi: spmi-pmic-arb: Add description for "qcom,mid" Add a description for the "qcom,mid" property which corresponds to the SPMI master ID of the SPMI PMIC arbiter controller. It is most useful in systems with multiple masters, e.g. when there are multiple SoCs connected to a single SPMI bus. Change-Id: I376e6f569f9bbea44ba3930480a330fb1dd2c2de Signed-off-by: Ayyagari Ushasreevalli --- bindings/spmi/qcom,spmi-pmic-arb.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/spmi/qcom,spmi-pmic-arb.yaml b/bindings/spmi/qcom,spmi-pmic-arb.yaml index fee4f0eb..d7308d84 100644 --- a/bindings/spmi/qcom,spmi-pmic-arb.yaml +++ b/bindings/spmi/qcom,spmi-pmic-arb.yaml @@ -85,6 +85,13 @@ properties: description: > which of the PMIC Arb provided channels to use for accesses + qcom,mid: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: > + SPMI master ID of this controller. + required: - compatible - reg-names From 8c6647b13370c751e1960cf8a04796055291ba44 Mon Sep 17 00:00:00 2001 From: Sayali Patil Date: Mon, 23 Sep 2024 23:04:56 +0530 Subject: [PATCH 33/67] ARM: dts: msm: Add xo clock handle for monaco Add xo clock handle for monaco. Change-Id: Ifd7fba89ea8bd19e288494373573a0d83d925692 Signed-off-by: Sayali Patil --- qcom/msm-arm-smmu-monaco.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi index fada8aa3..2338fce6 100644 --- a/qcom/msm-arm-smmu-monaco.dtsi +++ b/qcom/msm-arm-smmu-monaco.dtsi @@ -23,10 +23,12 @@ vdd-supply = <&gpu_cx_gdsc>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", - "gpu_cc_hlos1_vote_gpu_smmu_clk"; + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "xo"; #size-cells = <1>; #address-cells = <1>; ranges; From 268875af17d750a75e8af4488c79b063a1f31d8d Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Tue, 24 Sep 2024 13:35:40 +0530 Subject: [PATCH 34/67] ARM: dts: msm: Add mem-buf device for tuna The mem-buf device provides memory related services for shared memory between host and guest VMs. Change-Id: I72412dc7c5cbba1ddfd991a10c603bbbd15a266c Signed-off-by: Vijayanand Jitta --- qcom/tuna.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 8286f4e9..61525cb3 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -637,6 +637,16 @@ qcom,vmid-cp-camera-preview-ro; }; + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; + qcom,vmid = <3>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + }; + cam_rsc: rsc@adc8000 { label = "cam_rsc"; compatible = "qcom,rpmh-rsc"; From 79824b3a5ba0ebd3fce6a8401629b17b1c1bd9e5 Mon Sep 17 00:00:00 2001 From: Prakash Yadachi Date: Tue, 24 Sep 2024 14:17:01 +0530 Subject: [PATCH 35/67] ARM: dts: msm: Ignore dependencies on children by PM framework Change https://lore.kernel.org/all/20230525113034.46880-1-tony@atomide.com registers serial core controller as a child of msm uart device. Since child should suspend first, due to the child's auto suspend delay (SERIAL_PORT_AUTOSUSPEND_DELAY_MS), additional 500msecs delay is added during msm_geni_serial_runtime_suspend. Added new dtsi flag 'qcom,suspend-ignore-children', to ignore dependencies on children by runtime PM framework, this helps to exit quickly from msm_geni_serial_runtime_suspend and save power. Change-Id: I4b552c76a8b25fcad92762eba036ffe1797c4e26 Signed-off-by: Prakash Yadachi --- qcom/ravelin-qupv3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi index cd4af450..eeb1ec49 100644 --- a/qcom/ravelin-qupv3.dtsi +++ b/qcom/ravelin-qupv3.dtsi @@ -93,6 +93,7 @@ <&qupv3_se2_tx>, <&qupv3_se2_default_rx>; pinctrl-3 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>, <&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>; + qcom,suspend-ignore-children; qcom,wakeup-byte = <0xFD>; status = "disabled"; }; From 9e13f86902749bc3bff011111ee23c38413968da Mon Sep 17 00:00:00 2001 From: Khaja Hussain Shaik Khaji Date: Thu, 29 Aug 2024 20:45:58 +0530 Subject: [PATCH 36/67] ARM: dts: msm: Add remoteproc node for sdxkova Add remoteproc node for sdxkova modem subsystem. Change-Id: I0ee5423964240f74a1dad0819722ce8262f5850f Signed-off-by: Khaja Hussain Shaik Khaji --- qcom/sdxkova.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index bf209812..1a4d6c59 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -1664,6 +1664,49 @@ }; }; }; + + modem_pas: remoteproc-mss@04080000 { + compatible = "qcom,sdxpinn-modem-pas"; + reg = <0x0 0x4080000 0x0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + qcom,signal-aop; + qcom,qmp = <&aoss_qmp>; + memory-region = <&mpssadsp_mem>, + <&q6_mpss_dtb_mem>, + <&system_cma>, + <&dsm_partition_1_mem>, + <&dsm_partition_2_mem>, + <&qlink_logging_mem>; + firmware-name = "modem.mdt", "modem_dtb.mdt"; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; }; &gcc { From e67dc19200519fae32a1e431d4e5d5638d773bcd Mon Sep 17 00:00:00 2001 From: Saranya R Date: Wed, 25 Sep 2024 12:26:41 +0530 Subject: [PATCH 37/67] ARM: dts: msm: Update qcom,dma-heap-type for waipio vm Update qcom,dma-heap-type for waipio vm. Change-Id: Ic940af23b644f61242c5c5a17de9fc986fc80e9c Signed-off-by: Saranya R --- qcom/waipio-vm-dma-heaps.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/waipio-vm-dma-heaps.dtsi b/qcom/waipio-vm-dma-heaps.dtsi index 34c6196c..ddaf08af 100644 --- a/qcom/waipio-vm-dma-heaps.dtsi +++ b/qcom/waipio-vm-dma-heaps.dtsi @@ -11,7 +11,7 @@ qcom,tui { qcom,dma-heap-name = "qcom,tui"; - qcom,dma-heap-type = ; + qcom,dma-heap-type = ; qcom,dynamic-heap; }; }; From cc4e4c81689809717625f2f6b6e4d5037eb59c90 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Wed, 25 Sep 2024 14:30:37 +0530 Subject: [PATCH 38/67] ARM: dts: msm: Remove duplicate scm node for tuna Remove the duplicate entries for SCM node in tuna. Change-Id: I64fb9995dc3a371e8bcf19abd4ba68b7a10e0be4 Signed-off-by: Souradeep Chowdhury --- qcom/tuna.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 8286f4e9..0ce3690b 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -41,10 +41,7 @@ reserved_memory: reserved-memory {}; firmware: firmware { - qcom_scm: qcom_scm { - compatible = "qcom,scm"; - qcom,dload-mode = <&tcsr 0x19000>; - }; + qcom_scm: qcom_scm {}; }; aliases { From b3872295bcbec737561122049a1a111a80acb5c7 Mon Sep 17 00:00:00 2001 From: Kartikey Arora Date: Wed, 4 Sep 2024 02:28:06 +0530 Subject: [PATCH 39/67] ARM: dts: msm: Add wpss rproc node for tuna Add wpss rproc node for tuna. Change-Id: Ic40fb4ec80e55b9a3279969dd4145f759768795f CRs-Fixed: 3932187 Signed-off-by: Kartikey Arora --- bindings/remoteproc/qcom,adsp.yaml | 1 + qcom/tuna.dtsi | 41 ++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/bindings/remoteproc/qcom,adsp.yaml b/bindings/remoteproc/qcom,adsp.yaml index 842ebec6..fe76d57e 100644 --- a/bindings/remoteproc/qcom,adsp.yaml +++ b/bindings/remoteproc/qcom,adsp.yaml @@ -72,6 +72,7 @@ properties: - qcom,ravelin-wpss-pas - qcom,monaco-modem-pas - qcom,monaco-adsp-pas + - qcom,tuna-wpss-pas reg: maxItems: 1 diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index ef144f2d..9b4844fa 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Tuna"; @@ -1060,6 +1061,46 @@ restrict-access; }; + wpss_pas: remoteproc-wpss@a3500000 { + compatible = "qcom,tuna-wpss-pas"; + reg = <0xa3500000 0x10000>; + status = "ok"; + + memory-region = <&wpss_mem>; + + firmware-name = "wcn7750/wpss.mdt"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx","mx"; + + qcom,qmp = <&aoss_qmp>; + + /* Inputs from wpss */ + interrupts-extended = <&intc GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 0>, + <&wpss_smp2p_in 2 0>, + <&wpss_smp2p_in 1 0>, + <&wpss_smp2p_in 3 0>, + <&wpss_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to wpss */ + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From 3f87c02bd8d89695f7b237912939ec5faf4eeea5 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 23 Sep 2024 14:54:26 +0530 Subject: [PATCH 40/67] ARM: dts: msm: Remove duplicate reserved_memory nodes from Tuna DT gunyah_hyp_mem and cpusys_vm_mem reserved memory nodes are added twice for Tuna. Remove one set of redundant nodes. Change-Id: I9673b12e1911d5cc782aed62d9c1f22f821a7af6 Signed-off-by: Hrishabh Rajput --- qcom/tuna.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index ef144f2d..9a2fbd09 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1953,16 +1953,6 @@ #size-cells = <2>; ranges; - gunyah_hyp_mem: gunyah_hyp_region@80000000 { - no-map; - reg = <0x0 0x80000000 0x0 0xe00000>; - }; - - cpusys_vm_mem: cpusys_vm_region@80e00000 { - no-map; - reg = <0x0 0x80e00000 0x0 0x400000>; - }; - adsp_mem_heap: adsp_heap_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; From db3e5d0cc18cd3183cf1411fae65ee856bd58254 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 23 Sep 2024 14:02:45 +0530 Subject: [PATCH 41/67] ARM: dts: msm: Add initial devicetree for Tuna VM Add initial devicetree files for trustedvm for RUMI platform on Tuna SoC. Change-Id: I3d0694b8542c1f30a52d6caa89cdad1bd1174a2e Signed-off-by: Hrishabh Rajput --- qcom/Makefile | 7 ++ qcom/platform_map.bzl | 7 ++ qcom/tuna-vm-rumi.dts | 15 +++ qcom/tuna-vm-rumi.dtsi | 8 ++ qcom/tuna-vm.dtsi | 246 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 283 insertions(+) create mode 100644 qcom/tuna-vm-rumi.dts create mode 100644 qcom/tuna-vm-rumi.dtsi create mode 100644 qcom/tuna-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 6ee3d039..d0475ffa 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -210,6 +210,13 @@ dtb-y += $(sun_tuivm-dtb-y) endif endif +ifeq ($(CONFIG_ARCH_TUNA), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +tuna_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += tuna-vm-rumi.dtb +dtb-y += $(tuna_tuivm-dtb-y) +endif +endif + MONACO_BASE_DTB += monaco.dtb monacop.dtb MONACO_BOARDS += \ diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 13818ee9..d187d777 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -141,6 +141,7 @@ _platform_map = { {"name": "sunp-vm-hdk.dtb"}, {"name": "sun-vm-rumi.dtb"}, ], + "binary_compatible_with": ["tuna-tuivm"], }, "sun-oemvm": { "dtb_list": [ @@ -161,6 +162,12 @@ _platform_map = { {"name": "sun-vm-rumi.dtb"}, ], }, + "tuna-tuivm": { + "dtb_list": [ + # keep sorted + {"name": "tuna-vm-rumi.dtb"}, + ], + }, "pineapple": { "dtb_list": [ {"name": "pineapple.dtb"}, diff --git a/qcom/tuna-vm-rumi.dts b/qcom/tuna-vm-rumi.dts new file mode 100644 index 00000000..a15beab4 --- /dev/null +++ b/qcom/tuna-vm-rumi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/tuna-vm-rumi.dtsi b/qcom/tuna-vm-rumi.dtsi new file mode 100644 index 00000000..7cb42305 --- /dev/null +++ b/qcom/tuna-vm-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&arch_timer { + clock-frequency = <500000>; +}; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi new file mode 100644 index 00000000..634f9aaf --- /dev/null +++ b/qcom/tuna-vm.dtsi @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <655 0x10000>; + interrupt-parent = <&vgic>; + + chosen { + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + + CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "QTI"; + image-name = "qcom,trustedvm"; + qcom,pasid = <0x0 0x1c>; + qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;"; + qcom,secdomain-ids = <45>; + qcom,primary-vm-index = <0>; + vm-uri = "vmuid/trusted-ui"; + vm-guid = "598085da-c516-5b25-a9c1-927a02819770"; + qcom,sensitive; + + vm-attrs = "context-dump", "crash-restart"; + + /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. + * QUP1_SE4: GPII5 : IRQ_316 + * QUP2_SE7: GPII5 : IRQ_625 + */ + gic-irq-ranges = <316 316 + 625 625 /* PVM->SVM IRQ transfer */ + 279 279>; + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + /* + * IPA address linux image is loaded at. Must be within + * first 1GB due to memory hotplug requirement. + */ + base-address = <0x0 0x88800000 >; + }; + + segments { + config_cpio = <2>; + }; + + vcpus { + config = "/cpus"; + affinity = "proxy"; + affinity-map = <0x5 0x6>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + + minidump { + vdevice-type = "minidump"; + push-compatible = "qcom,minidump_rm"; + minidump_allowed; + }; + + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + virtio-mmio@0 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x1>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x0>; + memory { + qcom,label = <0x11>; //for persist.img + #address-cells = <0x2>; + base = <0x0 0xDA6F8000>; + }; + }; + + virtio-mmio@1 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x2>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x4000>; + memory { + qcom,label = <0x10>; //for system.img + #address-cells = <0x2>; + base = <0x0 0xDA6FC000>; + }; + }; + + virtio-mmio@2 { + vdevice-type = "virtio-mmio"; + patch = "/soc/virtio-mmio"; + peer-default; + vqs-num = <0x3>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x8000>; + memory { + qcom,label = <0x15>; //for virtio-vsock + #address-cells = <0x2>; + base = <0x0 0xDA700000>; + }; + }; + + swiotlb-shm { + vdevice-type = "shm"; + generate = "/swiotlb"; + push-compatible = "swiotlb"; + peer-default; + dma_base = <0x0 0x14000>; + memory { + qcom,label = <0x12>; + #address-cells = <0x2>; + base = <0x0 0xDA70c000>; + }; + }; + + vrtc { + vdevice-type = "vrtc-pl031"; + peer-default; + allocate-base; + }; + + }; + }; + + firmware: firmware { + qcom_scm: qcom_scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + virtio-mmio { + wakeup-source; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vgic: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x200000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <64>; + qcom,support-hypervisor; + }; +}; From 3e6e93e7b466df40a7dffae1cb355db131f03b8d Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 24 Sep 2024 03:49:09 -0700 Subject: [PATCH 42/67] ARM: dts: msm: Add watchdog node for kera and tuna Add the gh_watchdog node for kera and tuna. Change-Id: I49b90fc0e4abf6a912937cd474b048c2b8178ea5 Signed-off-by: Souradeep Chowdhury --- qcom/kera.dtsi | 4 ++++ qcom/tuna.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 845760d9..5d8aafc3 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -201,6 +201,10 @@ }; soc: soc { }; + + hypervisor: hypervisor { + gh_watchdog: qcom,gh-watchdog { }; + }; }; &firmware { diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index ef144f2d..c2728500 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -397,6 +397,10 @@ }; soc: soc { }; + + hypervisor: hypervisor { + gh_watchdog: qcom,gh-watchdog { }; + }; }; #include "tuna-reserved-memory.dtsi" From 1ed9c05e8e0b69766670d4d5d59b0671e9024a95 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 24 Sep 2024 03:50:42 -0700 Subject: [PATCH 43/67] ARM: dts: msm: Add the EUD node in Tuna Add the DT entry for EUD in Tuna. Change-Id: Iae927ff6e5a17909d8fbe76702efaf85d5113dd9 Signed-off-by: Souradeep Chowdhury --- qcom/tuna.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index ef144f2d..940a3568 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1054,6 +1054,19 @@ interrupt-names = "smp2p-sleepstate-in"; }; + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x88e0000 0x2000>, + <0x88e2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + qcom,eud-utmi-delay = /bits/ 16 <255>; + status = "ok"; + }; + qcom,msm-adsprpc-mem { compatible = "qcom,msm-adsprpc-mem-region"; memory-region = <&adsp_mem_heap>; From c0ad941ff44b72d03d95ad013ff442d9e5bf5cf8 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 24 Sep 2024 03:37:08 -0700 Subject: [PATCH 44/67] ARM: dts: msm: Add bootargs for tuna and kera Add the bootargs entry for tuna and kera. Change-Id: I07c281141826710d81d9b148e4eb25816d834c02 Signed-off-by: Souradeep Chowdhury --- qcom/kera.dtsi | 128 +------------------------------------------------ qcom/tuna.dtsi | 3 +- 2 files changed, 4 insertions(+), 127 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 845760d9..bebf9072 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -30,7 +30,8 @@ }; chosen: chosen { - bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; + stdout-path = "/soc/qcom,qupv3_1_geni_se@8c0000/qcom,qup_uart@894000:115200n8"; }; reserved_memory: reserved-memory {}; @@ -232,25 +233,6 @@ size = <0x0 0x2000000>; linux,cma-default; }; - - kinfo_mem: debug_kinfo_region { - alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; - size = <0x0 0x1000>; - no-map; - }; - - va_md_mem: va_md_mem_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x1000000>; - }; - - ramoops_mem: ramoops-region { - alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; - size = <0x0 0x200000>; - no-map; - }; }; &soc { @@ -338,11 +320,6 @@ }; }; - qcom,secure-buffer { - compatible = "qcom,secure-buffer"; - qcom,vmid-cp-camera-preview-ro; - }; - apps_rsc: rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; @@ -649,11 +626,6 @@ }; }; - cpu_pmu: cpu-pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - qcom,smp2p_sleepstate { compatible = "qcom,smp2p-sleepstate"; qcom,smem-states = <&sleepstate_smp2p_out 0>; @@ -662,64 +634,6 @@ interrupt-names = "smp2p-sleepstate-in"; }; - qcom,msm-imem@14680000 { - compatible = "qcom,msm-imem"; - reg = <0x14680000 0x1000>; - ranges = <0x0 0x14680000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - mem_dump_table@10 { - compatible = "qcom,msm-imem-mem_dump_table"; - reg = <0x10 0x8>; - }; - - restart_reason@65c { - compatible = "qcom,msm-imem-restart_reason"; - reg = <0x65c 0x4>; - }; - - dload_type@1c { - compatible = "qcom,msm-imem-dload-type"; - reg = <0x1c 0x4>; - }; - - boot_stats@6b0 { - compatible = "qcom,msm-imem-boot_stats"; - reg = <0x6b0 0x20>; - }; - - kaslr_offset@6d0 { - compatible = "qcom,msm-imem-kaslr_offset"; - reg = <0x6d0 0xc>; - }; - - pil@94c { - compatible = "qcom,pil-reloc-info"; - reg = <0x94c 0xc8>; - }; - - pil@6dc { - compatible = "qcom,msm-imem-pil-disable-timeout"; - reg = <0x6dc 0x4>; - }; - - diag_dload@c8 { - compatible = "qcom,msm-imem-diag-dload"; - reg = <0xc8 0xc8>; - }; - - modem_dsm@c98 { - compatible = "qcom,msm-imem-mss-dsm"; - reg = <0xc98 0x10>; - }; - - sys_dbg@af8 { - compatible = "qcom,msm-imem-gpu-dump-skip"; - reg = <0xb0c 0x4>; - }; - }; - eud: qcom,msm-eud@88e0000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; @@ -733,35 +647,6 @@ status = "ok"; }; - google,debug-kinfo { - compatible = "google,debug-kinfo"; - memory-region = <&kinfo_mem>; - }; - - mini_dump_mode { - compatible = "qcom,minidump"; - status = "ok"; - }; - - va_mini_dump { - compatible = "qcom,va-minidump"; - memory-region = <&va_md_mem>; - status = "ok"; - }; - - qcom_ramoops { - compatible = "qcom,ramoops"; - memory-region = <&ramoops_mem>; - pmsg-size = <0x200000>; - mem-type = <2>; - }; - - qcom,mpm2-sleep-counter@c221000 { - compatible = "qcom,mpm2-sleep-counter"; - reg = <0xc221000 0x1000>; - clock-frequency = <32768>; - }; - qcom,msm-adsprpc-mem { compatible = "qcom,msm-adsprpc-mem-region"; memory-region = <&adsp_mem_heap>; @@ -881,15 +766,6 @@ #clock-cells = <1>; #reset-cells = <1>; }; - - gh-secure-vm-loader@2 { - compatible = "qcom,gh-secure-vm-loader"; - qcom,pas-id = <35>; - qcom,vmid = <50>; - qcom,firmware-name = "cpusys_vm"; - memory-region = <&cpusys_vm_mem>; - }; - }; #include "tuna-gdsc.dtsi" diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index ef144f2d..973a1110 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -35,7 +35,8 @@ }; chosen: chosen { - bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; + stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; }; reserved_memory: reserved-memory {}; From 23c3bd006e45edd9696a255eefe522391590b760 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Fri, 16 Aug 2024 10:50:03 -0700 Subject: [PATCH 45/67] ARM: dts: msm: Use per-device genpd domain Guidance from genpd team is to use a different power domain for each device to avoid race condition in genpd framework when multiple devices on same power domain runtime suspend in parallel. Change-Id: I683ff80e5cef9583b65c14aa24db0f24d4ed981c Signed-off-by: Patrick Daly --- qcom/msm-arm-smmu-sun.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/msm-arm-smmu-sun.dtsi b/qcom/msm-arm-smmu-sun.dtsi index 4b640146..88ddefaf 100644 --- a/qcom/msm-arm-smmu-sun.dtsi +++ b/qcom/msm-arm-smmu-sun.dtsi @@ -22,7 +22,7 @@ * bandwidth vote must be present to prevent DDR * shutdown. */ - power-domains = <&gpucc GPU_CC_CX_GDSC>; + power-domains = <&gpucc GPU_CC_CX_SMMU_GDSC>; interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; From 3e0774d0ded124756e6fcc44c8f4c6df9dbf7617 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 23 Sep 2024 13:48:35 +0530 Subject: [PATCH 46/67] ARM: dts: msm: Add trustedvm support for Tuna Add device-tree nodes required to support trustedvm on Tuna SoC. Change-Id: I877bafe340f09a0415edf27e1409e2475ad452d6 Signed-off-by: Hrishabh Rajput --- qcom/tuna.dtsi | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 9a2fbd09..cdfcf995 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1792,6 +1792,63 @@ }; }; + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { + size = <0x4000>; + gunyah-label = <0x11>; + }; + + trust_ui_vm_vblk1_ring: trust_ui_vm_vblk1_ring { + size = <0x4000>; + gunyah-label = <0x10>; + }; + + + trust_ui_vm_vsock_ring: trust_ui_vm_vsock_ring { + size = <0xc000>; + gunyah-label = <0x15>; + }; + + trust_ui_vm_swiotlb: trust_ui_vm_swiotlb { + size = <0x400000>; + gunyah-label = <0x12>; + }; + + trust_ui_vm: qcom,trust_ui_vm { + vm_name = "trustedvm"; + shared-buffers-size = <0x414000>; + shared-buffers = <&trust_ui_vm_vblk0_ring + &trust_ui_vm_vblk1_ring + &trust_ui_vm_vsock_ring + &trust_ui_vm_swiotlb>; + }; + + trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x11>; + }; + + trust_ui_vm_virt_be1: trust_ui_vm_virt_be1@10 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x10>; + }; + + trust_ui_vm_virt_be2: trust_ui_vm_virt_be2@15 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x15>; + }; + + gh-secure-vm-loader@0 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <28>; + qcom,vmid = <45>; + qcom,firmware-name = "trustedvm"; + qcom,keep-running; + memory-region = <&trust_ui_vm_mem &vm_comm_mem>; + virtio-backends = <&trust_ui_vm_virt_be0 + &trust_ui_vm_virt_be1 + &trust_ui_vm_virt_be2>; + }; + gh-secure-vm-loader@2 { compatible = "qcom,gh-secure-vm-loader"; qcom,pas-id = <35>; @@ -1953,6 +2010,21 @@ #size-cells = <2>; ranges; + trust_ui_vm_mem: trust_ui_vm_region@f3800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf3800000 0x0 0x4400000>; + reusable; + alignment = <0x0 0x400000>; + }; + + vm_comm_mem: vm_comm_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + adsp_mem_heap: adsp_heap_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; From e684cfa2ed118071265d53bbfda988e9bda3566b Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Fri, 7 Jun 2024 13:52:24 +0530 Subject: [PATCH 47/67] ARM: dts: msm: Add stub regulator devices for kera Add stub regulator devices for the SMPS, LDO, and BOB regulators found on the PMICs used on kera boards to allow the regulator clients to vote on them. Change-Id: I1ff88145cdfb7111e473653d4a26e332f93267a8 Signed-off-by: Kavya Nunna --- qcom/kera-stub-regulators.dtsi | 615 +++++++++++++++++++++++++++++++++ qcom/kera.dtsi | 1 + 2 files changed, 616 insertions(+) create mode 100644 qcom/kera-stub-regulators.dtsi diff --git a/qcom/kera-stub-regulators.dtsi b/qcom/kera-stub-regulators.dtsi new file mode 100644 index 00000000..02d69e38 --- /dev/null +++ b/qcom/kera-stub-regulators.dtsi @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + + S1B: + pmxr2230_s1: regulator-pmxr2230-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + }; + + S2B: + pmxr2230_s2: regulator-pmxr2230-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_s2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1020000>; + regulator-max-microvolt = <2100000>; + }; + + S3B: + pmxr2230_s3: regulator-pmxr2230-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_s3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <2744000>; + }; + + S4B: + pmxr2230_s4: regulator-pmxr2230-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_s4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2156000>; + regulator-max-microvolt = <2400000>; + }; + + VDD_NSP1_LEVEL: + S5B_LEVEL: + pmxr2230_s5_level: regulator-pmxr2230-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L1B: + pmxr2230_l1: regulator-pmxr2230-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L2B: + pmxr2230_l2: regulator-pmxr2230-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + }; + + L4B: + pmxr2230_l4: regulator-pmxr2230-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + }; + + L5B: + pmxr2230_l5: regulator-pmxr2230-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L6B: + pmxr2230_l6: regulator-pmxr2230-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1370000>; + }; + + L7B: + pmxr2230_l7: regulator-pmxr2230-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <2000000>; + }; + + L8B: + pmxr2230_l8: regulator-pmxr2230-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + }; + + L9B: + pmxr2230_l9: regulator-pmxr2230-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <756000>; + regulator-max-microvolt = <816000>; + }; + + L10B: + pmxr2230_l10: regulator-pmxr2230-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + }; + + L11B: + pmxr2230_l11: regulator-pmxr2230-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L12B: + pmxr2230_l12: regulator-pmxr2230-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + L13B: + pmxr2230_l13: regulator-pmxr2230-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + }; + + L14B: + pmxr2230_l14: regulator-pmxr2230-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <2940000>; + }; + + L15B: + pmxr2230_l15: regulator-pmxr2230-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L16B: + pmxr2230_l16: regulator-pmxr2230-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3544000>; + }; + + L17B: + pmxr2230_l17: regulator-pmxr2230-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + }; + + L18B: + pmxr2230_l18: regulator-pmxr2230-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3544000>; + }; + + L19B: + pmxr2230_l19: regulator-pmxr2230-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3544000>; + }; + + L20B: + pmxr2230_l20: regulator-pmxr2230-l20 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l20"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + }; + + L21B: + pmxr2230_l21: regulator-pmxr2230-l21 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l21"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + }; + + L22B: + pmxr2230_l22: regulator-pmxr2230-l22 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l22"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3400000>; + }; + + L23B: + pmxr2230_l23: regulator-pmxr2230-l23 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l23"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + VDD_MX_LEVEL: + S1D_LEVEL: + pm_v6d_s1_level: regulator-pm_v6d-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL_AO: + S1D_LEVEL_AO: + pm_v6d_s1_level_ao: regulator-pm_v6d-s1-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s1_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + }; + + VDD_EBI_LEVEL: + S3D_LEVEL: + pm_v6d_s3_level: regulator-pm_v6d-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MODEM_LEVEL: + S4D_LEVEL: + pm_v6d_s4_level: regulator-pm_v6d-s4-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s4_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL: + S5D_LEVEL: + pm_v6d_s5_level: regulator-pm_v6d-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + S5D_LEVEL_AO: + pm_v6d_s5_level_ao: regulator-pm_v6d-s5-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s5_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L1D: + pm_v6d_l1: regulator-pm_v6d-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + }; + + L2D: + pm_v6d_l2: regulator-pm_v6d-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <556000>; + regulator-max-microvolt = <816000>; + }; + + VDD_LPI_CX_LEVEL: + L3D_LEVEL: + pm_v6d_l3_level: regulator-pm_v6d-l3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_l3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_LPI_MX_LEVEL: + L3B_LEVEL: + pmxr2230_l3_level: regulator-pmxr2230-l3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_GFX_LEVEL: + S1G_LEVEL: + pm_v6g_s1_level: regulator-pm_v6g-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S3G: + pm_v6g_s3: regulator-pm_v6g-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_s3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + L1G: + pm_v6g_l1: regulator-pm_v6g-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + L2G: + pm_v6g_l2: regulator-pm_v6g-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L3G: + pm_v6g_l3: regulator-pm_v6g-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1980000>; + }; + + S1I: + pmg1110i_s1: regulator-pmg1110i-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmg1110i_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1352000>; + }; + + S1J: + pmg1110j_s1: regulator-pmg1110j-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmg1110j_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1352000>; + }; + + L1K: + pmr735b_l1: regulator-pmr735b-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <806000>; + regulator-max-microvolt = <901000>; + }; + + L2K: + pmr735b_l2: regulator-pmr735b-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <969000>; + }; + + L3K: + pmr735b_l3: regulator-pmr735b-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1224000>; + }; + + L4K: + pmr735b_l4: regulator-pmr735b-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1854000>; + }; + + L5K: + pmr735b_l5: regulator-pmr735b-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <931000>; + }; + + L6K: + pmr735b_l6: regulator-pmr735b-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2000000>; + }; + + L7K: + pmr735b_l7: regulator-pmr735b-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <831000>; + regulator-max-microvolt = <919000>; + }; + + L1M: + pm8010m_l1: regulator-pm8010m-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + L2M: + pm8010m_l2: regulator-pm8010m-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + }; + + L3M: + pm8010m_l3: regulator-pm8010m-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L4M: + pm8010m_l4: regulator-pm8010m-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L5M: + pm8010m_l5: regulator-pm8010m-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + L6M: + pm8010m_l6: regulator-pm8010m-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L7M: + pm8010m_l7: regulator-pm8010m-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + }; + + L1N: + pm8010n_l1: regulator-pm8010n-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + L2N: + pm8010n_l2: regulator-pm8010n-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + }; + + L3N: + pm8010n_l3: regulator-pm8010n-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + }; + + L4N: + pm8010n_l4: regulator-pm8010n-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + }; + + L5N: + pm8010n_l5: regulator-pm8010n-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1980000>; + }; + + L6N: + pm8010n_l6: regulator-pm8010n-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L7N: + pm8010n_l7: regulator-pm8010n-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index b1d09dc3..d8ac88ee 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -903,6 +903,7 @@ }; #include "kera-pinctrl.dtsi" +#include "kera-stub-regulators.dtsi" #include "kera-usb.dtsi" #include "kera-qupv3.dtsi" From 7aa4cffcc7f65b7d4f0dc57dc38d4bc77bbf8b0b Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Thu, 26 Sep 2024 12:04:48 +0530 Subject: [PATCH 48/67] ARM: dts: msm: Add oemvm support for Tuna Add device-tree nodes required to support oemvm on Tuna SoC. Change-Id: I338429e2a15405b328106634a2b50290fd975023 Signed-off-by: Hrishabh Rajput --- qcom/tuna.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index cdfcf995..020e452c 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1849,6 +1849,47 @@ &trust_ui_vm_virt_be2>; }; + oem_vm_vblk0_ring: oem_vm_vblk0_ring { + size = <0x4000>; + gunyah-label = <0x16>; + }; + + oem_vm_vblk1_ring: oem_vm_vblk1_ring { + size = <0x4000>; + gunyah-label = <0x13>; + }; + + oem_vm_swiotlb: oem_vm_swiotlb { + size = <0x100000>; + gunyah-label = <0x14>; + }; + + oem_vm: qcom,oem_vm { + vm_name = "oemvm"; + shared-buffers-size = <0x108000>; + shared-buffers = <&oem_vm_vblk0_ring &oem_vm_vblk1_ring &oem_vm_swiotlb>; + }; + + oem_vm_virt_be0: oem_vm_virt_be0@16 { + qcom,vm = <&oem_vm>; + qcom,label = <0x16>; + }; + + oem_vm_virt_be1: oem_vm_virt_be1@13 { + qcom,vm = <&oem_vm>; + qcom,label = <0x13>; + }; + + gh-secure-vm-loader@1 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <34>; + qcom,vmid = <49>; + qcom,firmware-name = "oemvm"; + qcom,keep-running; + memory-region = <&oem_vm_mem &vm_comm_mem>; + virtio-backends = <&oem_vm_virt_be0 &oem_vm_virt_be1>; + }; + gh-secure-vm-loader@2 { compatible = "qcom,gh-secure-vm-loader"; qcom,pas-id = <35>; @@ -2017,6 +2058,13 @@ alignment = <0x0 0x400000>; }; + oem_vm_mem: oem_vm_region@f7c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf7c00000 0x0 0x4c00000>; + reusable; + alignment = <0x0 0x400000>; + }; + vm_comm_mem: vm_comm_mem_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; From a3bda1eab173815fcfd08be710aacecbbd14ab37 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Mon, 16 Sep 2024 12:44:40 +0530 Subject: [PATCH 49/67] ARM: dts: msm: Add necessary device nodes for Tuna SoC Add IMEM, debug kinfo, qcom-ramoops, minidump, va-minidump nodes for Tuna SoC. Change-Id: Ie63519b653dbcf0055edd831fa9cac3e6f77fcf6 Signed-off-by: Souradeep Chowdhury --- qcom/tuna.dtsi | 106 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 26202476..4dfce405 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -429,6 +429,25 @@ size = <0x0 0x2000000>; linux,cma-default; }; + + kinfo_mem: debug_kinfo_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; + + va_md_mem: va_md_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x1000000>; + }; + + ramoops_mem: ramoops-region { + alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; + size = <0x0 0x200000>; + no-map; + }; }; &firmware { @@ -1326,6 +1345,93 @@ reg = <0x1fc0000 0x30000>; }; + qcom,msm-imem@14680000 { + compatible = "qcom,msm-imem"; + reg = <0x14680000 0x1000>; + ranges = <0x0 0x14680000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + + modem_dsm@c98 { + compatible = "qcom,msm-imem-mss-dsm"; + reg = <0xc98 0x10>; + }; + + sys_dbg@af8 { + compatible = "qcom,msm-imem-gpu-dump-skip"; + reg = <0xb0c 0x4>; + }; + }; + + google,debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&kinfo_mem>; + }; + + mini_dump_mode { + compatible = "qcom,minidump"; + status = "ok"; + }; + + va_mini_dump { + compatible = "qcom,va-minidump"; + memory-region = <&va_md_mem>; + status = "ok"; + }; + + qcom_ramoops { + compatible = "qcom,ramoops"; + memory-region = <&ramoops_mem>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + clk_virt: interconnect@0 { compatible = "qcom,tuna-clk_virt"; #interconnect-cells = <1>; From 94a7be42b9def9b5ee05305fbf13595e7638771c Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Mon, 30 Sep 2024 10:19:54 +0530 Subject: [PATCH 50/67] ARM: dts: msm: Setting IOMMU to atomic in kera In this change switching from "bypass" to "atomic" for kera. Change-Id: I8a1141086a9f346c2613bb22ff601b69dd564131 Signed-off-by: Uttkarsh Aggarwal --- qcom/kera-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kera-usb.dtsi b/qcom/kera-usb.dtsi index 7798569b..d6d689be 100644 --- a/qcom/kera-usb.dtsi +++ b/qcom/kera-usb.dtsi @@ -37,7 +37,7 @@ reg = <0xa600000 0xd93c>; iommus = <&apps_smmu 0x40 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; dma-coherent; From 65fc98ce4f3d7ce2f451b8f5ab05dad7fd68534a Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Mon, 16 Sep 2024 19:13:59 +0530 Subject: [PATCH 51/67] ARM: dts: msm: Add WPSS glink edge node for Tuna Add WPSS glink edge node for remoteproc communication on Tuna Soc. Change-Id: Iaa54dcbfe6040ac53dde618008f5e598bb27c9d9 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 26202476..ebda7d2d 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1114,6 +1114,30 @@ /* Outputs to wpss */ qcom,smem-states = <&wpss_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <13>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "wpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "wpss"; + qcom,glink-label = "wpss"; + + qcom,wpss_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + }; + }; clocks { From 89345bbfae31f7d2b2e2f7e3bfa8475a25315a7b Mon Sep 17 00:00:00 2001 From: Ankit Sharma Date: Mon, 30 Sep 2024 12:24:41 +0530 Subject: [PATCH 52/67] ARM: dts: msm: tuna: modify capacity property Modify capacity of each cluster. The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn is used by EAS to take placement decisions. Change-Id: Ia54b1e43d0f98cac2ec68bc6d4a387d43c8c9d3f Signed-off-by: Ankit Sharma --- qcom/tuna.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 26202476..3a65083b 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -137,7 +137,7 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_2>; - capacity-dmips-mhz = <1321>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_2: l2-cache { compatible = "cache"; @@ -156,7 +156,7 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_3>; - capacity-dmips-mhz = <1321>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_3: l2-cache { compatible = "cache"; @@ -175,7 +175,7 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_4>; - capacity-dmips-mhz = <1321>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_4: l2-cache { compatible = "cache"; @@ -194,7 +194,7 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_5>; - capacity-dmips-mhz = <1321>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_5: l2-cache { compatible = "cache"; @@ -213,7 +213,7 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_6>; - capacity-dmips-mhz = <1321>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_6: l2-cache { compatible = "cache"; @@ -232,7 +232,7 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_7>; - capacity-dmips-mhz = <1935>; + capacity-dmips-mhz = <1300>; dynamic-power-coefficient = <295>; L2_7: l2-cache { compatible = "cache"; From 6f85a7d4c9a0eb4716da34669bb785cdee3c34e4 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 30 Sep 2024 15:08:17 +0530 Subject: [PATCH 53/67] ARM: dts: msm: Add chipinfo region as ext-region for cpusysvm Add chipinfo region as ext-region for cpusysvm. Change-Id: I1200495f5bb98ecbdfbba5fcdb3cb45708f63c0c Signed-off-by: Hrishabh Rajput --- qcom/tuna-reserved-memory.dtsi | 5 +++++ qcom/tuna.dtsi | 2 ++ 2 files changed, 7 insertions(+) diff --git a/qcom/tuna-reserved-memory.dtsi b/qcom/tuna-reserved-memory.dtsi index b990fbcb..1e9c039f 100644 --- a/qcom/tuna-reserved-memory.dtsi +++ b/qcom/tuna-reserved-memory.dtsi @@ -65,6 +65,11 @@ reg = <0x0 0x81ce4000 0x0 0x10000>; }; + chipinfo_mem: chipinfo_region@81cf4000 { + no-map; + reg = <0x0 0x81cf4000 0x0 0x1000>; + }; + smem_mem: smem_region@81d00000 { compatible = "qcom,smem"; reg = <0x0 0x81d00000 0x0 0x200000>; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index ef144f2d..94d10baa 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1798,6 +1798,8 @@ qcom,vmid = <50>; qcom,firmware-name = "cpusys_vm"; memory-region = <&cpusys_vm_mem>; + ext-region = <&chipinfo_mem>; + ext-label = <0x7>; }; qcom,pmic_glink_log { From bb87d71e1fa0e9a829d6ab929c36dccd6c504dce Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Wed, 18 Sep 2024 12:33:43 +0530 Subject: [PATCH 54/67] ARM: dts: msm: Add dt files for Tuna 7 SoC Add dt files for Tuna 7 SoC. Change-Id: I9e23a97046feaaa47547069fec2b05f5fd6a7b4c Signed-off-by: Shivendra Pratap --- qcom/Makefile | 2 +- qcom/platform_map.bzl | 1 + qcom/tuna7.dts | 13 +++++++++++++ qcom/tuna7.dtsi | 11 +++++++++++ 4 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 qcom/tuna7.dts create mode 100644 qcom/tuna7.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 060f3813..980bc4ed 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -52,7 +52,7 @@ sun-dtb-$(CONFIG_ARCH_SUN) += \ $(call add-overlays, $(SUN_BOARDS) $(APQ_SUN_BOARDS),$(SUN_APQ_BASE_DTB)) sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB) -TUNA_BASE_DTB += tuna.dtb +TUNA_BASE_DTB += tuna.dtb tuna7.dtb NOAPQ_TUNA_BOARDS += \ tuna-atp-overlay.dtbo \ tuna-cdp-overlay.dtbo \ diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 78f8bd5d..aed44985 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -67,6 +67,7 @@ _platform_map = { "tuna": { "dtb_list": [ {"name": "tuna.dtb"}, + {"name": "tuna7.dtb"}, ], "dtbo_list": [ { diff --git a/qcom/tuna7.dts b/qcom/tuna7.dts new file mode 100644 index 00000000..7153cabb --- /dev/null +++ b/qcom/tuna7.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna7.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Tuna 7 SoC"; + compatible = "qcom,tuna"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/tuna7.dtsi b/qcom/tuna7.dtsi new file mode 100644 index 00000000..769de07c --- /dev/null +++ b/qcom/tuna7.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Tuna 7"; + compatible = "qcom,tuna"; + qcom,msm-id = <681 0x10000>; +}; From fe23b698435f683295c4a475046deac545296d7a Mon Sep 17 00:00:00 2001 From: Jyothi bommidi Date: Tue, 24 Sep 2024 11:48:54 +0530 Subject: [PATCH 55/67] ARM: dts: msm: add touch driver device nodes for tuna Add focaltech touch driver device nodes on tuna for CDP, MTP, QRD and RCM platforms. Change-Id: Id0c3f46621ac82950a259adf09fddc1685398b09 Signed-off-by: Jyothi bommidi Signed-off-by: Anand Tarakh --- qcom/tuna-cdp.dtsi | 36 ++++++++++++++++++++++++ qcom/tuna-mtp.dtsi | 36 ++++++++++++++++++++++++ qcom/tuna-pinctrl.dtsi | 62 ++++++++++++++++++++++++++++++++++++++++++ qcom/tuna-qrd.dtsi | 39 ++++++++++++++++++++++++++ 4 files changed, 173 insertions(+) diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index 9df4770a..28e33b9d 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -2,3 +2,39 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ + +&qupv3_se4_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "st,fts"; + + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <176 0x2008>; + vdd-supply = <&L1D>; + avdd-supply = <&L22B>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + st,irq-gpio = <&tlmm 176 0x2008>; + st,irq-flags = <8>; + st,reset-gpio = <&tlmm 189 0x00>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + + st,touch-type = "primary"; + st,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <658>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 + &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; + }; +}; diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi index 9df4770a..947b1af1 100644 --- a/qcom/tuna-mtp.dtsi +++ b/qcom/tuna-mtp.dtsi @@ -2,3 +2,39 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +&qupv3_se4_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "st,fts"; + + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <176 0x2008>; + vdd-supply = <&L1D>; + avdd-supply = <&L22B>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + st,irq-gpio = <&tlmm 176 0x2008>; + st,irq-flags = <8>; + st,reset-gpio = <&tlmm 189 0x00>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + + st,touch-type = "primary"; + st,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <658>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 + &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; + }; +}; + diff --git a/qcom/tuna-pinctrl.dtsi b/qcom/tuna-pinctrl.dtsi index cfd44251..8c3ca7ff 100644 --- a/qcom/tuna-pinctrl.dtsi +++ b/qcom/tuna-pinctrl.dtsi @@ -1638,4 +1638,66 @@ drive-strength = <2>; }; }; + /* touchscreen pins */ + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio189", "gpio176"; + function = "gpio"; + }; + + config { + pins = "gpio189", "gpio176"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio189"; + function = "gpio"; + }; + + config { + pins = "gpio189"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio176"; + function = "gpio"; + }; + + config { + pins = "gpio176"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio189", "gpio176"; + function = "gpio"; + }; + + config { + pins = "gpio189", "gpio176"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + }; diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index 9df4770a..535e2a31 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -2,3 +2,42 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ + +&qupv3_se4_spi { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,touch-active = "st,fts"; + qcom,la-vm; + + st_fts@0 { + compatible = "st,fts"; + reg = <0x0>; + spi-max-frequency = <1000000>; + + interrupt-parent = <&tlmm>; + interrupts = <176 0x2008>; + vdd-supply = <&L1D>; + avdd-supply = <&L22B>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + st,irq-gpio = <&tlmm 176 0x2008>; + st,irq-flags = <8>; + st,reset-gpio = <&tlmm 189 0x00>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + + st,touch-type = "primary"; + st,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <658>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 + &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; + + }; +}; From ed005ef0658e99a17b9d683fc3249ab109ec04e0 Mon Sep 17 00:00:00 2001 From: Jigyanshu Mani Date: Tue, 1 Oct 2024 15:03:00 +0530 Subject: [PATCH 56/67] ARM: dts: msm: Define max no.of XHCI interrupters for ravelin DWC3 host and XHCI plat now communicates the maximum number of interrupters the XHCI HCD will allocate. Since platforms only require a limited number of interrupters (i.e. 3) make sure XHCI doesn't allocate more than is required. Change-Id: I9e8592c8f62562f44c760571ac1505ab80b05fc6 Signed-off-by: Jigyanshu Mani --- qcom/ravelin-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi index bd29bc5e..52a3c92d 100644 --- a/qcom/ravelin-usb.dtsi +++ b/qcom/ravelin-usb.dtsi @@ -77,6 +77,7 @@ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; tx-fifo-resize; + num-hc-interrupters = /bits/ 16 <3>; dr_mode = "otg"; maximum-speed = "super-speed"; usb-role-switch; From 7fe12752c252d3d6387dcdfd0893f47f66740d97 Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Fri, 20 Sep 2024 18:18:57 +0530 Subject: [PATCH 57/67] bindings: remoteproc: Add remoteproc bindings for Tuna Add devicetree bindings adsp,cdsp,modem for Tuna target. Change-Id: I9cfbccf7f124fdf6cace32a9628201236fbc01ad Signed-off-by: Shivendra Pratap --- bindings/remoteproc/qcom,adsp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/remoteproc/qcom,adsp.yaml b/bindings/remoteproc/qcom,adsp.yaml index fe76d57e..e5896615 100644 --- a/bindings/remoteproc/qcom,adsp.yaml +++ b/bindings/remoteproc/qcom,adsp.yaml @@ -63,6 +63,9 @@ properties: - qcom,sun-cdsp-pas - qcom,sun-modem-pas - qcom,sun-soccp-pas + - qcom,tuna-adsp-pas + - qcom,tuna-cdsp-pas + - qcom,tuna-modem-pas - qcom,parrot-adsp-pas - qcom,parrot-cdsp-pas - qcom,parrot-modem-pas From adf4dc145090b5f4ce6d2f581a345f64973f4e58 Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Fri, 6 Sep 2024 18:20:00 +0530 Subject: [PATCH 58/67] ARM: dts: qcom: Add nodes for remoteproc in Tuna dt Add remoteproc nodes for ADSP, CDSP, Modem subsystems in Tuna dt. Change-Id: Icfa7f9fbb5607f19f48256927f5b806870c62a07 Signed-off-by: Shivendra Pratap --- qcom/tuna.dtsi | 124 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 21b29384..76727e5e 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -793,6 +793,130 @@ interrupt-controller; }; + adsp_pas: remoteproc-adsp@03000000 { + compatible = "qcom,tuna-adsp-pas"; + reg = <0x03000000 0x10000>; + status = "ok"; + + cx-supply = <&VDD_LPI_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_LPI_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + qcom,qmp = <&aoss_qmp>; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "crypto_ddr"; + + firmware-name = "adsp.mdt", "adsp_dtb.mdt"; + memory-region = <&adspslpi_mem &q6_adsp_dtb_mem>; + /* Inputs from ssc */ + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + + cdsp_pas: remoteproc-cdsp@32300000 { + compatible = "qcom,tuna-cdsp-pas"; + reg = <0x32300000 0x10000>; + status = "ok"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MXC_LEVEL>; + mx-uV-uA = ; + nsp-supply = <&VDD_NSP1_LEVEL>;//To-Do : Verify if VDD_NSP1_LEVEL should be used + nsp-uV-uA = ; + reg-names = "cx","mx","nsp"; + + qcom,qmp = <&aoss_qmp>; + + memory-region = <&cdsp_mem &q6_cdsp_dtb_mem &global_sync_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + + modem_pas: remoteproc-mss@04080000 { + compatible = "qcom,tuna-modem-pas"; + reg = <0x4080000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + qcom,qmp = <&aoss_qmp>; + + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "crypto_ddr"; + + memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma &dsm_partition_1_mem &dsm_partition_2_mem>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,tuna-tlmm"; reg = <0x0f000000 0x1000000>; From 7aba41bc8d41797625364e79a08a3b3ece5605ff Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 30 Sep 2024 16:05:47 +0530 Subject: [PATCH 59/67] ARM: dts: msm: Add initial devicetree for Tuna OEMVM Add initial devicetree files for OEMVM for RUMI platform on Tuna SoC. Change-Id: Ia8a0dbeb6a345e6f5e08ba70c92b9957e27122ed Signed-off-by: Hrishabh Rajput --- qcom/Makefile | 3 +- qcom/platform_map.bzl | 9 ++ qcom/tuna-oemvm-rumi.dts | 15 +++ qcom/tuna-oemvm-rumi.dtsi | 8 ++ qcom/tuna-oemvm.dtsi | 218 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 252 insertions(+), 1 deletion(-) create mode 100644 qcom/tuna-oemvm-rumi.dts create mode 100644 qcom/tuna-oemvm-rumi.dtsi create mode 100644 qcom/tuna-oemvm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index d0475ffa..6793d500 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -212,7 +212,8 @@ endif ifeq ($(CONFIG_ARCH_TUNA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) -tuna_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += tuna-vm-rumi.dtb +tuna_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += tuna-vm-rumi.dtb \ + tuna-oemvm-rumi.dtb dtb-y += $(tuna_tuivm-dtb-y) endif endif diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index d187d777..c306113d 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -161,10 +161,19 @@ _platform_map = { {"name": "sunp-vm-hdk.dtb"}, {"name": "sun-vm-rumi.dtb"}, ], + "binary_compatible_with": ["tuna-oemvm"], }, "tuna-tuivm": { "dtb_list": [ # keep sorted + {"name": "tuna-oemvm-rumi.dtb"}, + {"name": "tuna-vm-rumi.dtb"}, + ], + }, + "tuna-oemvm": { + "dtb_list": [ + # keep sorted + {"name": "tuna-oemvm-rumi.dtb"}, {"name": "tuna-vm-rumi.dtb"}, ], }, diff --git a/qcom/tuna-oemvm-rumi.dts b/qcom/tuna-oemvm-rumi.dts new file mode 100644 index 00000000..e4658658 --- /dev/null +++ b/qcom/tuna-oemvm-rumi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/tuna-oemvm-rumi.dtsi b/qcom/tuna-oemvm-rumi.dtsi new file mode 100644 index 00000000..7cb42305 --- /dev/null +++ b/qcom/tuna-oemvm-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&arch_timer { + clock-frequency = <500000>; +}; diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi new file mode 100644 index 00000000..3bbe6c32 --- /dev/null +++ b/qcom/tuna-oemvm.dtsi @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <655 0x10000>; + interrupt-parent = <&vgic>; + + chosen { + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + + CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "QTI"; + image-name = "qcom,oemvm"; + qcom,pasid = <0x0 0x22>; + qcom,qtee-config-info = "p=3,9,39,7C,8F,97,159,7F1,CDF;"; + qcom,secdomain-ids = <49>; + qcom,primary-vm-index = <0>; + vm-uri = "vmuid/oemvm"; + vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0"; + qcom,sensitive; + + vm-attrs = "context-dump", "crash-restart"; + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + /* + * IPA address linux image is loaded at. Must be within + * first 1GB due to memory hotplug requirement. + */ + base-address = <0x0 0x88800000 >; + }; + + segments { + config_cpio = <2>; + }; + + vcpus { + config = "/cpus"; + affinity = "proxy"; + affinity-map = <0x5 0x6>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + + minidump { + vdevice-type = "minidump"; + push-compatible = "qcom,minidump_rm"; + minidump_allowed; + }; + + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + virtio-mmio@0 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x1>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x0>; + memory { + qcom,label = <0x16>; //for persist.img + #address-cells = <0x2>; + base = <0x0 0xFFEFC000>; + }; + }; + + virtio-mmio@1 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x2>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x4000>; + memory { + qcom,label = <0x13>; //for system.img + #address-cells = <0x2>; + base = <0x0 0xFFF00000>; + }; + }; + + swiotlb-shm { + vdevice-type = "shm"; + generate = "/swiotlb"; + push-compatible = "swiotlb"; + peer-default; + dma_base = <0x0 0x8000>; + memory { + qcom,label = <0x14>; + #address-cells = <0x2>; + base = <0x0 0xFFF04000>; + }; + }; + + vrtc { + vdevice-type = "vrtc-pl031"; + peer-default; + allocate-base; + }; + + }; + }; + + firmware: firmware { + qcom_scm: scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vgic: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x200000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <512>; + qcom,support-hypervisor; + }; +}; From b1c4c22e5cbe24e608d6833baca5146c727e90cc Mon Sep 17 00:00:00 2001 From: Shivnandan Kumar Date: Thu, 5 Sep 2024 20:19:44 +0530 Subject: [PATCH 60/67] ARM: dts: msm: Add CPUCP/SCMI node for Tuna Add device nodes for the cpucp mailbox, cpucp logs, and SCMI nodes for Tuna. Change-Id: If028d941d4cb812402a6617908d1bfe7ffbb6108 Signed-off-by: Shivnandan Kumar --- qcom/tuna.dtsi | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 1bfe94a4..06a7e2eb 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1641,6 +1641,64 @@ status = "disabled"; }; }; + + mmio_sram: mmio-sram@17D09400 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x17D09400 0x0 0x400>; + ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>; + + cpu_scp_lpri: scmi-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x17D09400 0x0 0x400>; + }; + }; + + cpucp: qcom,cpucp@17400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,cpucp"; + reg = <0x17d90000 0x2000>, + <0x17400000 0x10>; + reg-names = "rx", "tx"; + #mbox-cells = <1>; + interrupts = ; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&cpucp 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_qcom: protocol@80 { + reg = <0x80>; + #clock-cells = <1>; + }; + }; + + cpucp_log: qcom,cpucp_log@d8140000 { + compatible = "qcom,cpucp-log"; + reg = <0x81200000 0x10000>, <0x81210000 0x10000>; + mboxes = <&cpucp 1>; + }; + + qcom_c1dcvs: qcom,c1dcvs { + compatible = "qcom,c1dcvs-v2"; + }; + + qcom_dynpf: qcom,dynpf { + compatible = "qcom,dynpf"; + }; + + qcom_cpufreq_stats: qcom,cpufreq_stats { + compatible = "qcom,cpufreq-stats-v2"; + }; + + }; #include "tuna-gdsc.dtsi" From 54e77dd206d9ab5430be53b0f1d79f2ec5d41589 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Thu, 3 Oct 2024 13:42:25 +0530 Subject: [PATCH 61/67] ARM: dts: msm: Add UFS support for tuna Add UFS support for tuna atp, cdp, mtp and qrd platform. Change-Id: I0dddd4fe1f7b3ec8eb23d0aeb62d2aede78107c7 Signed-off-by: Manish Pandey --- qcom/tuna-cdp.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++++ qcom/tuna-mtp.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ qcom/tuna-qrd.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 177 insertions(+) diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index 28e33b9d..44461ef5 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -38,3 +38,48 @@ &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; }; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L1F>; + vdda-phy-max-microamp = <213100>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18340>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L3F>; + vccq-max-microamp = <1200000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&L5B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&S2B>; + qcom,vccq-parent-max-microamp = <210000>; + + status = "ok"; +}; diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi index 947b1af1..12fe6b41 100644 --- a/qcom/tuna-mtp.dtsi +++ b/qcom/tuna-mtp.dtsi @@ -38,3 +38,47 @@ }; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L1F>; + vdda-phy-max-microamp = <213100>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18340>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L3F>; + vccq-max-microamp = <1200000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&L5B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&S2B>; + qcom,vccq-parent-max-microamp = <210000>; + + status = "ok"; +}; diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index 535e2a31..f307bb6f 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -41,3 +41,48 @@ }; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L1F>; + vdda-phy-max-microamp = <213100>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18340>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L3F>; + vccq-max-microamp = <1200000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&L5B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&S2B>; + qcom,vccq-parent-max-microamp = <210000>; + + status = "ok"; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 76727e5e..45a8bba5 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1853,6 +1853,34 @@ status = "disabled"; }; + ice_cfg: shared_ice { + alg1 { + alg-name = "alg1"; + rx-alloc-percent = <60>; + status = "disabled"; + }; + + alg2 { + alg-name = "alg2"; + status = "disabled"; + + }; + + alg3 { + alg-name = "alg3"; + num-core = <28 28 15 13>; + status = "ok"; + }; + }; + + ufshc_dma_resv: ufshc_dma_resv_region { + /* + * Restrict IOVA mappings for UFSHC buffers to the 3 GB region + * from 0x1000 - 0xffffffff. + */ + iommu-addresses = <&ufshc_mem 0x0 0x1000>; + }; + ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, @@ -1907,6 +1935,8 @@ iommus = <&apps_smmu 0x60 0x0>; qcom,iommu-dma = "bypass"; + memory-region = <&ufshc_dma_resv>; + shared-ice-cfg = <&ice_cfg>; dma-coherent; qcom,bypass-pbl-rst-wa; @@ -1917,6 +1947,19 @@ reset-names = "rst"; status = "disabled"; + + qos0 { + mask = <0xfc>; + vote = <44>; + perf; + cpu_freq_vote = <2 5 7>; + }; + + qos1 { + mask = <0x03>; + vote = <44>; + cpu_freq_vote = <0>; + }; }; qcom_tzlog: tz-log@14680720 { From 64f855a7a0a797c9cf99cf9762213ff14f118c3e Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Thu, 3 Oct 2024 14:30:04 +0530 Subject: [PATCH 62/67] ARM: dts: msm: Add glink egde for adsp, modem and cdsp Add glink adsp, modem and cdsp device tree entries for tuna. Change-Id: Ibe643bde5e781f22b0cdbadc9bbbe98e66dbd222 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 76727e5e..14311677 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -832,6 +832,42 @@ /* Outputs to turing */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + remoteproc_adsp_glink: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,net-id = <2>; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + + qcom,no-wake-svc = <0x190>; + }; + + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; + }; }; cdsp_pas: remoteproc-cdsp@32300000 { @@ -874,6 +910,42 @@ /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + remoteproc_cdsp_glink: glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "cdsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12 + 0xF00 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-cores = <0 1>; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; + }; }; modem_pas: remoteproc-mss@04080000 { @@ -915,6 +987,34 @@ /* Outputs to mss */ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + }; }; tlmm: pinctrl@f000000 { From 87a2090caad22a2973bbf422fefafd62d896d30e Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Thu, 3 Oct 2024 11:51:53 +0530 Subject: [PATCH 63/67] ARM: dts: qcom: Add platform support for VMs on Tuna Add support for platforms like ATP, CDP, MTP, QRD and RCM for TUIVM and OEMVM on Tuna. Also, add support for additional Tuna variant. Change-Id: Ie7a6c542c7d31db5b823ae10db714ddc43330598 Signed-off-by: Hrishabh Rajput --- qcom/Makefile | 18 +++++++++++++++++- qcom/platform_map.bzl | 32 ++++++++++++++++++++++++++++++++ qcom/tuna-oemvm-atp.dts | 17 +++++++++++++++++ qcom/tuna-oemvm-atp.dtsi | 7 +++++++ qcom/tuna-oemvm-cdp.dts | 17 +++++++++++++++++ qcom/tuna-oemvm-cdp.dtsi | 7 +++++++ qcom/tuna-oemvm-mtp-kiwi.dts | 16 ++++++++++++++++ qcom/tuna-oemvm-mtp-kiwi.dtsi | 7 +++++++ qcom/tuna-oemvm-mtp-qmp1000.dts | 16 ++++++++++++++++ qcom/tuna-oemvm-mtp-qmp1000.dtsi | 7 +++++++ qcom/tuna-oemvm-mtp.dts | 16 ++++++++++++++++ qcom/tuna-oemvm-mtp.dtsi | 7 +++++++ qcom/tuna-oemvm-qrd.dts | 16 ++++++++++++++++ qcom/tuna-oemvm-qrd.dtsi | 7 +++++++ qcom/tuna-oemvm-rcm-kiwi.dts | 16 ++++++++++++++++ qcom/tuna-oemvm-rcm-kiwi.dtsi | 7 +++++++ qcom/tuna-oemvm-rcm.dts | 16 ++++++++++++++++ qcom/tuna-oemvm-rcm.dtsi | 7 +++++++ qcom/tuna-vm-atp.dts | 17 +++++++++++++++++ qcom/tuna-vm-atp.dtsi | 7 +++++++ qcom/tuna-vm-cdp.dts | 17 +++++++++++++++++ qcom/tuna-vm-cdp.dtsi | 7 +++++++ qcom/tuna-vm-mtp-kiwi.dts | 16 ++++++++++++++++ qcom/tuna-vm-mtp-kiwi.dtsi | 7 +++++++ qcom/tuna-vm-mtp-qmp1000.dts | 16 ++++++++++++++++ qcom/tuna-vm-mtp-qmp1000.dtsi | 7 +++++++ qcom/tuna-vm-mtp.dts | 16 ++++++++++++++++ qcom/tuna-vm-mtp.dtsi | 7 +++++++ qcom/tuna-vm-qrd.dts | 16 ++++++++++++++++ qcom/tuna-vm-qrd.dtsi | 7 +++++++ qcom/tuna-vm-rcm-kiwi.dts | 16 ++++++++++++++++ qcom/tuna-vm-rcm-kiwi.dtsi | 7 +++++++ qcom/tuna-vm-rcm.dts | 16 ++++++++++++++++ qcom/tuna-vm-rcm.dtsi | 7 +++++++ qcom/tuna-vm.dtsi | 2 +- 35 files changed, 422 insertions(+), 2 deletions(-) create mode 100644 qcom/tuna-oemvm-atp.dts create mode 100644 qcom/tuna-oemvm-atp.dtsi create mode 100644 qcom/tuna-oemvm-cdp.dts create mode 100644 qcom/tuna-oemvm-cdp.dtsi create mode 100644 qcom/tuna-oemvm-mtp-kiwi.dts create mode 100644 qcom/tuna-oemvm-mtp-kiwi.dtsi create mode 100644 qcom/tuna-oemvm-mtp-qmp1000.dts create mode 100644 qcom/tuna-oemvm-mtp-qmp1000.dtsi create mode 100644 qcom/tuna-oemvm-mtp.dts create mode 100644 qcom/tuna-oemvm-mtp.dtsi create mode 100644 qcom/tuna-oemvm-qrd.dts create mode 100644 qcom/tuna-oemvm-qrd.dtsi create mode 100644 qcom/tuna-oemvm-rcm-kiwi.dts create mode 100644 qcom/tuna-oemvm-rcm-kiwi.dtsi create mode 100644 qcom/tuna-oemvm-rcm.dts create mode 100644 qcom/tuna-oemvm-rcm.dtsi create mode 100644 qcom/tuna-vm-atp.dts create mode 100644 qcom/tuna-vm-atp.dtsi create mode 100644 qcom/tuna-vm-cdp.dts create mode 100644 qcom/tuna-vm-cdp.dtsi create mode 100644 qcom/tuna-vm-mtp-kiwi.dts create mode 100644 qcom/tuna-vm-mtp-kiwi.dtsi create mode 100644 qcom/tuna-vm-mtp-qmp1000.dts create mode 100644 qcom/tuna-vm-mtp-qmp1000.dtsi create mode 100644 qcom/tuna-vm-mtp.dts create mode 100644 qcom/tuna-vm-mtp.dtsi create mode 100644 qcom/tuna-vm-qrd.dts create mode 100644 qcom/tuna-vm-qrd.dtsi create mode 100644 qcom/tuna-vm-rcm-kiwi.dts create mode 100644 qcom/tuna-vm-rcm-kiwi.dtsi create mode 100644 qcom/tuna-vm-rcm.dts create mode 100644 qcom/tuna-vm-rcm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 6793d500..cfa2af0d 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -213,7 +213,23 @@ endif ifeq ($(CONFIG_ARCH_TUNA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) tuna_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += tuna-vm-rumi.dtb \ - tuna-oemvm-rumi.dtb + tuna-vm-atp.dtb \ + tuna-vm-cdp.dtb \ + tuna-vm-mtp.dtb \ + tuna-vm-mtp-kiwi.dtb \ + tuna-vm-mtp-qmp1000.dtb \ + tuna-vm-qrd.dtb \ + tuna-vm-rcm.dtb \ + tuna-vm-rcm-kiwi.dtb \ + tuna-oemvm-rumi.dtb \ + tuna-oemvm-atp.dtb \ + tuna-oemvm-cdp.dtb \ + tuna-oemvm-mtp.dtb \ + tuna-oemvm-mtp-kiwi.dtb \ + tuna-oemvm-mtp-qmp1000.dtb \ + tuna-oemvm-qrd.dtb \ + tuna-oemvm-rcm.dtb \ + tuna-oemvm-rcm-kiwi.dtb dtb-y += $(tuna_tuivm-dtb-y) endif endif diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index c306113d..d70229e6 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -166,14 +166,46 @@ _platform_map = { "tuna-tuivm": { "dtb_list": [ # keep sorted + {"name": "tuna-oemvm-atp.dtb"}, + {"name": "tuna-oemvm-cdp.dtb"}, + {"name": "tuna-oemvm-mtp.dtb"}, + {"name": "tuna-oemvm-mtp-kiwi.dtb"}, + {"name": "tuna-oemvm-mtp-qmp1000.dtb"}, + {"name": "tuna-oemvm-qrd.dtb"}, + {"name": "tuna-oemvm-rcm.dtb"}, + {"name": "tuna-oemvm-rcm-kiwi.dtb"}, {"name": "tuna-oemvm-rumi.dtb"}, + {"name": "tuna-vm-atp.dtb"}, + {"name": "tuna-vm-cdp.dtb"}, + {"name": "tuna-vm-mtp.dtb"}, + {"name": "tuna-vm-mtp-kiwi.dtb"}, + {"name": "tuna-vm-mtp-qmp1000.dtb"}, + {"name": "tuna-vm-qrd.dtb"}, + {"name": "tuna-vm-rcm.dtb"}, + {"name": "tuna-vm-rcm-kiwi.dtb"}, {"name": "tuna-vm-rumi.dtb"}, ], }, "tuna-oemvm": { "dtb_list": [ # keep sorted + {"name": "tuna-oemvm-atp.dtb"}, + {"name": "tuna-oemvm-cdp.dtb"}, + {"name": "tuna-oemvm-mtp.dtb"}, + {"name": "tuna-oemvm-mtp-kiwi.dtb"}, + {"name": "tuna-oemvm-mtp-qmp1000.dtb"}, + {"name": "tuna-oemvm-qrd.dtb"}, + {"name": "tuna-oemvm-rcm.dtb"}, + {"name": "tuna-oemvm-rcm-kiwi.dtb"}, {"name": "tuna-oemvm-rumi.dtb"}, + {"name": "tuna-vm-atp.dtb"}, + {"name": "tuna-vm-cdp.dtb"}, + {"name": "tuna-vm-mtp.dtb"}, + {"name": "tuna-vm-mtp-kiwi.dtb"}, + {"name": "tuna-vm-mtp-qmp1000.dtb"}, + {"name": "tuna-vm-qrd.dtb"}, + {"name": "tuna-vm-rcm.dtb"}, + {"name": "tuna-vm-rcm-kiwi.dtb"}, {"name": "tuna-vm-rumi.dtb"}, ], }, diff --git a/qcom/tuna-oemvm-atp.dts b/qcom/tuna-oemvm-atp.dts new file mode 100644 index 00000000..30c71167 --- /dev/null +++ b/qcom/tuna-oemvm-atp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + + qcom,board-id = <33 0>; +}; diff --git a/qcom/tuna-oemvm-atp.dtsi b/qcom/tuna-oemvm-atp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-oemvm-atp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-oemvm-cdp.dts b/qcom/tuna-oemvm-cdp.dts new file mode 100644 index 00000000..66a89247 --- /dev/null +++ b/qcom/tuna-oemvm-cdp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + + qcom,board-id = <1 0>; +}; diff --git a/qcom/tuna-oemvm-cdp.dtsi b/qcom/tuna-oemvm-cdp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-oemvm-cdp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-oemvm-mtp-kiwi.dts b/qcom/tuna-oemvm-mtp-kiwi.dts new file mode 100644 index 00000000..262ca733 --- /dev/null +++ b/qcom/tuna-oemvm-mtp-kiwi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-mtp-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM MTP + kiwi WLAN"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,board-id = <8 2>; +}; diff --git a/qcom/tuna-oemvm-mtp-kiwi.dtsi b/qcom/tuna-oemvm-mtp-kiwi.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-oemvm-mtp-kiwi.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-oemvm-mtp-qmp1000.dts b/qcom/tuna-oemvm-mtp-qmp1000.dts new file mode 100644 index 00000000..76a8ba06 --- /dev/null +++ b/qcom/tuna-oemvm-mtp-qmp1000.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-mtp-qmp1000.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM MTP QMP1000"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,board-id = <8 1>; +}; diff --git a/qcom/tuna-oemvm-mtp-qmp1000.dtsi b/qcom/tuna-oemvm-mtp-qmp1000.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-oemvm-mtp-qmp1000.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-oemvm-mtp.dts b/qcom/tuna-oemvm-mtp.dts new file mode 100644 index 00000000..76d8cfa0 --- /dev/null +++ b/qcom/tuna-oemvm-mtp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/qcom/tuna-oemvm-mtp.dtsi b/qcom/tuna-oemvm-mtp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-oemvm-mtp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-oemvm-qrd.dts b/qcom/tuna-oemvm-qrd.dts new file mode 100644 index 00000000..2fc3c353 --- /dev/null +++ b/qcom/tuna-oemvm-qrd.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/qcom/tuna-oemvm-qrd.dtsi b/qcom/tuna-oemvm-qrd.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-oemvm-qrd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-oemvm-rcm-kiwi.dts b/qcom/tuna-oemvm-rcm-kiwi.dts new file mode 100644 index 00000000..fda57bf8 --- /dev/null +++ b/qcom/tuna-oemvm-rcm-kiwi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-rcm-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM RCM + kiwi WLAN"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,board-id = <21 1>; +}; diff --git a/qcom/tuna-oemvm-rcm-kiwi.dtsi b/qcom/tuna-oemvm-rcm-kiwi.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-oemvm-rcm-kiwi.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-oemvm-rcm.dts b/qcom/tuna-oemvm-rcm.dts new file mode 100644 index 00000000..07298e6a --- /dev/null +++ b/qcom/tuna-oemvm-rcm.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-oemvm.dtsi" +#include "tuna-oemvm-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna OEMVM RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,board-id = <21 0>; +}; diff --git a/qcom/tuna-oemvm-rcm.dtsi b/qcom/tuna-oemvm-rcm.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-oemvm-rcm.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm-atp.dts b/qcom/tuna-vm-atp.dts new file mode 100644 index 00000000..f2552821 --- /dev/null +++ b/qcom/tuna-vm-atp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + + qcom,board-id = <33 0>; +}; diff --git a/qcom/tuna-vm-atp.dtsi b/qcom/tuna-vm-atp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-vm-atp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm-cdp.dts b/qcom/tuna-vm-cdp.dts new file mode 100644 index 00000000..c1918910 --- /dev/null +++ b/qcom/tuna-vm-cdp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + + qcom,board-id = <1 0>; +}; diff --git a/qcom/tuna-vm-cdp.dtsi b/qcom/tuna-vm-cdp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-vm-cdp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm-mtp-kiwi.dts b/qcom/tuna-vm-mtp-kiwi.dts new file mode 100644 index 00000000..b7e8fbfe --- /dev/null +++ b/qcom/tuna-vm-mtp-kiwi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-mtp-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,board-id = <8 2>; +}; diff --git a/qcom/tuna-vm-mtp-kiwi.dtsi b/qcom/tuna-vm-mtp-kiwi.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-vm-mtp-kiwi.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm-mtp-qmp1000.dts b/qcom/tuna-vm-mtp-qmp1000.dts new file mode 100644 index 00000000..c4a703c7 --- /dev/null +++ b/qcom/tuna-vm-mtp-qmp1000.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-mtp-qmp1000.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP QMP1000"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,board-id = <8 1>; +}; diff --git a/qcom/tuna-vm-mtp-qmp1000.dtsi b/qcom/tuna-vm-mtp-qmp1000.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-vm-mtp-qmp1000.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm-mtp.dts b/qcom/tuna-vm-mtp.dts new file mode 100644 index 00000000..d9c1e35b --- /dev/null +++ b/qcom/tuna-vm-mtp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/qcom/tuna-vm-mtp.dtsi b/qcom/tuna-vm-mtp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-vm-mtp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm-qrd.dts b/qcom/tuna-vm-qrd.dts new file mode 100644 index 00000000..e6393401 --- /dev/null +++ b/qcom/tuna-vm-qrd.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/qcom/tuna-vm-qrd.dtsi b/qcom/tuna-vm-qrd.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-vm-qrd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm-rcm-kiwi.dts b/qcom/tuna-vm-rcm-kiwi.dts new file mode 100644 index 00000000..e71f799e --- /dev/null +++ b/qcom/tuna-vm-rcm-kiwi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-rcm-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RCM + kiwi WLAN"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,board-id = <21 1>; +}; diff --git a/qcom/tuna-vm-rcm-kiwi.dtsi b/qcom/tuna-vm-rcm-kiwi.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-vm-rcm-kiwi.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm-rcm.dts b/qcom/tuna-vm-rcm.dts new file mode 100644 index 00000000..e550df1c --- /dev/null +++ b/qcom/tuna-vm-rcm.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tuna-vm.dtsi" +#include "tuna-vm-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,board-id = <21 0>; +}; diff --git a/qcom/tuna-vm-rcm.dtsi b/qcom/tuna-vm-rcm.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/tuna-vm-rcm.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 634f9aaf..12ededd4 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -9,7 +9,7 @@ / { #address-cells = <0x2>; #size-cells = <0x2>; - qcom,msm-id = <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>; interrupt-parent = <&vgic>; chosen { From 1d284d8a8d81eba78e4cdfeed326c2cad6bfc8b4 Mon Sep 17 00:00:00 2001 From: Kartikey Arora Date: Fri, 4 Oct 2024 17:59:03 +0530 Subject: [PATCH 64/67] ARM: dts: msm: Update wpss rproc node for tuna Update wpss rproc node for tuna with modified WPSS image address in PIL region. Change-Id: I9f1b885163c51bf279f96a27b389695b83b44019 CRs-Fixed: 3941237 Signed-off-by: Kartikey Arora --- qcom/tuna.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 14311677..20b31971 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1319,9 +1319,9 @@ restrict-access; }; - wpss_pas: remoteproc-wpss@a3500000 { + wpss_pas: remoteproc-wpss@97000000 { compatible = "qcom,tuna-wpss-pas"; - reg = <0xa3500000 0x10000>; + reg = <0x97000000 0x10000>; status = "ok"; memory-region = <&wpss_mem>; From 917bbed7571e907207f8ba08603ddf4505cb9f93 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 25 Sep 2024 11:03:36 +0530 Subject: [PATCH 65/67] ARM: dts: msm: Add gcc qcom-dummycc support for TVM on Tuna For upstream and tvm, qup common driver uses gcc phandles which are common in dt and to avoid qup driver probe failure, add gcc qcom-dummycc support as they are nop. This helps in avoiding additional logic in qup driver to not conditionalize based on variant. Change-Id: I770a2a3c0e31138891b3e298ccff8e2934ae91a1 Signed-off-by: Anaadi Mishra --- qcom/tuna-vm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 12ededd4..830368e7 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -205,6 +205,13 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + virtio-mmio { wakeup-source; }; From 9f5f8fa3f048c3f7f7da83d9f1af70aa8628f430 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Thu, 3 Oct 2024 18:22:43 +0530 Subject: [PATCH 66/67] bindings: nvmem: Add tuna and kera qfprom compat string Add the soc-specific compatible string for qfprom to support keepout regions on kera and tuna SoC. Change-Id: Ia8196126bc995614fb5c72216cdd322a1b9d1613 Signed-off-by: Souradeep Chowdhury --- bindings/nvmem/qcom,qfprom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/nvmem/qcom,qfprom.yaml b/bindings/nvmem/qcom,qfprom.yaml index 4dc6d9bb..93199018 100644 --- a/bindings/nvmem/qcom,qfprom.yaml +++ b/bindings/nvmem/qcom,qfprom.yaml @@ -31,6 +31,8 @@ properties: - qcom,sm6115-qfprom - qcom,sun-qfprom - qcom,ravelin-qfprom + - qcom,tuna-qfprom + - qcom,kera-qfprom - const: qcom,qfprom reg: From 3bd6e5e6d024322e8d5acace145343efb5159451 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Thu, 3 Oct 2024 12:21:51 +0530 Subject: [PATCH 67/67] bindings: remoteproc: Add remoteproc bindings for Kera Add devicetree bindings adsp,cdsp,modem for Kera target. Change-Id: I7c351896c9ae0e271ac6bf9ff52b4ba803cff720 Signed-off-by: Souradeep Chowdhury --- bindings/remoteproc/qcom,adsp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/remoteproc/qcom,adsp.yaml b/bindings/remoteproc/qcom,adsp.yaml index e5896615..e5b00374 100644 --- a/bindings/remoteproc/qcom,adsp.yaml +++ b/bindings/remoteproc/qcom,adsp.yaml @@ -70,6 +70,9 @@ properties: - qcom,parrot-cdsp-pas - qcom,parrot-modem-pas - qcom,parrot-wpss-pas + - qcom,kera-adsp-pas + - qcom,kera-cdsp-pas + - qcom,kera-modem-pas - qcom,ravelin-adsp-pas - qcom,ravelin-modem-pas - qcom,ravelin-wpss-pas