ARM: dts: msm: Add support for Sun GPU
Add the devicetree files for the GPU on Sun devices. Change-Id: Iaf7a19eb5e2c6c215e838ae1bfa3b01916c804d9 Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
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132
gpu/sun-gpu-pwrlevels.dtsi
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132
gpu/sun-gpu-pwrlevels.dtsi
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&msm_gpu {
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/* Power levels */
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <9>;
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qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <967000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <930000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <900000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <832000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS_L2 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <779000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <734000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <10>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <607000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* Low_SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <443000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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};
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/* Low_SVS_D1 */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <342000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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};
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/* Low_SVS_D2 */
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <222000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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};
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};
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};
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};
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