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ARM: dts: msm: enable hw-fences in display driver for Sun

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Enable the use of hw-fences as the preferred synchronization
primitives in the display driver for Sun target.

Change-Id: I6f7d769f0a9002d27e68bac55095a3958587e47b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This commit is contained in:
Christina Oliveira
2024-01-30 14:14:50 -08:00
parent 945dccd0fd
commit 672405ce89
2 changed files with 7 additions and 0 deletions
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5
bindings/sde.txt
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@@ -103,6 +103,10 @@ Optional properties:
-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
- qcom,sde-hw-version: A u32 value indicates the MDSS hw version - qcom,sde-hw-version: A u32 value indicates the MDSS hw version
- qcom,hw-fence-sw-version: A u32 value to indicate the hw fencing version. If set to a value
greather than zero, driver will attempt to enable the feature (if
supported by the HW). Otherwise, if this value is not set or set
to zero, feature will remain disabled.
- qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. - qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp.
- qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. - qcom,sde-mixer-size: A u32 value indicates the address range for each mixer.
- qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. - qcom,sde-ctl-size: A u32 value indicates the address range for each ctl.
@@ -718,6 +722,7 @@ Example:
#power-domain-cells = <0>; #power-domain-cells = <0>;
qcom,sde-hw-version = <0x70000000>; qcom,sde-hw-version = <0x70000000>;
qcom,hw-fence-sw-version = <0x1>;
qcom,sde-emulated-env; qcom,sde-emulated-env;
qcom,sde-off = <0x1000>; qcom,sde-off = <0x1000>;
qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400

2
display/sun-sde.dtsi
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@@ -219,6 +219,8 @@
clock-rate = <0 0 575000000 575000000 19200000 575000000>; clock-rate = <0 0 575000000 575000000 19200000 575000000>;
clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; clock-max-rate = <0 0 575000000 575000000 19200000 575000000>;
qcom,hw-fence-sw-version = <0x1>;
vdd-supply = <&disp_cc_mdss_core_gdsc>; vdd-supply = <&disp_cc_mdss_core_gdsc>;
mmcx-supply = <&VDD_MMCX_LEVEL>; mmcx-supply = <&VDD_MMCX_LEVEL>;