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ARM: dts: msm: Add support of mosi, clk gpios and doorbell interrupt

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Add mosi, clock gpios and doorbell interrupt for Q2SPI wakeup support
for Sun.

Change-Id: I199a1cd41b8e69799f3fc8cc1caebd67406e8744
Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
This commit is contained in:
Jyothi Kumar Seerapu
2024-02-06 00:35:11 +05:30
parent e2c3fd4898
commit 671acbec76
1 changed files with 5 additions and 2 deletions
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7
qcom/sun-qupv3.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
&soc { &soc {
@@ -962,7 +962,8 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg-names = "se_phys"; reg-names = "se_phys";
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 23 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk"; clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnect-names = "qup-core", "qup-config", "qup-memory";
@@ -970,6 +971,8 @@
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
mosi-pin = <&tlmm 21 0>;
clk-pin = <&tlmm 22 0>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_q2spi_mosi_active>, <&qupv3_se13_q2spi_miso_active>, pinctrl-0 = <&qupv3_se13_q2spi_mosi_active>, <&qupv3_se13_q2spi_miso_active>,
<&qupv3_se13_q2spi_clk_active>, <&qupv3_se13_q2spi_doorbell_active>; <&qupv3_se13_q2spi_clk_active>, <&qupv3_se13_q2spi_doorbell_active>;