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ARM: dts: msm: Add support for clock nodes and gdsc's for SM6150

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Add support for cpufreq_hw, clock controller nodes and their
corresponding gdsc's for SM6150.

Change-Id: I7d64cbe80eb7f10277acce0a0c91fb788c3c99dc
Signed-off-by: Chintan Kothari <quic_ckothari@quicinc.com>
This commit is contained in:
Chintan Kothari
2025-03-06 13:57:37 +05:30
parent 8adbf5b537
commit 63ca55d666
2 changed files with 430 additions and 0 deletions
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235
qcom/sm6150.dtsi
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@@ -4,8 +4,14 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,camcc-sm6150.h>
#include <dt-bindings/clock/qcom,dispcc-sm6150.h>
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
#include <dt-bindings/clock/qcom,gpucc-sm6150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/clock/qcom,videocc-sm6150.h>
/ {
model = "Qualcomm Technologies, Inc. SM6150";
@@ -43,6 +49,7 @@
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
@@ -66,6 +73,7 @@
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
@@ -84,6 +92,7 @@
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
@@ -101,6 +110,7 @@
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
@@ -118,6 +128,7 @@
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
@@ -135,6 +146,7 @@
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
@@ -152,6 +164,7 @@
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1 2>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
@@ -170,6 +183,7 @@
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1 2>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -427,6 +441,12 @@
<CONTROL_TCS 1>,
<FAST_PATH_TCS 0>;
};
rpmhcc: qcom,rpmhclk {
compatible = "qcom,sm6150-rpmh-clk";
#clock-cells = <1>;
status = "okay";
};
};
};
@@ -540,6 +560,126 @@
};
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
clock-frequency = <38400000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
};
gcc: clock-controller@100000 {
compatible = "qcom,sm6150-gcc", "syscon";
reg = <0x100000 0x1f0000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk";
protected-clocks = <GCC_SDR_CORE_CLK>,
<GCC_SDR_WR0_MEM_CLK>,
<GCC_SDR_WR1_MEM_CLK>,
<GCC_SDR_WR2_MEM_CLK>,
<GCC_SDR_CSR_HCLK>,
<GCC_SDR_PRI_MI2S_CLK>,
<GCC_SDR_SEC_MI2S_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sm6150-camcc", "syscon";
reg = <0xad00000 0x10000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sm6150-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo", "gpll0";
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@5090000 {
compatible = "qcom,sm6150-gpucc", "syscon";
reg = <0x5090000 0x9000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "bi_tcxo", "gpll0";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@ab00000 {
compatible = "qcom,sm6150-videocc", "syscon";
reg = <0xab00000 0x10000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
apsscc: syscon@182a0000 {
compatible = "syscon";
reg = <0x182a0000 0x1c>;
};
mccc: syscon@90b0000 {
compatible = "syscon";
reg = <0x90b0000 0x54>;
};
debugcc: debug-clock-controller@0 {
compatible = "qcom,sm6150-debugcc";
qcom,apsscc = <&apsscc>;
qcom,camcc = <&camcc>;
qcom,dispcc = <&dispcc>;
qcom,gcc = <&gcc>;
qcom,gpucc = <&gpucc>;
qcom,mccc = <&mccc>;
qcom,videocc = <&videocc>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo_clk_src";
#clock-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <2>;
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
@@ -756,9 +896,104 @@
};
#include "sm6150-regulator.dtsi"
#include "sm6150-gdsc.dtsi"
#include "sm6150-pinctrl.dtsi"
#include "msm-rdbg.dtsi"
&tlmm {
status = "okay";
};
&emac_gdsc {
status = "ok";
};
&pcie_0_gdsc {
status = "ok";
};
&ufs_phy_gdsc {
status = "ok";
};
&usb30_prim_gdsc {
status = "ok";
};
&usb20_sec_gdsc {
status = "ok";
};
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
status = "ok";
};
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
status = "ok";
};
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
status = "ok";
};
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
status = "ok";
};
&titan_top_gdsc {
parent-supply = <&VDD_MX_LEVEL>;
status = "ok";
};
&bps_gdsc {
qcom,support-hw-trigger;
status = "ok";
};
&ife_0_gdsc {
status = "ok";
};
&ife_1_gdsc {
status = "ok";
};
&ipe_0_gdsc {
qcom,support-hw-trigger;
status = "ok";
};
&mdss_core_gdsc {
status = "ok";
};
&gpu_cx_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gpu_gx_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&vcodec0_gdsc {
qcom,support-hw-trigger;
status = "ok";
};
&venus_gdsc {
status = "ok";
};