diff --git a/qcom/sm6150-gdsc.dtsi b/qcom/sm6150-gdsc.dtsi new file mode 100644 index 00000000..4ab74042 --- /dev/null +++ b/qcom/sm6150-gdsc.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@106004 { + compatible = "qcom,gdsc"; + reg = <0x106004 0x4>; + regulator-name = "emac_gdsc"; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + reg = <0x16b004 0x4>; + regulator-name = "pcie_0_gdsc"; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + reg = <0x177004 0x4>; + regulator-name = "ufs_phy_gdsc"; + status = "disabled"; + }; + + usb20_sec_gdsc: qcom,gdsc@1a6004 { + compatible = "qcom,gdsc"; + reg = <0x1a6004 0x4>; + regulator-name = "usb20_sec_gdsc"; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + reg = <0x10f004 0x4>; + regulator-name = "usb30_prim_gdsc"; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + reg = <0x17d040 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + reg = <0x17d044 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + reg = <0x17d048 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + reg = <0x17d04c 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + reg = <0x17d050 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + reg = <0x17d054 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + reg = <0x17d058 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + titan_top_gdsc: qcom,gdsc@ad0b134 { + compatible = "qcom,gdsc"; + reg = <0xad0b134 0x4>; + regulator-name = "titan_top_gdsc"; + status = "disabled"; + }; + + bps_gdsc: qcom,gdsc@ad06004 { + compatible = "qcom,gdsc"; + reg = <0xad06004 0x4>; + regulator-name = "bps_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + reg = <0xad09004 0x4>; + regulator-name = "ife_0_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + reg = <0xad0a004 0x4>; + regulator-name = "ife_1_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + reg = <0xad07004 0x4>; + regulator-name = "ipe_0_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + reg = <0xaf03000 0x4>; + regulator-name = "mdss_core_gdsc"; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@5091540 { + compatible = "syscon"; + reg = <0x5091540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@509106c { + compatible = "qcom,gdsc"; + reg = <0x509106c 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@509100c { + compatible = "qcom,gdsc"; + reg = <0x509100c 0x4>; + regulator-name = "gpu_gx_gdsc"; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + vcodec0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + reg = <0xab00874 0x4>; + regulator-name = "vcodec0_gdsc"; + status = "disabled"; + }; + + venus_gdsc: qcom,gdsc@ab00814 { + compatible = "qcom,gdsc"; + reg = <0xab00814 0x4>; + regulator-name = "venus_gdsc"; + status = "disabled"; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index a2c9e93d..4dd1255f 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -4,8 +4,14 @@ */ #include +#include +#include +#include +#include +#include #include #include +#include / { model = "Qualcomm Technologies, Inc. SM6150"; @@ -43,6 +49,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -66,6 +73,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_100: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -84,6 +92,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_200: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -101,6 +110,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_300: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -118,6 +128,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_400: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -135,6 +146,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_500: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -152,6 +164,7 @@ dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1 2>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "arm,arch-cache"; @@ -170,6 +183,7 @@ dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1 2>; L2_700: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; @@ -427,6 +441,12 @@ , ; }; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,sm6150-rpmh-clk"; + #clock-cells = <1>; + status = "okay"; + }; }; }; @@ -540,6 +560,126 @@ }; }; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,sm6150-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + protected-clocks = , + , + , + , + , + , + ; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm6150-camcc", "syscon"; + reg = <0xad00000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm6150-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5090000 { + compatible = "qcom,sm6150-gpucc", "syscon"; + reg = <0x5090000 0x9000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "bi_tcxo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm6150-videocc", "syscon"; + reg = <0xab00000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm6150-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,mccc = <&mccc>; + qcom,videocc = <&videocc>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x18323000 0x1400>, <0x18325800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <2>; + }; + cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; @@ -756,9 +896,104 @@ }; #include "sm6150-regulator.dtsi" +#include "sm6150-gdsc.dtsi" #include "sm6150-pinctrl.dtsi" #include "msm-rdbg.dtsi" &tlmm { status = "okay"; }; + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb20_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&titan_top_gdsc { + parent-supply = <&VDD_MX_LEVEL>; + status = "ok"; +}; + +&bps_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + status = "ok"; +}; + +&ife_1_gdsc { + status = "ok"; +}; + +&ipe_0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&venus_gdsc { + status = "ok"; +};