Merge 27465abcc4 on remote branch

Change-Id: I2a69dbef186157d10e5ac1e6e0799d00d5696ee6

bindings/arm/msm/msm.yaml

@@ -126,6 +126,13 @@ properties:
               - qcom,rumi
           - const: qcom,tuna
 
+      - description: Qualcomm Technologies, Inc. KERA
+        items:
+          - enum:
+              - qcom,kera-rumi
+              - qcom,rumi
+          - const: qcom,kera
+
       - description: Qualcomm Technologies, Inc. MONACO
         items:
           - enum:

bindings/arm/msm/msm_hang_detect.yaml

@@ -7,7 +7,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 title: QTI MSM Core Hang Detection
 
 maintainers:
-  - Elliot Berman <eberman@quicinc.com>
+  - Elliot Berman <quic_eberman@quicinc.com>
 
 description: |
   Core Hang Detection provides the three sysfs entries for configuring

bindings/arm/msm/qcom,qfprom-sys.yaml

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,qfprom-sys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. QFPROM_SYS driver
+
+maintainers:
+  - Naman Jain <quic_namajain@quicinc.com>
+
+description: |+
+  QFPROM_SYS provides access to the nvmem cells to the user space.
+  The driver exports the cell values as sysfs entries.
+
+properties:
+  compatible:
+    const: qcom,qfprom-sys
+
+  nvmem-cell-names:
+    description: array of strings for cell names
+
+  nvmem-cells:
+    description: phandle to particular cell from provider
+
+required:
+  - compatible
+  - nvmem-cell-names
+  - nvmem-cells
+
+additionalProperties: false
+
+examples:
+  - |
+    qfprom@0 {
+        compatible = "qcom,qfprom-sys";
+        nvmem-cells = <&tsens_calibration1>, <&tsens_calibration2>;
+        nvmem-cell-names = "calibration1", "calibration2";
+    };
+...

bindings/arm/msm/rpm.yaml

@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/rpm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. RPM-SMD device
+
+maintainers:
+  - Raghavendra Kakarla <quic_rkakarla@quicinc.com>
+
+description:
+  RPM is a dedicated hardware engine for managing shared SoC resources,
+  which includes buses, clocks, power rails, etc.  The goal of RPM is
+  to achieve the maximum power savings while satisfying the SoC's
+  operational and performance requirements.  RPM accepts resource
+  requests from multiple RPM masters.  It arbitrates and aggregates
+  the requests, and configures the shared resources. The RPM masters
+  are the application processor, the modem processor, as well as hardware
+  accelerators. The RPM driver communicates with the hardware engine using
+  SMD.
+
+properties:
+  compatible:
+    items:
+      - const: qcom,rpm-smd
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+
+    rpm_bus: qcom,rpm-smd {
+            compatible = "qcom,rpm-smd";
+            interrupts = <IPCC_CLIENT_AOP
+                          IPCC_MPROC_SIGNAL_GLINK_QMP
+                          IRQ_TYPE_EDGE_RISING>;
+    };

bindings/input/qcom,qpnp-power-on.yaml

@@ -0,0 +1,317 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/qcom,qpnp-power-on.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. QPNP Power-on PMIC Peripheral
+
+maintainers:
+  - David Collins <quic_collinsd@quicinc.com>
+
+description: >
+  qpnp-power-on devices support the power-on (PON) peripheral found on
+  Qualcomm Technologies, Inc. PMICs. The supported functionality includes power
+  on/off reason, kerelease detection, PMIC reset configurations and other
+  PON specific features. The PON module supports multiple physical power-on
+  (KPDPWR_N, CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources. This
+  peripheral is connected to the host processor via the SPMI interface.y press/
+
+properties:
+  compatible:
+    const: qcom,qpnp-power-on
+
+  reg:
+    description: Specifies the SPMI base address for this
+                 PON (power-on) peripheral. For PMICs that have
+                 PON peripheral (GEN3) split into PON_HLOS and
+                 PON_PBS, this can hold addresses of both.
+                 PON_PBS base address needs to be specified for
+                 such devices if "qcom,kdpwr-sw-debounce" is specified.
+
+  reg-names:
+    description: For PON GEN1 and GEN2, it should be "pon".
+                 and for PON GEN3, it should include "pon_hlos" and
+                 optionally "pon_pbs".
+
+  interrupts:
+    description: Specifies the interrupts associated with PON.
+
+  interrupt-names:
+    description: Specifies the interrupt names associated with
+                 the interrupts property. Must be a subset of
+                 "kpdpwr", "kpdpwr-bark", "resin", "resin-bark",
+                 "cblpwr", "kpdpwr-resin-bark", and
+                 "pmic-wd-bark". Bark interrupts are associated
+                  with system reset configuration to allow default
+                  reset configuration to be activated. If system
+                  reset configuration is not supported then bark
+                  interrupts are nops. Additionally, the
+                  "pmic-wd-bark" interrupt can be added if the
+                  system needs to handle PMIC watchdog barks.
+
+  qcom,pon-dbc-delay:
+    description: The debounce delay for the power-key interrupt
+                 specified in us.
+                 Possible values for GEN1 PON are
+                 15625, 31250, 62500, 125000, 250000, 500000,
+                 1000000 and 2000000.
+                 Possible values for GEN2 PON are
+                 62, 123, 245, 489, 977, 1954, 3907, 7813,
+                 15625, 31250, 62500, 125000 and 250000.
+                 Intermediate value is rounded down to the
+                 nearest valid value.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,system-reset:
+    description: Boolean which specifies that this PON peripheral
+                 can be used to reset the system. This property
+                 can only be used by one device on the system. It
+                 is an error to include it more than once.
+    type: boolean
+
+  qcom,modem-reset:
+    description: Boolean which specifies that this PON peripheral
+                 can be used to reset the attached modem chip.
+                 This property can only be used by one PON device
+                 on the system. qcom,modem-reset and
+                 qcom,system-reset cannot be specified for the
+                 same PON device.
+    type: boolean
+
+  qcom,s3-debounce:
+    description: The debounce delay for stage 3 reset trigger in
+                 secs. The values range from 0 to 128.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,s3-src:
+    description: The source for stage 3 reset. It can be one of
+                 "kpdpwr", "resin", "kpdpwr-or-resin" or
+                 "kpdpwr-and-resin".
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,clear-warm-reset:
+    description: Boolean which specifies that the WARM_RESET
+                 reason registers need to be cleared for this
+                 target. The property is used for the targets
+                 which have a hardware feature to catch resets
+                 which aren't triggered by the application
+                 processor. In such cases clearing WARM_REASON
+                 registers across processor resets keeps the
+                 registers in a useful state.
+    type: boolean
+
+  qcom,secondary-pon-reset:
+    description: Boolean property which indicates that the PON
+                 peripheral is a secondary PON device which
+                 needs to be configured during reset in addition
+                 to the primary PON device that is configured
+                 for system reset through qcom,system-reset
+                 property.
+                 This should not be defined along with the
+                 qcom,system-reset or qcom,modem-reset property.
+    type: boolean
+
+  qcom,store-hard-reset-reason:
+    description: Boolean property which if set will store the
+                 hardware reset reason to SOFT_RB_SPARE register
+                 of the core PMIC PON peripheral.
+    type: boolean
+
+  qcom,hard-reset-poweroff-type:
+    description: Same description as
+                 qcom,warm-reset-poweroff-type but this applies
+                 for the system hard reset case.
+    type: boolean
+
+  qcom,kpdpwr-sw-debounce:
+    description: Boolean property to enable the debounce logic
+                 on the KPDPWR_N rising edge.
+    type: boolean
+
+  qcom,pon_X:
+    description: These PON child nodes correspond to features
+                 supported by the PON peripheral including reset
+                 configurations, pushbutton keys, and regulators.
+    type: boolean
+
+required:
+  - compatible
+  - reg
+
+patternProperties:
+  "^pon-[0-9]+$":
+    type: object
+    $ref: input.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      regulator-name:
+        description: Regulator name for the PON regulator that is being configured.
+
+      qcom,pon-spare-reg-addr:
+        description: Register offset from the base address of the
+                 PON peripheral that needs to be configured for
+                 the regulator being controlled.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      qcom,pon-spare-reg-bit:
+        description: Bit position in the specified register that
+                 needs to be configured for the regulator being
+                 controlled.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      qcom,pon-type:
+        description: The type of PON/RESET source. Supported values are
+                    0 = KPDPWR
+                    1 = RESIN
+                    2 = CBLPWR
+                    3 = KPDPWR_RESIN
+                    These values are PON_POWER_ON_TYPE_* found in
+                    include/dt-bindings/input/qcom,qpnp-power-on.h
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      qcom,pull-up:
+        description: Boolean flag indicating if a pull-up resistor
+                    should be enabled for the input.
+        type: boolean
+
+      qcom,support-reset:
+        description: Indicates if this PON source supports
+                    reset functionality.
+                    0 = Not supported
+                    1 = Supported
+                    If this property is not defined, then default S2
+                    reset configurations should not be modified.
+        type: boolean
+
+      qcom,use-bark:
+        description: Specify if this PON type needs to handle a bark
+                     interrupt.
+        type: boolean
+
+      linux,code:
+        description: The input key-code associated with the reset
+                     source. The reset source in its default
+                     configuration can be used to support standard keys.
+
+      qcom,s1-timer:
+        description: The debounce timer for the BARK interrupt for
+                     the reset source. Value is specified in ms.
+                     Supported values are
+                     0, 32, 56, 80, 128, 184, 272, 408, 608, 904,
+                     1352, 2048, 3072, 4480, 6720, 10256
+        type: boolean
+
+      qcom,s2-timer:
+        description: The debounce timer for the S2 reset specified
+                     in ms. On the expiry of this timer, the PMIC
+                     executes the reset sequence.
+                     Supported values are
+                     0, 10, 50, 100, 250, 500, 1000, 2000
+        type: boolean
+
+      qcom,s2-type:
+        description: The type of reset associated with this source.
+                     Supported values
+                     0 = SOFT_RESET (legacy)
+                     1 = WARM_RESET
+                     4 = SHUTDOWN
+                     5 = DVDD_SHUTDOWN
+                     7 = HARD_RESET
+                     8 = DVDD_HARD_RESET
+                     These values are PON_POWER_OFF_TYPE_* found in
+                     include/dt-bindings/input/qcom,qpnp-power-on.h
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+    required:
+      - regulator-name
+      - qcom,pon-spare-reg-addr
+      - qcom,pon-spare-reg-bit
+      - qcom,pon-type
+      - qcom,s1-timer
+      - qcom,s2-timer
+      - qcom,s2-type
+
+    additionalProperties: false
+
+allOf:
+  - $ref: input.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    qcom,power-on@800 {
+               compatible = "qcom,qpnp-power-on";
+               reg = <0x800>;
+               interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
+                            <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>,
+                            <0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>,
+                            <0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>;
+               interrupt-names = "kpdpwr", "resin", "resin-bark",
+                                 "kpdpwr-resin-bark";
+               qcom,pon-dbc-delay = <15625>;
+               qcom,system-reset;
+               qcom,s3-debounce = <32>;
+               qcom,s3-src = "resin";
+               qcom,clear-warm-reset;
+               qcom,store-hard-reset-reason;
+               qcom,pon_1 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+                           qcom,pull-up;
+                           linux,code = <KEY_POWER>;
+               };
+               qcom,pon_2 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+                           qcom,support-reset = <1>;
+                           qcom,pull-up;
+                           qcom,s1-timer = <0>;
+                           qcom,s2-timer = <2000>;
+                           qcom,s2-type = <PON_POWER_OFF_TYPE_WARM_RESET>;
+                           linux,code = <KEY_VOLUMEDOWN>;
+                           qcom,use-bark;
+               };
+               qcom,pon_3 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR_RESIN>;
+                           qcom,support-reset = <1>;
+                           qcom,s1-timer = <6720>;
+                           qcom,s2-timer = <2000>;
+                           qcom,s2-type = <PON_POWER_OFF_TYPE_HARD_RESET>;
+                           qcom,pull-up;
+                           qcom,use-bark;
+               };
+    };
+  - |
+    qcom,power-on@800 {
+               compatible = "qcom,qpnp-power-on";
+               reg = <0x800>;
+               qcom,secondary-pon-reset;
+               qcom,hard-reset-poweroff-type = <PON_POWER_OFF_TYPE_SHUTDOWN>;
+
+               pon_perph_reg:qcom,pon_perph_reg {
+                                                 regulator-name = "pon_spare_reg";
+                                                 qcom,pon-spare-reg-addr = <0x8c>;
+                                                 qcom,pon-spare-reg-bit = <1>;
+               };
+    };
+  - |
+    pon_hlos@1300 {
+               compatible = "qcom,qpnp-power-on";
+               reg = <0x1300>, <0x800>;
+               reg-names = "pon_hlos", "pon_pbs";
+               interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>
+                            <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+               interrupt-names = "kpdpwr", "resin";
+               qcom,kpdpwr-sw-debounce;
+
+               qcom,pon_1 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+                           linux,code = <KEY_POWER>;
+               };
+               qcom,pon_2 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+                           linux,code = <KEY_VOLUMEDOWN>;
+               };
+    };
+...

bindings/input/touchscreen/goodix.yaml

@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/input/touchscreen/goodix.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Goodix GT9xx series touchscreen controller Bindings
+title: Goodix GT9xx series touchscreen controller
 
 maintainers:
   - Dmitry Torokhov <dmitry.torokhov@gmail.com>
@@ -29,6 +29,7 @@ properties:
       - goodix,gt928
       - goodix,gt9286
       - goodix,gt967
+      - goodix,gt9916S
 
   reg:
     enum: [ 0x5d, 0x14 ]

bindings/input/touchscreen/st,stmfts.txt

@@ -8,7 +8,7 @@ The driver supports also hovering as an absolute single touch event with x, y, z
 coordinates.
 
 Required properties:
-- compatible		: must be "st,stmfts" OR "st,fts"
+- compatible		: must be "st,stmfts" OR "st,fts" OR "st,fts2"
 - reg			: I2C slave address, (e.g. 0x49)
 - interrupts		: interrupt specification
 - avdd-supply		: analogic power supply

bindings/interconnect/qcom,rpm.yaml

@@ -43,6 +43,12 @@ properties:
       - qcom,sdm660-gnoc
       - qcom,sdm660-mnoc
       - qcom,sdm660-snoc
+      - qcom,monaco-bimc
+      - qcom,monaco-system_noc
+      - qcom,monaco-config_noc
+      - qcom,monaco-clk_virt
+      - qcom,monaco-mmnrt_virt
+      - qcom,monaco-mmrt_virt
 
   '#interconnect-cells':
     description: |
@@ -96,6 +102,12 @@ allOf:
               - qcom,sdm660-cnoc
               - qcom,sdm660-gnoc
               - qcom,sdm660-snoc
+              - qcom,monaco-bimc
+              - qcom,monaco-system_noc
+              - qcom,monaco-config_noc
+              - qcom,monaco-clk_virt
+              - qcom,monaco-mmnrt_virt
+              - qcom,monaco-mmrt_virt
 
     then:
       properties:
@@ -215,6 +227,27 @@ allOf:
             - description: Aggregate2 USB3 AXI Clock.
             - description: Config NoC USB2 AXI Clock.
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,monaco-system_noc
+
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: bus
+            - const: bus_a
+
+        clocks:
+          items:
+            - description: Bus Clock.
+            - description: Bus A Clock.
+            - description: IPA Clock.
+            - description: Config NoC USB2 AXI Clock.
+            - description: System NoC USB2 AXI Clock.
 examples:
   - |
       #include <dt-bindings/clock/qcom,rpmcc.h>

bindings/interconnect/qcom,rpmh.yaml

@@ -172,6 +172,18 @@ properties:
       - qcom,parrot-nsp_noc
       - qcom,parrot-pcie_anoc
       - qcom,parrot-system_noc
+      - qcom,ravelin-clk_virt
+      - qcom,ravelin-mc_virt
+      - qcom,ravelin-aggre1_noc
+      - qcom,ravelin-aggre2_noc
+      - qcom,ravelin-cnoc2
+      - qcom,ravelin-cnoc3
+      - qcom,ravelin-gem_noc
+      - qcom,ravelin-lpass_ag_noc
+      - qcom,ravelin-mmss_noc
+      - qcom,ravelin-pcie_anoc
+      - qcom,ravelin-system_noc
+      - qcom,ravelin-video_aggre_noc
 
   '#interconnect-cells': true
 

bindings/interrupt-controller/qcom,mpm-legacy.yaml

@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm-legacy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MPM Interrupt Controller
+
+maintainers:
+  - Raghavendra Kakarla <quic_rkakarla@quicinc.com>
+
+description:
+  Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
+  MSM Power Manager (MPM) that is in always-on domain. In addition to managing
+  resources during sleep, the hardware also has an interrupt controller that
+  monitors the interrupts when the system is asleep, wakes up the APSS when
+  one of these interrupts occur and replays it to GIC interrupt controller
+  after GIC becomes operational.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - "qcom,mpm-blair"
+          - "qcom,mpm-holi"
+          - "qcom,mpm-pitti"
+          - "qcom,mpm-monaco"
+      - const: qcom,mpm
+
+  reg:
+    minItems: 1
+    items:
+      - description: Specifies the base address and size of vMPM registers in RPM MSG RAM.
+      - description: Specifies the address and size of MPM timer registers in RPM MSG RAM.
+      - description: Timer frame register to read the aggregated time.
+
+  '#interrupt-cells':
+    const: 2
+
+  interrupt-controller: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    mpm: interrupt-controller@45f01b8 {
+        compatible = "qcom,mpm", "qcom,mpm-blair";
+        interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
+        reg = <0x45f01b8 0x1000>,
+              <0xb011008 0x4>,  /* MSM_APCS_GCC_BASE 4K */
+              <0xf121000 0x1000>; /* Timer Frame Register */
+        reg-names = "vmpm", "ipc", "timer";
+        interrupt-controller;
+        interrupt-parent = <&intc>;
+        interrupt-cells = <2>;
+    };
+
+    wake-device {
+        interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>;
+    };

bindings/leds/qcom,leds-qpnp-vibrator-ldo.yaml

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/qcom,leds-qpnp-vibrator-ldo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Vibrator-LDO
+
+maintainers:
+  - Jishnu Prakash <quic_jprakash@quicinc.com>
+
+description: >
+  QPNP (Qualcomm Technologies, Inc. Plug N Play) Vibrator-LDO is a peripheral
+  on some QTI PMICs. It can be interfaced with the host processor via SPMI.
+
+properties:
+  compatible:
+    const: qcom,qpnp-vibrator-ldo
+
+  reg:
+    description: Base address of vibrator-ldo peripheral.
+
+  qcom,vib-ldo-volt-uv:
+    description: The optimal voltage requirement of the vibrator motor for
+                 a normal vibration. Value is specified in microvolts.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,disable-overdrive:
+    description: Do not apply overdrive voltage.
+    type: boolean
+
+  qcom,vib-overdrive-volt-uv:
+    description: The voltage in microvolts used as overdrive factor for
+                 improving motor reactivity at the start of vibration.
+                 If this property not specified, a default value of
+                 2 times the value specified in qcom,vib-ldo-volt-uv
+                 property is used.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+  - compatible
+  - reg
+  - qcom,vib-ldo-volt-uv
+
+allOf:
+  - $ref: common.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    pmi632_vib: qcom,vibrator@5700 {
+        compatible = "qcom,qpnp-vibrator-ldo";
+        reg = <0x5700 0x100>;
+        qcom,vib-ldo-volt-uv = <1504000>;
+        qcom,disable-overdrive;
+        qcom,vib-overdrive-volt-uv = <3544000>;
+    };
+...

bindings/leds/qcom,leds-qti-tri-led.yaml

@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/qcom,leds-qti-tri-led.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. TRI_LED driver specific document
+
+maintainers:
+  - Subbaraman Narayanamurthy <subbaram@quicinc.com>
+
+description: >
+  This binding document describes the properties of TRI_LED module in
+  Qualcomm Technologies, Inc. PMIC chips.
+
+properties:
+  compatible:
+    const: qcom,tri-led
+
+  reg:
+    description: Register base of the TRI_LED module.
+
+  nvmem-names:
+    description: Nvmem device name for SDAM to do PBS trigger. It must be
+                 defined as "pbs_sdam". This is required only for HR_LEDs.
+
+  nvmem:
+    description: Phandle of the nvmem device name to access SDAM to do PBS
+                 trigger. This is required only for HR_LEDs.
+
+  pwms:
+    description: The PWM device (phandle) used for controlling LED.
+
+  led-sources:
+    description: see Documentation/devicetree/bindings/leds/common.txt;
+                 Device current output identifiers are 0 - LED1_EN,
+                 1 - LED2_EN, 2 - LED3_EN.
+  label:
+    description: see Documentation/devicetree/bindings/leds/common.txt;
+
+  linux,default-trigger:
+    description: see Documentation/devicetree/bindings/leds/common.txt;
+
+required:
+  - compatible
+  - reg
+  - pwms
+  - led-sources
+
+allOf:
+  - $ref: common.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    pmi8998_rgb: tri-led@d000{
+            compatible = "qcom,tri-led";
+            reg = <0xd000>;
+
+            red {
+                 label = "red";
+                 pwms = <&pmi8998_lpg 4 1000000>;
+                 led-sources = <0>;
+            };
+            green {
+                   label = "green";
+                   pwms = <&pmi8998_lpg 3 1000000>;
+                   led-sources = <1>;
+            };
+            blue {
+                  label = "blue";
+                  pwms = <&pmi8998_lpg 2 1000000>;
+                  led-sources = <2>;
+             };
+    };
+...

bindings/nvmem/qcom,qfprom.yaml

@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/nvmem/qcom,qfprom.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Technologies Inc, QFPROM Efuse bindings
+title: Qualcomm Technologies Inc, QFPROM Efuse
 
 maintainers:
   - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
@@ -30,6 +30,7 @@ properties:
           - qcom,sdm845-qfprom
           - qcom,sm6115-qfprom
           - qcom,sun-qfprom
+          - qcom,ravelin-qfprom
       - const: qcom,qfprom
 
   reg:

bindings/pinctrl/qcom,kera-tlmm.yaml

@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,kera-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Kera TLMM block
+
+maintainers:
+  - Mukesh Ojha <quic_mojha@quicinc.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer (TLMM) block found
+  in the Kera platform.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,kera-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 105
+
+  gpio-line-names:
+    maxItems: 214
+
+  '#gpio-cells': true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+patternProperties:
+  '-state$':
+    oneOf:
+      - $ref: "#/$defs/qcom-kera-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-kera-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-kera-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+        minItems: 1
+        maxItems: 36
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+        enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3,
+                atest_char_start, atest_usb0, atest_usb00, atest_usb01,
+                atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1,
+                audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk,
+                cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0,
+                cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4,
+                cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2,
+                cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0,
+                cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0,
+                cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx,
+                coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete,
+                ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
+                ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2,
+                gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0,
+                i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0,
+                i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0,
+                i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0,
+                i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0,
+                i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0,
+                i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck,
+                i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1,
+                mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,
+                mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
+                nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1,
+                phase_flag10, phase_flag11, phase_flag12, phase_flag13,
+                phase_flag14, phase_flag15, phase_flag16, phase_flag17,
+                phase_flag18, phase_flag19, phase_flag2, phase_flag20,
+                phase_flag21, phase_flag22, phase_flag23, phase_flag24,
+                phase_flag25, phase_flag26, phase_flag27, phase_flag28,
+                phase_flag29, phase_flag3, phase_flag30, phase_flag31,
+                phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8,
+                phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
+                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0,
+                qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
+                qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4,
+                qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
+                qlink_big_enable, qlink_big_request, qlink_little_enable,
+                qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3,
+                qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2,
+                qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3,
+                qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4,
+                qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2,
+                qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3,
+                qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0,
+                qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1,
+                qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2,
+                qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3,
+                qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4,
+                qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2,
+                qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3,
+                qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6,
+                qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0,
+                qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40,
+                sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2,
+                tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2,
+                tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
+                uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
+                uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0,
+                vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
+
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    allOf:
+      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+      - if:
+          properties:
+            pins:
+              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
+        then:
+          required:
+            - function
+
+    additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    pinctrl@f100000 {
+        compatible = "qcom,kera-tlmm";
+        reg = <0x0f100000 0x300000>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&tlmm 0 0 211>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+        gpio-wo-state {
+            pins = "gpio1";
+            function = "gpio";
+        };
+
+        uart-w-state {
+            rx-pins {
+                pins = "gpio26";
+                function = "qup1_se7_l0";
+                bias-pull-up;
+            };
+
+            tx-pins {
+                pins = "gpio27";
+                function = "qup1_se7_l1";
+                bias-disable;
+            };
+        };
+    };
+...

bindings/pinctrl/qcom,monaco-tlmm.yaml

@@ -16,7 +16,7 @@ allOf:
   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 properties:
   compatible:
-    const: "qcom,monaco-pinctrl"
+    const: "qcom,monaco-tlmm"
 
   reg:
     maxItems: 1

bindings/pinctrl/qcom,pmic-gpio.yaml

@@ -18,6 +18,7 @@ properties:
     items:
       - enum:
           - qcom,pm2250-gpio
+          - qcom,pm5100-gpio
           - qcom,pm660-gpio
           - qcom,pm660l-gpio
           - qcom,pm6125-gpio
@@ -303,6 +304,7 @@ allOf:
           contains:
             enum:
               - qcom,pmx65-gpio
+              - qcom,pm5100-gpio
     then:
       properties:
         gpio-line-names:
@@ -474,6 +476,7 @@ $defs:
                                             and gpio11)
                  - gpio1-gpio16 for pmx65
                  - gpio1-gpio12 for pmxr2230
+                 - gpio1-gpio16 for pm5100
 
         items:
           pattern: "^gpio([0-9]+)$"

bindings/pinctrl/qcom,tuna-tlmm.yaml

@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,tuna-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Tuna TLMM block
+
+maintainers:
+  - Shivendra Pratap <quic_spratap@quicinc.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer (TLMM) block found
+  in the Tuna platform.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,tuna-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 105
+
+  gpio-line-names:
+    maxItems: 214
+
+  '#gpio-cells': true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+patternProperties:
+  '-state$':
+    oneOf:
+      - $ref: "#/$defs/qcom-tuna-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-tuna-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-tuna-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+        minItems: 1
+        maxItems: 36
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+        enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3,
+                atest_char_start, atest_usb0, atest_usb00, atest_usb01,
+                atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1,
+                audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk,
+                cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0,
+                cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4,
+                cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2,
+                cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0,
+                cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0,
+                cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx,
+                coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete,
+                ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
+                ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2,
+                gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0,
+                i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0,
+                i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0,
+                i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0,
+                i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0,
+                i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0,
+                i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck,
+                i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1,
+                mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,
+                mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
+                nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1,
+                phase_flag10, phase_flag11, phase_flag12, phase_flag13,
+                phase_flag14, phase_flag15, phase_flag16, phase_flag17,
+                phase_flag18, phase_flag19, phase_flag2, phase_flag20,
+                phase_flag21, phase_flag22, phase_flag23, phase_flag24,
+                phase_flag25, phase_flag26, phase_flag27, phase_flag28,
+                phase_flag29, phase_flag3, phase_flag30, phase_flag31,
+                phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8,
+                phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
+                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0,
+                qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
+                qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4,
+                qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
+                qlink_big_enable, qlink_big_request, qlink_little_enable,
+                qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3,
+                qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2,
+                qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3,
+                qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4,
+                qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2,
+                qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3,
+                qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0,
+                qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1,
+                qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2,
+                qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3,
+                qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4,
+                qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2,
+                qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3,
+                qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6,
+                qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0,
+                qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40,
+                sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2,
+                tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2,
+                tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
+                uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
+                uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0,
+                vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
+
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    allOf:
+      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+      - if:
+          properties:
+            pins:
+              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
+        then:
+          required:
+            - function
+
+    additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    pinctrl@f100000 {
+        compatible = "qcom,tuna-tlmm";
+        reg = <0x0f100000 0x300000>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&tlmm 0 0 211>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+        gpio-wo-state {
+            pins = "gpio1";
+            function = "gpio";
+        };
+
+        uart-w-state {
+            rx-pins {
+                pins = "gpio26";
+                function = "qup1_se7_l0";
+                bias-pull-up;
+            };
+
+            tx-pins {
+                pins = "gpio27";
+                function = "qup1_se7_l1";
+                bias-disable;
+            };
+        };
+    };
+...

bindings/pwm/qcom,pwm-qti-lpg.yaml

@@ -0,0 +1,356 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/qcom,pwm-qti-lpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Light Pulse Generator
+
+maintainers:
+  - Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
+
+description: |
+  This binding document describes the properties of LPG (Light Pulse Generator)
+  device module in Qualcomm Technologies, Inc. PMIC chips.
+
+properties:
+  compatible:
+    const: qcom,pwm-lpg
+
+  reg:
+    minItems: 1
+    maxItems: 2
+    description: |
+      Register base for LPG and LUT modules.
+
+  reg-names:
+    oneOf:
+      - const: lpg-base
+      - items:
+        - const: lpg-base
+        - const: lut-base
+
+  "#pwm-cells":
+    const: 2
+
+  qcom,num-lpg-channels:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The number of the consecutive LPG/PWM channels in the chip.
+
+  nvmem-names:
+    description: |
+      The nvmem device name(s) for the SDAM module(s) where the
+      LUT pattern data is stored. This property is required
+      only when LUT mode is supported with a SDAM module
+      instead of a LUT module. It can take the following
+      mutually exclusive sets of values
+    oneOf:
+    - const: ppg_sdam
+    - items:
+      - const: lut_sdam
+      - const: lpg_chan_sdam
+
+  nvmem:
+    minItems: 1
+    maxItems: 2
+    description: |
+      Phandle(s) of the nvmem device(s) to access the LUT stored
+      in the SDAM module(s). This property is required only when
+      LUT mode is supported and the LUT pattern is stored in
+      SDAM modules instead of a LUT module.
+
+  qcom,pbs-client:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Phandle of the PBS client used for sending the PBS
+      trigger. This property is required when LUT mode is
+      supported and the LUT pattern is stored in a single SDAM
+      module (not two) instead of a LUT module.
+
+  qcom,lut-sdam-base:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The register base of the LUT entries stored in SDAM. This
+      property is required only when LUT mode is supported and
+      the LUT pattern is stored in a SDAM module instead of a
+      LUT module.
+
+  qcom,lut-patterns:
+    description: |
+      Duty ratios in percentages for LPG working at LUT mode.
+      These duty ratios will be translated into PWM values
+      and stored in LUT or SDAM module shared for all LPG
+      channels. The LUT module has resource to store 47 PWM
+      values at max while SDAM module can store up to 64 PWM
+      values. This property is required if any LPG channels
+      support LUT mode.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    maxItems: 64
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - "#pwm-cells"
+  - qcom,num-lpg-channels
+
+patternProperties:
+  "^lpg@[0-9a-f]$":
+    type: object
+    $ref: pwm.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      qcom,lpg-chan-id:
+        minimum: 1
+        maximum: 8
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          The LPG channel's hardware ID indexed from 1. Allowed
+          range is 1 - 8. Maximum value depends on the number of
+          channels supported on PMIC. Cannot specify this property
+          for a channel that is PFM enabled.
+
+      qcom,lpg-sdam-base:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Register base address for LPG configuration in SDAM for
+          the LPG channel specified under "qcom,lpg-chan-id".
+          This property is required if LUT mode is supported with
+          a SDAM module.
+
+      qcom,ramp-step-ms:
+        description: |
+          The step duration in milliseconds for LPG staying at each
+          duty specified in the LUT pattern. Allowed range
+          1 - 511 when LUT module is used, and 8 - 2000 when SDAM is used.
+
+      qcom,ramp-high-index:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          The high index of the LUT pattern where LPG ends up
+          ramping to. Allowed range 1 - 47 when LUT module
+          is used, and 1 - 64 when SDAM module is used.
+
+      qcom,ramp-low-index:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          The low index of the LUT pattern from where LPG begins
+          ramping from. The ramp-low-index should be always less
+          than ramp-high-index when SDAM module is used. Allowed
+          range 0 - 46 when LUT module is used, and 0 - 63 when
+          SDAM module is used.
+
+      qcom,ramp-pattern-repeat:
+        description: |
+          The flag to specify if LPG would be ramping with the LUT
+          pattern repeatedly.
+        type: boolean
+
+      qcom,ramp-pause-hi-count:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          The number of step counts for which the LPG will continue
+          to hold the output after it has ramped up to the high
+          index of the LUT. Allowed range 0 - 254 if SDAM is used.
+
+      qcom,ramp-pause-lo-count:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          The number of step counts for which the LPG will continue
+          to hold the output after it has ramped down to the low
+          index of the LUT. Allowed range 0 - 254 if SDAM is used.
+
+      qcom,ramp-from-low-to-high:
+        description: |
+          The flag to specify the LPG ramping direction. The ramping
+          direction is from low index to high index of the LUT
+          pattern if it's specified. This property is not required
+          when SDAM module is used.
+        type: boolean
+
+    required:
+      - qcom,lpg-chan-id
+      - qcom,ramp-step-ms
+      - qcom,ramp-high-index
+      - qcom,ramp-low-index
+
+allOf:
+  - if:
+      properties:
+        nvmem: true
+
+    then:
+      patternProperties:
+        "^lpg@[0-9a-f]$":
+          properties:
+            qcom,lpg-sdam-base: true
+            qcom,ramp-step-ms:
+              minimum: 8
+              maximum: 2000
+
+            qcom,ramp-high-index:
+              minimum: 1
+              maximum: 64
+
+            qcom,ramp-low-index:
+              minimum: 0
+              maximum: 63
+
+            qcom,ramp-pause-lo-count:
+              minimum: 0
+              maximum: 254
+
+            qcom,ramp-pause-hi-count:
+              minimum: 0
+              maximum: 254
+
+    else:
+      patternProperties:
+        "^lpg@[0-9a-f]$":
+          properties:
+            qcom,lpg-sdam-base: false
+            qcom,ramp-step-ms:
+              minimum: 1
+              maximum: 511
+
+            qcom,ramp-high-index:
+              minimum: 1
+              maximum: 47
+
+            qcom,ramp-low-index:
+              minimum: 0
+              maximum: 46
+
+additionalProperties: false
+
+examples:
+  - |
+    pm8150l_lpg: lpg@b100 {
+            compatible = "qcom,pwm-lpg";
+            reg = <0xb100>, <0xb000>;
+            reg-names = "lpg-base", "lut-base";
+            qcom,num-lpg-channels = <6>;
+            #pwm-cells = <2>;
+            qcom,lut-patterns = <0 14 28 42 56 70 84 100
+                                 100 84 70 56 42 28 14 0>;
+            lpg@1 {
+                   qcom,lpg-chan-id = <1>;
+                   qcom,ramp-step-ms = <200>;
+                   qcom,ramp-pause-hi-count = <10>;
+                   qcom,ramp-pause-lo-count = <10>;
+                   qcom,ramp-low-index = <0>;
+                   qcom,ramp-high-index = <15>;
+                   qcom,ramp-from-low-to-high;
+                   qcom,ramp-pattern-repeat;
+            };
+            lpg@2 {
+                   qcom,lpg-chan-id = <2>;
+                   qcom,ramp-step-ms = <200>;
+                   qcom,ramp-pause-hi-count = <10>;
+                   qcom,ramp-pause-lo-count = <10>;
+                   qcom,ramp-low-index = <0>;
+                   qcom,ramp-high-index = <15>;
+                   qcom,ramp-from-low-to-high;
+                   qcom,ramp-pattern-repeat;
+            };
+            lpg@3 {
+                   qcom,lpg-chan-id = <3>;
+                   qcom,ramp-step-ms = <200>;
+                   qcom,ramp-pause-hi-count = <10>;
+                   qcom,ramp-pause-lo-count = <10>;
+                   qcom,ramp-low-index = <0>;
+                   qcom,ramp-high-index = <15>;
+                   qcom,ramp-from-low-to-high;
+                   qcom,ramp-pattern-repeat;
+            };
+    };
+  - |
+    pmi632_lpg: lpg@b100 {
+           compatible = "qcom,pwm-lpg";
+           reg = <0xb100>;
+           reg-names = "lpg-base";
+           qcom,num-lpg-channels = <3>;
+           #pwm-cells = <2>;
+           nvmem-names = "ppg_sdam";
+           nvmem = <&sdam7>;
+           qcom,pbs-client = <&pbs_client_3>;
+           qcom,lut-sdam-base = <0x80>;
+           qcom,lut-patterns = <0 14 28 42 56 70 84 100
+                               100 84 70 56 42 28 14 0>;
+           lpg@1 {
+                  qcom,lpg-sdam-base = <0x48>:
+                  qcom,lpg-chan-id = <1>;
+                  qcom,ramp-step-ms = <200>;
+                  qcom,ramp-low-index = <0>;
+                  qcom,ramp-high-index = <15>;
+                  qcom,ramp-pause-hi-count = <10>;
+                  qcom,ramp-pause-lo-count = <10>;
+                  qcom,ramp-pattern-repeat;
+           };
+           lpg@2 {
+                  qcom,lpg-sdam-base = <0x56>;
+                  qcom,lpg-chan-id = <2>;
+                  qcom,ramp-step-ms = <200>;
+                  qcom,ramp-low-index = <0>;
+                  qcom,ramp-high-index = <15>;
+                  qcom,ramp-pause-hi-count = <10>;
+                  qcom,ramp-pause-lo-count = <10>;
+                  qcom,ramp-pattern-repeat;
+           };
+           lpg@3 {
+                  qcom,lpg-sdam-base = <0x64>;
+                  qcom,lpg-chan-id = <3>;
+                  qcom,ramp-step-ms = <200>;
+                  qcom,ramp-low-index = <0>;
+                  qcom,ramp-high-index = <15>;
+                  qcom,ramp-pause-hi-count = <10>;
+                  qcom,ramp-pause-lo-count = <10>;
+                  qcom,ramp-pattern-repeat;
+           };
+    };
+  - |
+    pm8350c_pwm_1: pwms@e800 {
+           compatible = "qcom,pwm-lpg";
+           reg = <0xe800>;
+           reg-names = "lpg-base";
+           #pwm-cells = <2>;
+           qcom,num-lpg-channels = <3>;
+           nvmem = <&pmk8350_sdam_21 &pmk8350_sdam_22>;
+           nvmem-names = "lpg_chan_sdam", "lut_sdam";
+           qcom,lut-sdam-base = <0x45>;
+           qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
+                                 90 80 70 60 50 40 30 20 10 0>;
+           lpg@1 {
+                  qcom,lpg-sdam-base = <0x48>;
+                  qcom,lpg-chan-id = <1>;
+                  qcom,ramp-step-ms = <200>;
+                  qcom,ramp-low-index = <0>;
+                  qcom,ramp-high-index = <19>;
+                  qcom,ramp-pause-hi-count = <10>;
+                  qcom,ramp-pause-lo-count = <10>;
+                  qcom,ramp-pattern-repeat;
+           };
+           lpg@2 {
+                  qcom,lpg-sdam-base = <0x56>;
+                  qcom,lpg-chan-id = <2>;
+                  qcom,ramp-step-ms = <200>;
+                  qcom,ramp-low-index = <0>;
+                  qcom,ramp-high-index = <19>;
+                  qcom,ramp-pause-hi-count = <10>;
+                  qcom,ramp-pause-lo-count = <10>;
+                  qcom,ramp-pattern-repeat;
+           };
+           lpg@3 {
+                  qcom,lpg-sdam-base = <0x64>;
+                  qcom,lpg-chan-id = <3>;
+                  qcom,ramp-step-ms = <200>;
+                  qcom,ramp-low-index = <0>;
+                  qcom,ramp-high-index = <19>;
+                  qcom,ramp-pause-hi-count = <10>;
+                  qcom,ramp-pause-lo-count = <10>;
+                  qcom,ramp-pattern-repeat;
+           };
+    };
+...

bindings/regulator/rpmh-regulator.yaml

@@ -10,15 +10,15 @@ maintainers:
   - David Collins <quic_collinsd@quicinc.com>
 
 description: |
-  rpmh-regulator devices support PMIC regulator management via the Voltage
-  Regulator Manager (VRM), Aggregated Resource Controller (ARC) and
-  Oscillator Buffer (XOB) RPMh accelerators.  The APPS processor communicates
+  rpmh-regulator devices support PMIC regulator management via the Voltage Regulator
+  Manager (VRM), Aggregated Resource Controller (ARC), Oscillator Buffer (XOB)  and
+  Programmable Boot Sequencer (PBS) RPMh accelerators.  The APPS processor communicates
   with these hardware blocks via a Resource State Coordinator (RSC) using command
   packets.  The VRM allows changing four parameters for a given regulator: enable state,
   output voltage, operating mode and minimum headroom voltage.  The ARC allows changing
   only a single parameter for a given regulator: its operating level.  This
   operating level is fed into CPR which then decides upon a final explicit voltage
-  for the regulator.  The XOB allows changing only a single parameter for a given
+  for the regulator.  The XOB and PBS allow changing only a single parameter for a given
   regulator: its enable state.  Despite its name, the XOB is capable of controlling
   the enable state of any PMIC peripheral.  It is used for clock buffers, low-voltage
   switches, and LDO/SMPS regulators which have a fixed voltage and mode.
@@ -36,6 +36,7 @@ properties:
       - qcom,rpmh-vrm-regulator
       - qcom,rpmh-arc-regulator
       - qcom,rpmh-xob-regulator
+      - qcom,rpmh-pbs-regulator
 
   qcom,resource-name:
     description: |
@@ -139,7 +140,7 @@ patternProperties:
 
       regulator-enable-ramp-delay:
         description: |
-          For VRM and XOB resources, the time in microseconds to delay
+          For VRM, XOB and PBS resources, the time in microseconds to delay
           after enabling a regulator.
 
       qcom,set:
@@ -295,6 +296,17 @@ examples:
       };
     };
 
+    rpmh-regulator-vrmsd {
+      compatible = "qcom,rpmh-pbs-regulator";
+      qcom,resource-name = "vrm.sd";
+
+      L24B_PBS:
+      pm6450_l24_pbs: regulator-pm6450-l24-pbs {
+        regulator-name = "pm6450_l24_pbs";
+        qcom,set = <RPMH_REGULATOR_SET_ALL>;
+      };
+    };
+
   - |
     #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 

bindings/remoteproc/qcom,spss.yaml

@@ -58,6 +58,12 @@ properties:
   px-supply:
     description: Phandle to the PX regulator
 
+  sensors-supply:
+    description: Phandle to the Sensors regulator
+
+  sensors-uV-uA:
+    description: Voltage and Current levels for Sensors regulator
+
   memory-region:
     maxItems: 1
     description: Reference to the reserved-memory for the SPSS
@@ -74,6 +80,8 @@ required:
   - reg-names
   - interrupts
   - cx-supply
+  - sensors-supply
+  - sensors-uV-uA
   - clocks
   - clock-names
   - memory-region
@@ -99,6 +107,9 @@ examples:
         cx-supply = <&VDD_CX_LEVEL>;
         cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
 
+        sensors-supply = <&L2J>;
+        sensors-uV-uA = <1200000 100000>;
+
         clocks = <&rpmhcc RPMH_CXO_CLK>;
         clock-names = "xo";
         qcom,proxy-clock-names = "xo";

bindings/soc/qcom/qcom,mpam.yaml

@@ -9,6 +9,7 @@ title: Qualcomm Technologies, Inc. (QTI) MPAM Driver
 maintainers:
   - avajid@quicinc.com <quic_avajid@quicinc.com>
   - gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
+  - Huang Yiwei <quic_hyiwei@quicinc.com>
 
 description: |
   The Qualcomm Technologies, Inc. (QTI) MPAM Driver provides sysfs nodes for
@@ -19,11 +20,25 @@ properties:
   compatible:
     const: qcom,mpam
 
+  reg:
+    items:
+      - description: address and size of CPUCP DTIM area for MPAM monitor data
+
+  reg-names:
+    items:
+      - const: mon-base
+
 required:
   - compatible
+  - reg
+  - reg-names
+
+additionalProperties: false
 
 examples:
   - |
     qcom_mpam: qcom,mpam {
       compatible = "qcom,mpam";
+      reg = <0x17b6f000 0x1000>;
+      reg-names = "mon-base";
     };

bindings/thermal/qcom,bcl-off-cdev.yaml

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qcom,bcl-off-cdev.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. BCL OFF cooling device
+
+maintainers:
+  - Nitesh Kumar <quic_nitekuma@quicinc.com>
+
+description: |
+ The BCL OFF cooling device, will be used to disable PMIC bcl.
+ This cooling device will be called when modem RF calibration
+ is performed using external power supply.
+
+ When external power supply is used for RF calibration, ibat current
+ can cross the battery specs and can trigger batfet issues. So pmic bcl
+ should be disabled as it is for protection for battery not external
+ power supply.
+
+
+properties:
+  compatible:
+    const: qcom,bcl-off
+
+  reg:
+    maxItems: 1
+    description: |
+     <a b> where 'a' is the starting register address of the PMIC
+     peripheral and 'b' is the size of the peripheral address space.
+
+  '#cooling-cells':
+    const: 2
+    description: |
+      Must be 2. Needed for of_thermal as cooling device identifier.
+      Please refer to <devicetree/bindings/thermal/thermal.txt> for
+      more details.
+
+required:
+  - compatible
+  - reg
+  - '#cooling-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    bcl_off: bcl-off {
+      compatible = "qcom,bcl-off";
+      reg = <0x4700 0x100>;
+      #cooling-cells = <2>;
+    };

bindings/thermal/qcom-tsens.yaml

@@ -57,6 +57,7 @@ properties:
               - qcom,sm8150-tsens
               - qcom,sm8250-tsens
               - qcom,sm8350-tsens
+              - qcom,tsens26xx
           - const: qcom,tsens-v2
 
   reg:

bindings/thermal/qti-lmh-cpu-vdd-cdev.yaml

@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qti-lmh-cpu-vdd-cdev.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QTI LMH CPU Voltage cooling devices.
+
+maintainers:
+  - Nitesh Kumar <quic_nitekuma@quicinc.com>
+
+description: |
+ The LMH CPU voltage cooling device will be used to place voltage restriction
+ vote on CPU railway during cold thermal condition. This cooling device driver
+ will register one cooling device per LLM, which can be used by thermal zone to
+ place voltage restriction vote.
+
+properties:
+  compatible:
+    const: qcom,lmh-cpu-vdd
+
+  reg:
+    maxItems: 1
+    description: |
+     <a b> where 'a' is the starting register address of the LLM
+     and 'b' is the size of LLM address space.
+
+  "#cooling-cells":
+    const: 2
+    description: |
+      Must be 2. Needed for of_thermal as cooling device
+      identifier. Please refer to <devicetree/bindings/thermal/thermal.txt> for more
+      details.
+
+required:
+  - compatible
+  - reg
+  - "#cooling-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    lmh_cpu_vdd0: qcom,lmh-cpu-vdd@18350800 {
+      compatible = "qcom,lmh-cpu-vdd";
+      reg =  <0x18350800 0x1000>;
+      #cooling-cells = <2>;
+    };

bindings/thermal/qti-regulator-cdev.yaml

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qti-regulator-cdev.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Regulator cooling device.
+
+maintainers:
+  - Nitesh Kumar <quic_nitekuma@quicinc.com>
+
+description: |
+ The regulator cooling device, will be used to place a voltage floor
+ restriction on a rail.
+
+
+properties:
+  compatible:
+    const: qcom,regulator-cooling-device
+
+  cdev-supply:
+    description: |
+      phandle to the regulator to which the cooling device will
+      place a floor mitigation.
+
+  regulator-levels:
+    description: |
+      Array of regulator voltages the cooling device should
+      use to place a floor restriction. The voltages should be specified
+      in descending order.
+
+  "#cooling-cells":
+    const: 2
+    description: |
+      Must be 2. Please refer to
+      <devicetree/bindings/thermal/thermal.txt> for more details.
+
+required:
+  - compatible
+  - cdev-supply
+  - regulator-levels
+  - "#cooling-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    mx_cdev: mx-cdev-lvl {
+      compatible = "qcom,regulator-cooling-device";
+      cdev-supply = <&regulator-cdev-supply>;
+      regulator-levels = <RPMH_REGULATOR_LEVEL_NOM RPMH_REGULATOR_LEVEL_OFF>;
+      #cooling-cells = <2>;
+    };

qcom/Makefile

@@ -15,8 +15,8 @@ add-overlays = $(foreach o,$1,$(foreach b,$2,$(eval $(basename $b)-$(basename $o
 
 ifneq ($(CONFIG_ARCH_QTI_VM), y)
 
-SUN_BASE_DTB += sun.dtb sun-v2.dtb
-SUN_APQ_BASE_DTB += sunp.dtb sunp-v2.dtb
+SUN_BASE_DTB += sun.dtb sun-v2.dtb sun-tp.dtb sun-tp-v2.dtb
+SUN_APQ_BASE_DTB += sunp.dtb sunp-v2.dtb sunp-tp.dtb sunp-tp-v2.dtb
 
 SUN_BOARDS += \
 		sun-mtp-3.5mm-overlay.dtbo \
@@ -50,6 +50,23 @@ sun-dtb-$(CONFIG_ARCH_SUN) += \
 	$(call add-overlays, $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS),$(SUN_BASE_DTB))\
 	$(call add-overlays, $(SUN_BOARDS) $(APQ_SUN_BOARDS),$(SUN_APQ_BASE_DTB))
 sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB)
+
+TUNA_BASE_DTB += tuna.dtb
+NOAPQ_TUNA_BOARDS += \
+		 tuna-rumi-overlay.dtbo
+
+sun-dtb-$(CONFIG_ARCH_TUNA) +=  \
+        $(call add-overlays, $(NOAPQ_TUNA_BOARDS),$(TUNA_BASE_DTB))
+sun-overlays-dtb-$(CONFIG_ARCH_TUNA) += $(NOAPQ_TUNA_BOARDS) $(TUNA_BASE_DTB)
+dtb-y += $(sun-dtb-y)
+
+KERA_BASE_DTB += kera.dtb
+NOAPQ_KERA_BOARDS += \
+		 kera-rumi-overlay.dtbo
+
+sun-dtb-$(CONFIG_ARCH_KERA) +=  \
+        $(call add-overlays, $(NOAPQ_KERA_BOARDS),$(KERA_BASE_DTB))
+sun-overlays-dtb-$(CONFIG_ARCH_KERA) += $(NOAPQ_KERA_BOARDS) $(KERA_BASE_DTB)
 dtb-y += $(sun-dtb-y)
 
 PINEAPPLE_BASE_DTB += pineapple.dtb pineapple-v2.dtb
@@ -74,6 +91,40 @@ pineapple-dtb-$(CONFIG_ARCH_PINEAPPLE) += \
 pineapple-overlays-dtb-$(CONFIG_ARCH_PINEAPPLE) += $(PINEAPPLE_BOARDS) $(NOAPQ_PINEAPPLE_BOARDS) $(PINEAPPLE_BASE_DTB) $(PINEAPPLE_APQ_BASE_DTB)
 dtb-y += $(pineapple-dtb-y)
 
+PARROT_BASE_DTB += parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
+PARROT_4GB_BASE_DTB += parrot-4gb.dtb
+
+PARROT_BOARDS += \
+		 parrot-rumi-overlay.dtbo \
+		 parrot-atp-overlay.dtbo \
+		 parrot-idp-overlay.dtbo \
+		 parrot-idp-wcn3990-overlay.dtbo \
+		 parrot-idp-wcn3990-amoled-rcm-overlay.dtbo \
+		 parrot-idp-wcn6750-amoled-rcm-overlay.dtbo \
+		 parrot-idp-wcn6750-amoled-overlay.dtbo \
+		 parrot-idp-nopmi-overlay.dtbo \
+		 parrot-idp-pm8350b-overlay.dtbo \
+		 parrot-qrd-overlay.dtbo \
+		 parrot-qrd-wcn6750-overlay.dtbo \
+		 parrot-qrd-nopmi-overlay.dtbo   \
+		 parrot-qrd-pm8350b-overlay.dtbo
+
+PARROT_4GB_BOARDS += \
+		 parrot-idp-4gb-overlay.dtbo \
+		 parrot-idp-wcn3990-4gb-overlay.dtbo \
+		 parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dtbo \
+		 parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dtbo \
+		 parrot-idp-wcn6750-amoled-4gb-overlay.dtbo \
+		 parrot-qrd-4gb-overlay.dtbo \
+		 parrot-qrd-wcn6750-4gb-overlay.dtbo \
+
+
+parrot-dtb-$(CONFIG_ARCH_PARROT) += \
+	$(call add-overlays, $(PARROT_BOARDS),$(PARROT_BASE_DTB)) \
+	$(call add-overlays, $(PARROT_4GB_BOARDS),$(PARROT_4GB_BASE_DTB))
+parrot-overlays-dtb-$(CONFIG_ARCH_PARROT) += $(PARROT_BOARDS) $(PARROT_BASE_DTB) $(PARROT_4GB_BOARDS) $(PARROT_4GB_BASE_DTB)
+dtb-y += $(parrot-dtb-y)
+
 endif
 
 ifeq ($(CONFIG_ARCH_PINEAPPLE), y)

qcom/diwali-gdsc.dtsi

@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	/* CAM_CC GDSCs */
+	cam_cc_bps_gdsc: qcom,gdsc@ad10004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad10004 0x4>;
+		regulator-name = "cam_cc_bps_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	cam_cc_ife_0_gdsc: qcom,gdsc@ad13004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad13004 0x4>;
+		regulator-name = "cam_cc_ife_0_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	cam_cc_ife_1_gdsc: qcom,gdsc@ad14004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad14004 0x4>;
+		regulator-name = "cam_cc_ife_1_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	cam_cc_ife_2_gdsc: qcom,gdsc@ad14078 {
+		compatible = "qcom,gdsc";
+		reg = <0xad14078 0x4>;
+		regulator-name = "cam_cc_ife_2_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	cam_cc_ipe_0_gdsc: qcom,gdsc@ad11004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad11004 0x4>;
+		regulator-name = "cam_cc_ipe_0_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	cam_cc_titan_top_gdsc: qcom,gdsc@ad15120 {
+		compatible = "qcom,gdsc";
+		reg = <0xad15120 0x4>;
+		regulator-name = "cam_cc_titan_top_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	cam_cc_camss_top_gdsc: qcom,gdsc@adf4004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf4004 0x4>;
+		regulator-name = "cam_cc_camss_top_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	/* DISP_CC GDSCs */
+	disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf09000 0x4>;
+		regulator-name = "disp_cc_mdss_core_gdsc";
+		proxy-supply = <&disp_cc_mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf0b000 0x4>;
+		regulator-name = "disp_cc_mdss_core_int2_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	/* DISP_CC_0 GDSCs */
+	disp0_cc_mdss_core_gdsc: qcom,disp0-gdsc@af09000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf09000 0x4>;
+		regulator-name = "disp0_cc_mdss_core_gdsc";
+		proxy-supply = <&disp0_cc_mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	disp0_cc_mdss_core_int2_gdsc: qcom,disp0-gdsc@af0b000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf0b000 0x4>;
+		regulator-name = "disp0_cc_mdss_core_int2_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	/* DISP_CC_1 GDSCs */
+	disp1_cc_mdss_core_gdsc: qcom,disp1-gdsc@15709000 {
+		compatible = "qcom,gdsc";
+		reg = <0x15709000 0x4>;
+		regulator-name = "disp1_cc_mdss_core_gdsc";
+		proxy-supply = <&disp1_cc_mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	disp1_cc_mdss_core_int2_gdsc: qcom,disp1-gdsc@1570b000 {
+		compatible = "qcom,gdsc";
+		reg = <0x1570b000 0x4>;
+		regulator-name = "disp1_cc_mdss_core_int2_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	gcc_apcs_gdsc_vote_ctrl: syscon@162128 {
+		compatible = "syscon";
+		reg = <0x162128 0x4>;
+	};
+
+	gcc_apcs_gdsc_sleep_ctrl: syscon@162204 {
+		compatible = "syscon";
+		reg = <0x162204 0x4>;
+	};
+
+	/* GCC GDSCs */
+	gcc_pcie_0_gdsc: qcom,gdsc@17b004 {
+		compatible = "qcom,gdsc";
+		reg = <0x17b004 0x4>;
+		regulator-name = "gcc_pcie_0_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
+		status = "disabled";
+	};
+
+	gcc_ufs_phy_gdsc: qcom,gdsc@187004 {
+		compatible = "qcom,gdsc";
+		reg = <0x187004 0x4>;
+		regulator-name = "gcc_ufs_phy_gdsc";
+		qcom,retain-regs;
+		proxy-supply = <&gcc_ufs_phy_gdsc>;
+		qcom,proxy-consumer-enable;
+		status = "disabled";
+	};
+
+	gcc_usb30_prim_gdsc: qcom,gdsc@149004 {
+		compatible = "qcom,gdsc";
+		reg = <0x149004 0x4>;
+		regulator-name = "gcc_usb30_prim_gdsc";
+		qcom,retain-regs;
+		proxy-supply = <&gcc_usb30_prim_gdsc>;
+		qcom,proxy-consumer-enable;
+		status = "disabled";
+	};
+
+	gcc_pcie_0_phy_gdsc: qcom,gdsc@17c000 {
+		compatible = "qcom,gdsc";
+		reg = <0x17c000 0x4>;
+		regulator-name = "gcc_pcie_0_phy_gdsc";
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>;
+		status = "disabled";
+	};
+
+	gcc_pcie_1_gdsc: qcom,gdsc@19d004 {
+		compatible = "qcom,gdsc";
+		reg = <0x19d004 0x4>;
+		regulator-name = "gcc_pcie_1_gdsc";
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
+		status = "disabled";
+	};
+
+	gcc_pcie_1_phy_gdsc: qcom,gdsc@19e000 {
+		compatible = "qcom,gdsc";
+		reg = <0x19e000 0x4>;
+		regulator-name = "gcc_pcie_1_phy_gdsc";
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>;
+		status = "disabled";
+	};
+
+	gcc_pcie_2_gdsc: qcom,pcie2-gdsc@19d004 {
+		compatible = "qcom,gdsc";
+		reg = <0x19d004 0x4>;
+		regulator-name = "gcc_pcie_2_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
+		status = "disabled";
+	};
+
+	gcc_usb3_phy_gdsc: qcom,gdsc@160018 {
+		compatible = "qcom,gdsc";
+		reg = <0x160018 0x4>;
+		regulator-name = "gcc_usb3_phy_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	gcc_venus_gdsc: qcom,gdsc@1b6020 {
+		compatible = "qcom,gdsc";
+		reg = <0x1b6020 0x4>;
+		regulator-name = "gcc_venus_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	gcc_vcodec0_gdsc: qcom,gdsc@1b6044 {
+		compatible = "qcom,gdsc";
+		reg = <0x1b6044 0x4>;
+		regulator-name = "gcc_vcodec0_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@18d050 {
+		compatible = "qcom,gdsc";
+		reg = <0x18d050 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@18d058 {
+		compatible = "qcom,gdsc";
+		reg = <0x18d058 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc: qcom,gdsc@18d078 {
+		compatible = "qcom,gdsc";
+		reg = <0x18d078 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc: qcom,gdsc@18d07c {
+		compatible = "qcom,gdsc";
+		reg = <0x18d07c 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc: qcom,gdsc@18d088 {
+		compatible = "qcom,gdsc";
+		reg = <0x18d088 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc: qcom,gdsc@18d08c {
+		compatible = "qcom,gdsc";
+		reg = <0x18d08c 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@18d054 {
+		compatible = "qcom,gdsc";
+		reg = <0x18d054 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@18d06c {
+		compatible = "qcom,gdsc";
+		reg = <0x18d06c 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@18d05c {
+		compatible = "qcom,gdsc";
+		reg = <0x18d05c 0x4>;
+		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@18d060 {
+		compatible = "qcom,gdsc";
+		reg = <0x18d060 0x4>;
+		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	/* GPU_CC GDSCs */
+	gpu_cc_cx_hw_ctrl: syscon@3d9953c {
+		compatible = "syscon";
+		reg = <0x3d9953c 0x4>;
+	};
+
+	/* GPU_CC GDSCs */
+	gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
+		compatible = "qcom,gdsc";
+		reg = <0x3d99108 0x4>;
+		hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>;
+		regulator-name = "gpu_cc_cx_gdsc";
+		qcom,no-status-check-on-disable;
+		qcom,clk-dis-wait-val = <8>;
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	gpu_cc_gx_domain_addr: syscon@3d99504 {
+		compatible = "syscon";
+		reg = <0x3d99504 0x4>;
+	};
+
+	gpu_cc_gx_sw_reset: syscon@3d99058 {
+		compatible = "syscon";
+		reg = <0x3d99058 0x4>;
+	};
+
+	gpu_cc_gx_acd_reset: syscon@3d99358 {
+		compatible = "syscon";
+		reg = <0x3d99358 0x4>;
+	};
+
+	gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
+		compatible = "syscon";
+		reg = <0x3d9958c 0x4>;
+	};
+
+	gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
+		compatible = "qcom,gdsc";
+		reg = <0x3d9905c 0x4>;
+		regulator-name = "gpu_cc_gx_gdsc";
+		domain-addr = <&gpu_cc_gx_domain_addr>;
+		sw-reset = <&gpu_cc_gx_sw_reset>,
+			   <&gpu_cc_gx_acd_reset>,
+			   <&gpu_cc_gx_acd_iroot_reset>;
+		qcom,reset-aon-logic;
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	/* VIDEO_CC GDSCs */
+	video_cc_mvs0_gdsc: qcom,gdsc@aaf81a4 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf81a4 0x4>;
+		regulator-name = "video_cc_mvs0_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	video_cc_mvs0c_gdsc: qcom,gdsc@aaf8084 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf8084 0x4>;
+		regulator-name = "video_cc_mvs0c_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	video_cc_mvs1_gdsc: qcom,gdsc@aaf8244 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf8244 0x4>;
+		regulator-name = "video_cc_mvs1_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	video_cc_mvs1c_gdsc: qcom,gdsc@aaf8124 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf8124 0x4>;
+		regulator-name = "video_cc_mvs1c_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	video_cc_mvsc_gdsc: qcom,gdsc@aaf5004 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf5004 0x4>;
+		regulator-name = "video_cc_mvsc_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+};

qcom/ipcc-test-parrot.dtsi

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "ipcc-test.dtsi"
+
+&soc {
+	/delete-node/ ipcc-self-ping-slpi;
+};

qcom/kera-pinctrl.dtsi

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+};

qcom/kera-rumi-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "kera-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kera RUMI";
+	compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi";
+	qcom,msm-id = <659 0x10000>;
+	qcom,board-id = <15 0>;
+};

qcom/kera-rumi.dtsi

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&arch_timer {
+	clock-frequency = <500000>;
+};
+
+&memtimer {
+	clock-frequency = <500000>;
+};

qcom/kera.dts

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+#include "kera.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kera SoC";
+	compatible = "qcom,kera";
+	qcom,board-id = <0 0>;
+};

qcom/kera.dtsi

@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kera";
+	compatible = "qcom,kera";
+	qcom,msm-id = <659 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory {
+		device_type = "memory";
+		reg = <0 0 0 0>;
+	};
+
+	chosen: chosen {
+		bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
+	};
+
+	reserved_memory: reserved-memory {};
+
+	firmware: firmware {};
+
+	aliases {};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table"; /* TODO: Update to psci */
+			cpu-release-addr = <0x0 0xE3940000>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "spin-table"; /* TODO: Update to psci */
+			cpu-release-addr = <0x0 0xE3940000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "spin-table"; /* TODO: Update to psci */
+			cpu-release-addr = <0x0 0xE3940000>;
+			next-level-cache = <&L2_2>;
+			L2_2: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x300>;
+			enable-method = "spin-table"; /* TODO: Update to psci */
+			cpu-release-addr = <0x0 0xE3940000>;
+			next-level-cache = <&L2_3>;
+			L2_3: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x400>;
+			enable-method = "spin-table"; /* TODO: Update to psci */
+			cpu-release-addr = <0x0 0xE3940000>;
+			next-level-cache = <&L2_4>;
+			L2_4: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x500>;
+			enable-method = "spin-table"; /* TODO: Update to psci */
+			cpu-release-addr = <0x0 0xE3940000>;
+			next-level-cache = <&L2_5>;
+			L2_5: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x600>;
+			enable-method = "spin-table"; /* TODO: Update to psci */
+			cpu-release-addr = <0x0 0xE3940000>;
+			next-level-cache = <&L2_6>;
+			L2_6: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x700>;
+			enable-method = "spin-table"; /* TODO: Update to psci */
+			cpu-release-addr = <0x0 0xE3940000>;
+			next-level-cache = <&L2_7>;
+			L2_7: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU3>;
+				};
+
+				core1 {
+					cpu = <&CPU4>;
+				};
+
+				core2 {
+					cpu = <&CPU5>;
+				};
+
+				core3 {
+					cpu = <&CPU6>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	soc: soc { };
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@17100000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x40000>;
+		reg = <0x17100000 0x10000>,	/* GICD */
+		      <0x17180000 0x200000>;	/* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	memtimer: timer@17420000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x17420000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@17421000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17421000 0x1000>,
+			      <0x17422000 0x1000>;
+		};
+
+		frame@17423000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17423000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17425000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17425000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17427000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17427000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17429000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17429000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742b000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742b000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742d000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742d000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,kera-tlmm";
+		reg = <0xf000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+#include "kera-pinctrl.dtsi"

qcom/monaco-dma-heaps.dtsi

@@ -8,6 +8,7 @@
 &soc {
 	qcom,dma-heaps {
 		compatible = "qcom,dma-heaps";
+		depends-on-supply = <&qcom_scm>;
 
 		qcom,qseecom {
 			qcom,dma-heap-name = "qcom,qseecom";

qcom/monaco-pinctrl.dtsi

@@ -5,7 +5,7 @@
 
 &soc {
 	tlmm: pinctrl@500000 {
-		compatible = "qcom,monaco-pinctrl";
+		compatible = "qcom,monaco-tlmm";
 		reg = <0x500000 0x300000>;
 		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;

qcom/monaco-regulators.dtsi

@@ -58,7 +58,7 @@
 		};
 
 		cx_cdev: cx-cdev-lvl {
-			/* compatible = "qcom,regulator-cooling-device"; */
+			compatible = "qcom,regulator-cooling-device";
 			regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>;
 			regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NONE
 					RPM_SMD_REGULATOR_LEVEL_NOM>;

qcom/monaco-thermal-overlay.dtsi

@@ -13,6 +13,21 @@
 				cooling-device = <&CPU0 1 1>;
 			};
 
+			trip0_cpu1 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&CPU1 1 1>;
+			};
+
+			trip0_cpu2 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&CPU2 1 1>;
+			};
+
+			trip0_cpu3 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&CPU3 1 1>;
+			};
+
 			trip1_cpu2 {
 				trip = <&pm5100_trip0>;
 				cooling-device = <&cpu2_pause 1 1>;
@@ -27,11 +42,26 @@
 
 	pm5100-bcl-lvl0 {
 		cooling-maps {
-			cpu0_cdev {
+			cpu0_cdev0 {
 				trip = <&bcl_lvl0>;
 				cooling-device = <&CPU0 2 2>;
 			};
 
+			cpu1_cdev0 {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&CPU1 2 2>;
+			};
+
+			cpu2_cdev0 {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&CPU2 2 2>;
+			};
+
+			cpu3_cdev0 {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&CPU3 2 2>;
+			};
+
 			cpu2_cdev {
 				trip = <&bcl_lvl0>;
 				cooling-device = <&cpu2_pause 1 1>;
@@ -51,11 +81,26 @@
 
 	pm5100-bcl-lvl1 {
 		cooling-maps {
-			cpu0_cdev {
+			cpu0_cdev0 {
 				trip = <&bcl_lvl1>;
 				cooling-device = <&CPU0 2 2>;
 			};
 
+			cpu1_cdev0 {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&CPU1 2 2>;
+			};
+
+			cpu2_cdev0 {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&CPU2 2 2>;
+			};
+
+			cpu3_cdev0 {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&CPU3 2 2>;
+			};
+
 			cpu1_cdev {
 				trip = <&bcl_lvl1>;
 				cooling-device = <&cpu1_pause 1 1>;
@@ -76,11 +121,26 @@
 
 	socd {
 		cooling-maps {
-			soc_cpu0 {
+			socd_cpu0 {
 				trip = <&socd_trip>;
 				cooling-device = <&CPU0 1 1>;
 			};
 
+			socd_cpu1 {
+				trip = <&socd_trip>;
+				cooling-device = <&CPU1 1 1>;
+			};
+
+			socd_cpu2 {
+				trip = <&socd_trip>;
+				cooling-device = <&CPU2 1 1>;
+			};
+
+			socd_cpu3 {
+				trip = <&socd_trip>;
+				cooling-device = <&CPU3 1 1>;
+			};
+
 			soc_cpu2 {
 				trip = <&socd_trip>;
 				cooling-device = <&cpu2_pause 1 1>;

qcom/monaco-thermal.dtsi

@@ -69,8 +69,36 @@
 		};
 	};
 
+	qcom,cpu-hotplug {
+		compatible = "qcom,cpu-hotplug";
+
+		cpu0_hotplug: cpu0-hotplug {
+			qcom,cpu = <&CPU0>;
+			qcom,cdev-alias = "cpu-hotplug0";
+			#cooling-cells = <2>;
+		};
+
+		cpu1_hotplug: cpu1-hotplug {
+			qcom,cpu = <&CPU1>;
+			qcom,cdev-alias = "cpu-hotplug1";
+			#cooling-cells = <2>;
+		};
+
+		cpu2_hotplug: cpu2-hotplug {
+			qcom,cpu = <&CPU2>;
+			qcom,cdev-alias = "cpu-hotplug2";
+			#cooling-cells = <2>;
+		};
+
+		cpu3_hotplug: cpu3-hotplug {
+			qcom,cpu = <&CPU3>;
+			qcom,cdev-alias = "cpu-hotplug3";
+			#cooling-cells = <2>;
+		};
+	};
+
 	tsens0:tsens@4410000 {
-		//compatible = "qcom,tsens26xx";
+		compatible = "qcom,tsens26xx";
 		reg = <0x04410000 0x20>,
 			<0x04411000 0x140>;
 		reg-names = "tsens_srot_physical",
@@ -139,7 +167,7 @@
 	};
 
 	lmh_cpu_vdd: qcom,lmh-cpu-vdd@f550800 {
-		//compatible = "qcom,lmh-cpu-vdd";
+		compatible = "qcom,lmh-cpu-vdd";
 		reg =  <0xf550800 0x1000>;
 		#cooling-cells = <2>;
 	};

qcom/monaco.dtsi

@@ -351,7 +351,7 @@
 };
 
 &firmware {
-	scm {
+	qcom_scm: scm {
 		compatible = "qcom,scm";
 		qcom,dload-mode = <&tcsr 0x13000>;
 	};

qcom/msm-arm-smmu-parrot.dtsi

@@ -0,0 +1,402 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@3da0000 {
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
+		reg = <0x3da0000 0x40000>,
+			<0x3de6000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x6>;
+		qcom,num-smr-override = <0x6>;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cc_cx_gdsc>;
+
+		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+			 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+			 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+			 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			 <&gpucc GPU_CC_AHB_CLK>;
+		clock-names =
+			"gpu_cc_cx_gmu",
+			"gpu_cc_hub_cx_int",
+			"gpu_cc_hlos1_vote_gpu_smmu",
+			"gcc_gpu_memnoc_gfx",
+			"gcc_gpu_snoc_dvm_gfx",
+			"gpu_cc_ahb";
+
+		qcom,actlr =
+			/* All CBs of GFX: +15 deep PF */
+			<0x000 0x7ff 0x32B>;
+
+		interrupts =	<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+
+		gfx_0_tbu: gfx_0_tbu@3de9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x3de9000 0x1000>,
+				<0x3de6200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,iova-width = <49>;
+		};
+
+		gfx_1_tbu: gfx_1_tbu@3ded000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x3ded000 0x1000>,
+				<0x3de6208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,iova-width = <49>;
+		};
+	};
+
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x151da000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x4e>;
+		qcom,num-smr-override = <0x78>;
+		qcom,handoff-smrs = <0x800 0x402>;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+
+		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,actlr =
+			/* Camera clients, +0 PF */
+			<0x8A0 0x4A0 0x1>,
+			<0xcA0 0x4A0 0x1>,
+			<0x2000 0xE0 0x1>,
+			<0x2100 0x60 0x1>,
+			/* For Display clients, +3 PF */
+			<0x800 0x407 0x103>,
+			<0xc00 0x407 0x103>,
+			/* For video clients, +0 PF */
+			<0x2180 0x27 0x1>,
+			/* NSP clients, +15PF */
+			<0x1000 0x7ff 0x303>;
+
+		interconnects = <&gem_noc MASTER_APPSS_PROC
+				&cnoc3 SLAVE_TCU>;
+		qcom,active-only;
+
+		anoc_1_tbu: anoc_1_tbu@151dd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151dd000 0x1000>,
+				<0x151da200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,iova-width = <36>;
+			qcom,micro-idle;
+			interconnects = <&gem_noc MASTER_APPSS_PROC
+					&cnoc3 SLAVE_IMEM>;
+			qcom,active-only;
+		};
+
+		anoc_2_tbu: anoc_2_tbu@151e1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e1000 0x1000>,
+				<0x151da208  0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,iova-width = <36>;
+			qcom,micro-idle;
+			interconnects = <&gem_noc MASTER_APPSS_PROC
+					&cnoc3 SLAVE_IMEM>;
+			qcom,active-only;
+		};
+
+		mnoc_hf_0_tbu: mnoc_hf_0_tbu@151e5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e5000 0x1000>,
+				<0x151da210 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x800 0x400>;
+			qcom,iova-width = <32>;
+			qcom,micro-idle;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
+			interconnects = <&mmss_noc MASTER_CAMNOC_HF
+					&mc_virt SLAVE_EBI1>;
+			qcom,active-only;
+		};
+
+		mnoc_hf_1_tbu: mnoc_hf_1_tbu@151e9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e9000 0x1000>,
+				<0x151da218 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0xc00 0x400>;
+			qcom,iova-width = <32>;
+			qcom,micro-idle;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
+			interconnects = <&mmss_noc MASTER_CAMNOC_HF
+					&mc_virt SLAVE_EBI1>;
+			qcom,active-only;
+		};
+
+		compute_1_tbu: compute_1_tbu@151ed000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151ed000 0x1000>,
+				<0x151da220 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1000 0x400>;
+			qcom,iova-width = <32>;
+			qcom,micro-idle;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_turing_mmu_tbu1_gdsc>;
+			interconnects = <&nsp_noc MASTER_CDSP_PROC
+					&mc_virt SLAVE_EBI1>;
+			qcom,active-only;
+		};
+
+		compute_0_tbu: compute_0_tbu@151f1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f1000 0x1000>,
+				<0x151da228 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1400 0x400>;
+			qcom,iova-width = <32>;
+			qcom,micro-idle;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>;
+			interconnects = <&nsp_noc MASTER_CDSP_PROC
+					&mc_virt SLAVE_EBI1>;
+			qcom,active-only;
+		};
+
+		lpass_tbu: lpass_tbu@151f5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f5000 0x1000>,
+				<0x151da230 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1800 0x400>;
+			qcom,iova-width = <32>;
+			qcom,micro-idle;
+			interconnects = <&lpass_ag_noc MASTER_LPASS_PROC
+					&mc_virt SLAVE_EBI1>;
+			qcom,active-only;
+		};
+
+		pcie_tbu: pcie_tbu@151f9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f9000 0x1000>,
+				<0x151da238 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1c00 0x400>;
+			qcom,iova-width = <36>;
+			qcom,micro-idle;
+			interconnects = <&pcie_noc MASTER_PCIE_0
+					&mc_virt SLAVE_EBI1>;
+			qcom,active-only;
+		};
+
+		sf_0_tbu: sf_0_tbu@151fd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151fd000 0x1000>,
+				<0x151da240 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2000 0x400>;
+			qcom,iova-width = <32>;
+			qcom,micro-idle;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
+			interconnects = <&mmss_noc MASTER_CAMNOC_SF
+					&mc_virt SLAVE_EBI1>;
+			qcom,active-only;
+		};
+	};
+
+	dma_dev@0x0 {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	iommu_test_device {
+		compatible = "qcom,iommu-debug-test";
+
+		usecase0_apps {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e0 0>;
+		};
+
+		usecase1_apps_fastmap {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e0 0>;
+			qcom,iommu-dma = "fastmap";
+		};
+
+		usecase2_apps_atomic {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e0 0>;
+			qcom,iommu-dma = "atomic";
+		};
+
+		usecase3_apps_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e1 0>;
+			dma-coherent;
+		};
+
+		usecase4_apps_secure {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e0 0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
+		};
+
+		usecase5_kgsl {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x7 0x400>;
+		};
+
+		usecase6_kgsl_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x407 0x400>;
+			dma-coherent;
+		};
+	};
+};

qcom/msm-arm-smmu-sun.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -17,8 +17,7 @@
 		ranges;
 		dma-coherent;
 
-		qcom,regulator-names = "vdd";
-		vdd-supply = <&gpu_cc_cx_gdsc>;
+		power-domains = <&gpucc GPU_CC_CX_GDSC>;
 
 		clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
 		clock-names =

qcom/parrot-4gb.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot-4gb.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot 4Gb SoC";
+	compatible = "qcom,parrot";
+	qcom,board-id = <0 0x600>;
+};

qcom/parrot-4gb.dtsi

@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot.dtsi"
+/ {
+};
+
+&non_secure_display_dma_buf {
+	status = "disabled";
+};
+
+&non_secure_display_memory {
+	status = "disabled";
+};
+
+&mem_client_3_size {
+	qcom,peripheral-size = <0x200000>;
+};
+
+&trust_ui_vm_mem {
+	status = "disabled";
+};
+
+&trust_ui_vm_qrtr {
+	status = "disabled";
+};
+
+&trust_ui_vm_vblk0_ring {
+	status = "disabled";
+};
+
+&trust_ui_vm_swiotlb {
+	status = "disabled";
+};
+
+&soc {
+
+	qcom,guestvm_loader@e0b00000 {
+		status = "disabled";
+	};
+
+	qrtr-gunyah {
+		status = "disabled";
+	};
+
+	qcom,virtio_backend@0 {
+		status = "disabled";
+	};
+
+};

qcom/parrot-atp-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn3990.dtsi"
+#include "parrot-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot ATP";
+	compatible = "qcom,parrot-atp", "qcom,parrot", "qcom,atp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <33 0>;
+};

qcom/parrot-atp.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn3990.dtsi"
+#include "parrot-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot ATP";
+	compatible = "qcom,parrot-atp", "qcom,parrot", "qcom,atp";
+	qcom,board-id = <33 0>;
+};

qcom/parrot-atp.dtsi

@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "parrot-pm7250b.dtsi"
+#include "parrot-pmic-overlay.dtsi"
+#include "parrot-thermal-overlay.dtsi"
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm6450_gpios 1 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4-waipio";
+
+	vdda-phy-supply = <&L5B>;
+	vdda-pll-supply = <&L16B>;
+	vdda-phy-max-microamp = <140000>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+
+	vcc-supply = <&L24B>;
+	vcc-max-microamp = <1200000>;
+
+	vccq-supply = <&L13B>;
+	vccq-max-microamp = <1200000>;
+
+	vccq2-supply = <&L19B>;
+	vccq2-max-microamp = <750000>;
+
+	qcom,vddp-ref-clk-supply = <&L13B>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	/*
+	 * ufs-dev-types and nvmem entries are for ufs device
+	 * identification using nvmem interface. Use number of
+	 * ufs devices supported for ufs-dev-types, and nvmem handle
+	 * added by pmic for sdam register.
+	 *
+	 * Default value taken by driver is bit[0] = 0 for 3.x and
+	 * bit[0] = 1 for 2.x driver code takes this as default case.
+	 *
+	 * But Bit value to identify ufs device is not consistent
+	 * across the targets it could be bit[0] = 0/1 for UFS2.x/3x
+	 * and vice versa. If the bit[0] value is not same as default
+	 * value used in driver and if its reverted then use flag
+	 * qcom,ufs-dev-revert to identify ufs device.
+	 */
+	ufs-dev-types = <2>;
+	qcom,ufs-dev-revert;
+	nvmem-cells = <&ufs_dev>, <&boot_config>;
+	nvmem-cell-names = "ufs_dev", "boot_conf";
+
+	status = "ok";
+};
+
+&battery_charger {
+	qcom,thermal-mitigation = <3000000 1500000 1000000 500000>;
+	qcom,wireless-charging-not-supported;
+};
+
+&qupv3_se9_spi {
+	status = "ok";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	qcom,spi-touch-active = "focaltech,fts_ts";
+
+	focaltech@0 {
+		reg = <0x0>;
+		spi-max-frequency = <6000000>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <65 0x2008>;
+		focaltech,reset-gpio = <&tlmm 64 0x00>;
+		focaltech,irq-gpio = <&tlmm 65 0x2008>;
+		focaltech,display-coords = <0 0 1080 2340>;
+		focaltech,max-touch-number = <5>;
+		focaltech,ic-type = <0x3658D488>;
+		focaltech,touch-type = "primary";
+
+		vdd-supply = <&L28B>;
+
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
+		pinctrl-0 = <&ts_spi_active>;
+		pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
+		pinctrl-2 = <&ts_spi_release>;
+	};
+};
+
+&sdhc_1 {
+	status = "ok";
+
+	vdd-supply = <&L24B>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&L19B>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+};
+
+&sdhc_2 {
+	status = "ok";
+
+	vdd-supply = <&L9E>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&L6E>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+};
+
+&usb0 {
+	usb-role-switch;
+	extcon = <&eud>;
+
+	dwc3@a600000 {
+		usb-role-switch;
+		dr_mode = "otg";
+	};
+
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};

qcom/parrot-dma-heaps.dtsi

@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+		compatible = "qcom,dma-heaps";
+		qcom,secure_cdsp {
+			qcom,dma-heap-name = "qcom,cma-secure-cdsp";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&cdsp_secure_heap>;
+		};
+
+		qcom,adsp {
+			qcom,dma-heap-name = "qcom,adsp";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&sdsp_mem>;
+		};
+
+		qcom,audio_ml {
+			qcom,dma-heap-name = "qcom,audio-ml";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&audio_cma_mem>;
+		};
+
+		non_secure_display_dma_buf: qcom,display {
+			qcom,dma-heap-name = "qcom,display";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			qcom,max-align = <9>;
+			memory-region = <&non_secure_display_memory>;
+		};
+
+		qcom,qseecom {
+			qcom,dma-heap-name = "qcom,qseecom";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_mem>;
+		};
+
+		qcom,qseecom_ta {
+			qcom,dma-heap-name = "qcom,qseecom-ta";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_ta_mem>;
+		};
+	};
+};

qcom/parrot-idp-4gb-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>;
+	qcom,board-id = <34 0x600>;
+};

qcom/parrot-idp-4gb.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot-4gb.dtsi"
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 0x600>;
+};

qcom/parrot-idp-4gb.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp.dtsi"

qcom/parrot-idp-nopmi-overlay.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <34 0>;
+	qcom,pmic-id-size = <9>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+};

qcom/parrot-idp-nopmi.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 0>;
+	qcom,pmic-id-size = <9>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+};

qcom/parrot-idp-overlay.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <34 0>;
+};

qcom/parrot-idp-pm7250b.dtsi

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-pm7250b.dtsi"
+
+/ {
+	qcom,pmic-id-size = <9>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2E>;
+};
+
+&battery_charger {
+	qcom,thermal-mitigation = <3000000 1500000 1000000 500000>;
+	qcom,wireless-charging-not-supported;
+};
+
+&usb0 {
+	usb-role-switch;
+	extcon = <&eud>;
+
+	dwc3@a600000 {
+		usb-role-switch;
+		dr_mode = "otg";
+	};
+
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};

qcom/parrot-idp-pm8350b-overlay.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp.dtsi"
+#include "parrot-idp-pm8350b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <34 0>;
+};

qcom/parrot-idp-pm8350b.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp.dtsi"
+#include "parrot-idp-pm8350b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 0>;
+};

qcom/parrot-idp-pm8350b.dtsi

@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-pm8350b.dtsi"
+
+/ {
+	qcom,pmic-id-size = <9>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x32 0x0 0x0 0x0 0x0 0x0>;
+};
+
+&battery_charger {
+	qcom,thermal-mitigation = <3000000 1500000 1000000 500000>;
+};
+
+&usb0 {
+	usb-role-switch;
+	extcon = <&eud>;
+
+	dwc3@a600000 {
+		usb-role-switch;
+		dr_mode = "otg";
+	};
+
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};

qcom/parrot-idp-wcn3990-4gb-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn3990.dtsi"
+#include "parrot-idp-wcn3990-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR + WCN3990";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>;
+	qcom,board-id = <34 0x601>;
+};

qcom/parrot-idp-wcn3990-4gb.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot-4gb.dtsi"
+#include "parrot-wcn3990.dtsi"
+#include "parrot-idp-wcn3990-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR + WCN3990";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 0x601>;
+};

qcom/parrot-idp-wcn3990-4gb.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp-4gb.dtsi"

qcom/parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn3990.dtsi"
+#include "parrot-idp-wcn3990-amoled-rcm-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP 4GB DDR + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>;
+	qcom,board-id = <34 0x603>;
+};

qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot-4gb.dtsi"
+#include "parrot-wcn3990.dtsi"
+#include "parrot-idp-wcn3990-amoled-rcm-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP 4GB DDR + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 0x603>;
+};

qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp-4gb.dtsi"

qcom/parrot-idp-wcn3990-amoled-rcm-overlay.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn3990.dtsi"
+#include "parrot-idp-wcn3990-amoled-rcm.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <34 3>;
+};

qcom/parrot-idp-wcn3990-amoled-rcm.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn3990.dtsi"
+#include "parrot-idp-wcn3990-amoled-rcm.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 3>;
+};

qcom/parrot-idp-wcn3990-amoled-rcm.dtsi

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp.dtsi"
+
+&soc {
+};
+
+&qupv3_se9_i2c {
+	status = "disabled";
+};
+
+&qupv3_se9_spi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "ok";
+	qcom,touch-active = "goodix,gt9916S";
+
+	goodix-berlin@0 {
+		reg = <0>;
+		spi-max-frequency = <1000000>;
+
+		goodix,avdd-name = "avdd";
+		avdd-supply = <&L28B>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <65 0x2008>;
+		goodix,reset-gpio = <&tlmm 64 0x00>;
+		goodix,irq-gpio = <&tlmm 65 0x2008>;
+		goodix,irq-flags = <2>;
+		goodix,panel-max-x = <1080>;
+		goodix,panel-max-y = <2400>;
+		goodix,panel-max-w = <255>;
+		goodix,panel-max-p = <4096>;
+		goodix,firmware-name = "goodix_firmware_spi.bin";
+		goodix,config-name = "goodix_cfg_group_spi.bin";
+
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
+		pinctrl-0 = <&ts_spi_active>;
+		pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
+		pinctrl-2 = <&ts_spi_release>;
+
+		qcom,touch-environment = "pvm";
+	};
+};

qcom/parrot-idp-wcn3990-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+#include "parrot-wcn3990.dtsi"
+#include "parrot-idp-wcn3990.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP + WCN3990";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <34 1>;
+};

qcom/parrot-idp-wcn3990.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn3990.dtsi"
+#include "parrot-idp-wcn3990.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP + WCN3990";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 1>;
+};

qcom/parrot-idp-wcn3990.dtsi

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp.dtsi"
+
+&soc {
+};

qcom/parrot-idp-wcn6750-amoled-4gb-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-wcn6750-amoled-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>;
+	qcom,board-id = <34 0x604>;
+};

qcom/parrot-idp-wcn6750-amoled-4gb.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot-4gb.dtsi"
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-wcn6750-amoled-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 0x604>;
+};

qcom/parrot-idp-wcn6750-amoled-4gb.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp-4gb.dtsi"

qcom/parrot-idp-wcn6750-amoled-overlay.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-wcn6750-amoled.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <34 4>;
+};

qcom/parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-wcn6750-amoled-rcm-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>;
+	qcom,board-id = <34 0x602>;
+};

qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot-4gb.dtsi"
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-wcn6750-amoled-rcm-4gb.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 0x602>;
+};

qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp-4gb.dtsi"

qcom/parrot-idp-wcn6750-amoled-rcm-overlay.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-wcn6750-amoled-rcm.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <34 2>;
+};

qcom/parrot-idp-wcn6750-amoled-rcm.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-wcn6750-amoled-rcm.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 2>;
+};

qcom/parrot-idp-wcn6750-amoled-rcm.dtsi

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp.dtsi"
+
+&soc {
+};
+
+&qupv3_se9_i2c {
+	status = "disabled";
+};
+
+&qupv3_se9_spi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "ok";
+	qcom,touch-active = "goodix,gt9916S";
+
+	goodix-berlin@0 {
+		reg = <0>;
+		spi-max-frequency = <1000000>;
+
+		goodix,avdd-name = "avdd";
+		avdd-supply = <&L28B>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <65 0x2008>;
+		goodix,reset-gpio = <&tlmm 64 0x00>;
+		goodix,irq-gpio = <&tlmm 65 0x2008>;
+		goodix,irq-flags = <2>;
+		goodix,panel-max-x = <1080>;
+		goodix,panel-max-y = <2400>;
+		goodix,panel-max-w = <255>;
+		goodix,panel-max-p = <4096>;
+		goodix,firmware-name = "goodix_firmware_spi.bin";
+		goodix,config-name = "goodix_cfg_group_spi.bin";
+
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
+		pinctrl-0 = <&ts_spi_active>;
+		pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
+		pinctrl-2 = <&ts_spi_release>;
+
+		qcom,touch-environment = "pvm";
+	};
+};

qcom/parrot-idp-wcn6750-amoled.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp-wcn6750-amoled.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 4>;
+};

qcom/parrot-idp-wcn6750-amoled.dtsi

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-idp.dtsi"
+
+&soc {
+};
+
+&qupv3_se9_i2c {
+	status = "disabled";
+};
+
+&qupv3_se9_spi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "ok";
+	qcom,touch-active = "goodix,gt9916S";
+
+	goodix-berlin@0 {
+		reg = <0>;
+		spi-max-frequency = <1000000>;
+
+		goodix,avdd-name = "avdd";
+		avdd-supply = <&L28B>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <65 0x2008>;
+		goodix,reset-gpio = <&tlmm 64 0x00>;
+		goodix,irq-gpio = <&tlmm 65 0x2008>;
+		goodix,irq-flags = <2>;
+		goodix,panel-max-x = <1080>;
+		goodix,panel-max-y = <2400>;
+		goodix,panel-max-w = <255>;
+		goodix,panel-max-p = <4096>;
+		goodix,firmware-name = "goodix_firmware_spi.bin";
+		goodix,config-name = "goodix_cfg_group_spi.bin";
+
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
+		pinctrl-0 = <&ts_spi_active>;
+		pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
+		pinctrl-2 = <&ts_spi_release>;
+
+		qcom,touch-environment = "pvm";
+	};
+};

qcom/parrot-idp.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn6750.dtsi"
+#include "parrot-idp.dtsi"
+#include "parrot-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,board-id = <34 0>;
+};

qcom/parrot-idp.dtsi

@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "parrot-pmic-overlay.dtsi"
+#include "parrot-thermal-overlay.dtsi"
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm6450_gpios 1 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+};
+
+&pm6450_pwm_1 {
+	status = "ok";
+};
+
+&qupv3_se9_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "ok";
+	qcom,i2c-touch-active = "novatek,NVT-ts";
+
+	novatek@62 {
+		reg = <0x62>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <13 0x2008>;
+
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+			"pmx_ts_release";
+
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+
+		novatek,reset-gpio = <&tlmm 12 0x00>;
+		novatek,irq-gpio = <&tlmm 13 0x2008>;
+
+		novatek,trusted-touch-mode = "vm_mode";
+		novatek,touch-environment = "pvm";
+		novatek,trusted-touch-spi-irq = <566>;
+		novatek,trusted-touch-io-bases = <0xa8c000 0xa10000>;
+		novatek,trusted-touch-io-sizes = <0x1000 0x4000>;
+		novatek,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0
+						&tlmm 12 0 &tlmm 13 0x2008>;
+	};
+
+	focaltech@38 {
+		status = "disabled";
+		reg = <0x38>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <13 0x2008>;
+		focaltech,reset-gpio = <&tlmm 12 0x00>;
+		focaltech,irq-gpio = <&tlmm 13 0x2008>;
+		focaltech,display-coords = <0 0 1080 2408>;
+		focaltech,max-touch-number = <5>;
+		focaltech,ic-type = <0x8726081C>;
+		focaltech,touch-type = "primary";
+
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+	};
+};
+
+&sdhc_1 {
+	status = "ok";
+
+	vdd-supply = <&L24B>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&L19B>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+};
+
+&sdhc_2 {
+	status = "ok";
+
+	vdd-supply = <&L9E>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&L6E>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4-waipio";
+
+	vdda-phy-supply = <&L5B>;
+	vdda-pll-supply = <&L16B>;
+	vdda-phy-max-microamp = <140000>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+
+	vcc-supply = <&L24B>;
+	vcc-max-microamp = <1200000>;
+
+	vccq-supply = <&L13B>;
+	vccq-max-microamp = <1200000>;
+
+	vccq2-supply = <&L19B>;
+	vccq2-max-microamp = <750000>;
+
+	qcom,vddp-ref-clk-supply = <&L13B>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	/*
+	 * ufs-dev-types and nvmem entries are for ufs device
+	 * identification using nvmem interface. Use number of
+	 * ufs devices supported for ufs-dev-types, and nvmem handle
+	 * added by pmic for sdam register.
+	 *
+	 * Default value taken by driver is bit[0] = 0 for 3.x and
+	 * bit[0] = 1 for 2.x driver code takes this as default case.
+	 *
+	 * But Bit value to identify ufs device is not consistent
+	 * across the targets it could be bit[0] = 0/1 for UFS2.x/3x
+	 * and vice versa. If the bit[0] value is not same as default
+	 * value used in driver and if its reverted then use flag
+	 * qcom,ufs-dev-revert to identify ufs device.
+	 */
+	ufs-dev-types = <2>;
+	qcom,ufs-dev-revert;
+	nvmem-cells = <&ufs_dev>, <&boot_config>;
+	nvmem-cell-names = "ufs_dev", "boot_conf";
+
+	status = "ok";
+};

qcom/parrot-pm7250b.dtsi

@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/thermal/thermal_qti.h>
+#include "pm7250b.dtsi"
+
+&soc {
+	qcom,pmic_glink {
+		status = "okay";
+	};
+
+	qcom,pmic_glink_log {
+		compatible = "qcom,pmic-glink";
+		qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
+
+		qcom,battery_debug {
+			compatible = "qcom,battery-debug";
+		};
+
+		qcom,charger_ulog_glink {
+			compatible = "qcom,charger-ulog-glink";
+		};
+
+		spmi_glink_debug: qcom,spmi_glink_debug {
+			compatible = "qcom,spmi-glink-debug";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			depends-on-supply = <&spmi1_bus>;
+
+			/* Primary SPMI bus */
+			spmi@0 {
+				reg = <0>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				qcom,pm7250b-debug@8 {
+					compatible = "qcom,spmi-pmic";
+					reg = <8 SPMI_USID>;
+					qcom,can-sleep;
+				};
+			};
+
+			/* Secondary SPMI bus */
+			spmi@1 {
+				reg = <1>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				smb1394_glink_debug: qcom,smb1394-debug@9 {
+					compatible = "qcom,spmi-pmic";
+					reg = <9 SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+				qcom,smb1394-debug@b {
+					compatible = "qcom,spmi-pmic";
+					reg = <11 SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+				qcom,smb1394-debug@c {
+					compatible = "qcom,spmi-pmic";
+					reg = <12 SPMI_USID>;
+					qcom,can-sleep;
+				};
+			};
+		};
+	};
+};
+
+&glink_edge {
+	qcom,pmic_glink_rpmsg {
+		qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
+	};
+
+	qcom,pmic_glink_log_rpmsg {
+		qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
+		qcom,intents = <0x800  5
+			0xc00 3
+			0x2000 1>;
+	};
+};
+
+&battery_charger {
+	status = "okay";
+};
+
+&ucsi {
+	status = "okay";
+};
+
+&altmode {
+	status = "okay";
+};
+
+&spmi0_debug_bus {
+	depends-on2-supply = <&smb1394_glink_debug>;
+
+	qcom,pm7250b-debug@8 {
+		compatible = "qcom,spmi-pmic";
+		reg = <8 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		qcom,can-sleep;
+	};
+
+	qcom,pm7250b-debug@9 {
+		compatible = "qcom,spmi-pmic";
+		reg = <9 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		qcom,can-sleep;
+	};
+};
+
+&pm7250b_2 {
+	/* Slave ID - 8 */
+	reg = <8 SPMI_USID>;
+};
+
+&pm7250b_3 {
+	/* Slave ID - 9 */
+	reg = <9 SPMI_USID>;
+};
+
+&pm7250b_clkdiv {
+	clocks = <&rpmhcc RPMH_CXO_CLK>;
+};
+
+&pm7250b_vadc {
+	interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+	smb1390_therm@e {
+		qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
+	};
+
+	pm7250b_usb_conn_therm {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		label = "pm7250b_usb_conn_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm7250b_smb_skin_therm {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		label = "pm7250b_smb_skin_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm7250b_adc_tm {
+	interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+	io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
+			<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>;
+
+	pm7250b_usb_conn_therm {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pm7250b_smb_skin_therm {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&thermal_zones {
+	socd {
+		cooling-maps {
+			socd_apc1 {
+				trip = <&socd_trip>;
+				cooling-device = <&APC1_pause 1 1>;
+			};
+
+			socd_cdsp1 {
+				trip = <&socd_trip>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+
+			socd_gpu0 {
+				trip = <&socd_trip>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pm7250b-ibat-lvl0 {
+		trips {
+			ibat-lvl0 {
+				temperature = <6000>;
+			};
+		};
+	};
+
+	pm7250b-ibat-lvl1 {
+		trips {
+			ibat-lvl1 {
+				temperature = <7500>;
+			};
+		};
+	};
+
+	pm7250b-bcl-lvl0 {
+		cooling-maps {
+			vbat_lte0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			vbat_nr0_scg {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_nr_scg_dsc 3 3>;
+			};
+
+			vbat_nr0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_nr_dsc 6 6>;
+			};
+
+			vbat_cdsp0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cdsp_sw 2 2>;
+			};
+
+			vbat_cpu_5 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			vbat_gpu0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+		};
+	};
+
+	pm7250b-bcl-lvl1 {
+		cooling-maps {
+			vbat_lte1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&modem_lte_dsc 10 10>;
+			};
+
+			vbat_nr1_scg {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&modem_nr_scg_dsc 10 10>;
+			};
+
+			vbat_nr1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&modem_nr_dsc 9 9>;
+			};
+
+			vbat_cdsp1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+
+			vbat_cpu_6_7 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cpu_6_7_pause 1 1>;
+			};
+
+			vbat_gpu1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pm7250b-bcl-lvl2 {
+		cooling-maps {
+			vbat_cdsp2 {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
+			};
+
+			vbat_gpu2 {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	sys-therm-7 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors =  <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-6 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors =  <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+
+&pm7250b_tz {
+	interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+};
+
+&pm7250b_bcl {
+	interrupts = <0x8 0x1d 0x0 IRQ_TYPE_EDGE_RISING>,
+		   <0x8 0x1d 0x1 IRQ_TYPE_EDGE_RISING>,
+		   <0x8 0x1d 0x2 IRQ_TYPE_EDGE_RISING>;
+};

qcom/parrot-pm8350b.dtsi

@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-smb139x.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&pm6150a_amoled {
+	/delete-node/ oledb@e000;
+	/delete-node/ ab@de00;
+	/delete-node/ ibb@dc00;
+};
+
+#include "pm8350b.dtsi"
+
+&soc {
+	qcom,pmic_glink {
+		status = "okay";
+	};
+
+	qcom,pmic_glink_log {
+		compatible = "qcom,pmic-glink";
+		qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
+
+		qcom,battery_debug {
+			compatible = "qcom,battery-debug";
+		};
+
+		qcom,charger_ulog_glink {
+			compatible = "qcom,charger-ulog-glink";
+		};
+
+		spmi_glink_debug: qcom,spmi_glink_debug {
+			compatible = "qcom,spmi-glink-debug";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			depends-on-supply = <&spmi1_bus>;
+
+			/* Primary SPMI bus */
+			spmi@0 {
+				reg = <0>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				qcom,pm8350b-debug@3 {
+					compatible = "qcom,spmi-pmic";
+					reg = <3 SPMI_USID>;
+					qcom,can-sleep;
+				};
+			};
+
+			/* Secondary SPMI bus */
+			spmi@1 {
+				reg = <1>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				smb1394_glink_debug: qcom,smb1394-debug@9 {
+					compatible = "qcom,spmi-pmic";
+					reg = <9 SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+				qcom,smb1394-debug@b {
+					compatible = "qcom,spmi-pmic";
+					reg = <11 SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+				qcom,smb1394-debug@c {
+					compatible = "qcom,spmi-pmic";
+					reg = <12 SPMI_USID>;
+					qcom,can-sleep;
+				};
+			};
+		};
+	};
+};
+
+&glink_edge {
+	qcom,pmic_glink_rpmsg {
+		qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
+	};
+
+	qcom,pmic_glink_log_rpmsg {
+		qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
+		qcom,intents = <0x800  5
+			0xc00 3
+			0x2000 1>;
+	};
+};
+
+&battery_charger {
+	status = "okay";
+};
+
+&ucsi {
+	status = "okay";
+};
+
+&altmode {
+	status = "okay";
+};
+
+&spmi0_debug_bus {
+	depends-on2-supply = <&smb1394_glink_debug>;
+
+	qcom,pm8350b-debug@3 {
+		compatible = "qcom,spmi-pmic";
+		reg = <3 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		qcom,can-sleep;
+	};
+};
+
+&apps_rsc_drv2 {
+	rpmh-regulator-ldod1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldod1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1D: pm8350b_l1: regulator-pm8350b-l1 {
+			regulator-name = "pm8350b_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1296000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&pmk8350_sdam_2 {
+	hap_cl_brake: cl_brake@7c {
+		reg = <0x7c 0x1>;
+		bits = <0 8>;
+	};
+};
+
+&pm8350b_haptics {
+	nvmem-cell-names = "hap_cl_brake";
+	nvmem-cells = <&hap_cl_brake>;
+	nvmem-names = "hap_cfg_sdam";
+	nvmem = <&pmk8350_sdam_46>;
+	qcom,pbs-client = <&pm8350b_pbs2>;
+};
+
+&pmk8350_vadc {
+	pm8350b_ref_gnd {
+		reg = <PM8350B_ADC7_REF_GND>;
+		label = "pm8350b_ref_gnd";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350b_vref_1p25 {
+		reg = <PM8350B_ADC7_1P25VREF>;
+		label = "pm8350b_vref_1p25";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350b_die_temp {
+		reg = <PM8350B_ADC7_DIE_TEMP>;
+		label = "pm8350b_die_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350b_vph_pwr {
+		reg = <PM8350B_ADC7_VPH_PWR>;
+		label = "pm8350b_vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	pm8350b_vbat_sns {
+		reg = <PM8350B_ADC7_VBAT_SNS>;
+		label = "pm8350b_vbat_sns";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	pm8350b_chg_temp {
+		reg = <PM8350B_ADC7_CHG_TEMP>;
+		label = "pm8350b_chg_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350b_iin_fb {
+		reg = <PM8350B_ADC7_IIN_FB>;
+		label = "pm8350b_iin_fb";
+		qcom,pre-scaling = <32 100>;
+	};
+
+	pm8350b_ichg_fb {
+		reg = <PM8350B_ADC7_ICHG_FB>;
+		label = "pm8350b_ichg_fb";
+		qcom,pre-scaling = <1000 305185>;
+	};
+
+	pm8350b_usb_in_v_div_16 {
+		reg = <PM8350B_ADC7_USB_IN_V_16>;
+		label = "pm8350b_usb_in_v_div_16";
+		qcom,pre-scaling = <1 16>;
+	};
+
+	smb139x_1_smb_temp {
+		reg = <SMB1394_1_ADC7_SMB_TEMP>;
+		label = "smb139x_1_smb_temp";
+		qcom,hw-settle-time = <200>;
+	};
+
+	smb139x_1_ichg_smb {
+		reg = <SMB1394_1_ADC7_ICHG_SMB>;
+		label = "smb139x_1_ichg_smb";
+		qcom,hw-settle-time = <200>;
+	};
+
+	smb139x_1_iin_smb {
+		reg = <SMB1394_1_ADC7_IIN_SMB>;
+		label = "smb139x_1_iin_smb";
+		qcom,hw-settle-time = <200>;
+	};
+
+	smb139x_2_smb_temp {
+		reg = <SMB1394_2_ADC7_SMB_TEMP>;
+		label = "smb139x_2_smb_temp";
+		qcom,hw-settle-time = <200>;
+	};
+
+	smb139x_2_ichg_smb {
+		reg = <SMB1394_2_ADC7_ICHG_SMB>;
+		label = "smb139x_2_ichg_smb";
+		qcom,hw-settle-time = <200>;
+	};
+
+	smb139x_2_iin_smb {
+		reg = <SMB1394_2_ADC7_IIN_SMB>;
+		label = "smb139x_2_iin_smb";
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&pm8350b_tz {
+	io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&thermal_zones {
+	socd {
+		trips {
+			socd-trip {
+				temperature = <90>;
+				hysteresis = <1>;
+			};
+		};
+
+		cooling-maps {
+			socd_apc1 {
+				trip = <&socd_trip>;
+				cooling-device = <&APC1_pause 1 1>;
+			};
+
+			socd_cdsp1 {
+				trip = <&socd_trip>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+
+			socd_gpu0 {
+				trip = <&socd_trip>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pm8350b-ibat-lvl0 {
+		trips {
+			ibat-lvl0 {
+				temperature = <6000>;
+			};
+		};
+	};
+
+	pm8350b-ibat-lvl1 {
+		trips {
+			ibat-lvl1 {
+				temperature = <7500>;
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl0 {
+		cooling-maps {
+			vbat_lte0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			vbat_nr0_scg {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_nr_scg_dsc 3 3>;
+			};
+
+			vbat_nr0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_nr_dsc 6 6>;
+			};
+
+			vbat_cdsp0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cdsp_sw 2 2>;
+			};
+
+			vbat_cpu_5 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			vbat_gpu0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl1 {
+		cooling-maps {
+			vbat_lte1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&modem_lte_dsc 10 10>;
+			};
+
+			vbat_nr1_scg {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&modem_nr_scg_dsc 10 10>;
+			};
+
+			vbat_nr1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&modem_nr_dsc 9 9>;
+			};
+
+			vbat_cdsp1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+
+			vbat_cpu_6_7 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cpu_6_7_pause 1 1>;
+			};
+
+			vbat_gpu1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl2 {
+		cooling-maps {
+			vbat_cdsp2 {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
+			};
+
+			vbat_gpu2 {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};

qcom/parrot-pmic-overlay.dtsi

@@ -0,0 +1,700 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm6450.h>
+
+#define PMR735A_SID	6
+
+#include "pmk8350.dtsi"
+#include "pm6450.dtsi"
+#include "pm6150l.dtsi"
+#include "pmr735a.dtsi"
+
+&soc {
+	reboot_reason {
+		compatible = "qcom,reboot-reason";
+		nvmem-cells = <&restart_reason>;
+		nvmem-cell-names = "restart_reason";
+	};
+
+	pmic-pon-log {
+		compatible = "qcom,pmic-pon-log";
+		nvmem = <&pmk8350_sdam_5>;
+		nvmem-names = "pon_log";
+	};
+};
+
+&pmk8350 {
+	/delete-node/ pon_pbs@800;
+	/delete-node/ pon_hlos@1300;
+
+	pon_hlos@1300 {
+		compatible = "qcom,pm8998-pon";
+		reg = <0x1300>, <0x800>;
+		reg-names = "pon_hlos", "pon_pbs";
+		qcom,log-kpd-event;
+
+		pwrkey {
+			compatible = "qcom,pmk8350-pwrkey";
+			interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+			linux,code = <KEY_POWER>;
+		};
+
+		resin {
+			compatible = "qcom,pmk8350-resin";
+			interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+};
+
+&pmk8350_vadc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&quiet_therm_default>;
+
+	/delete-node/ pm8350_ref_gnd;
+	/delete-node/ pm8350_vref_1p25;
+	/delete-node/ pm8350_die_temp;
+	/delete-node/ pm8350_vph_pwr;
+
+	/delete-node/ pm8350b_ref_gnd;
+	/delete-node/ pm8350b_vref_1p25;
+	/delete-node/ pm8350b_die_temp;
+	/delete-node/ pm8350b_vph_pwr;
+	/delete-node/ pm8350b_vbat_sns;
+
+	/delete-node/ pmr735b_ref_gnd;
+	/delete-node/ pmr735b_vref_1p25;
+	/delete-node/ pmr735b_die_temp;
+
+	/* PM6450 Channel nodes */
+	pm6450_ref_gnd {
+		reg = <PM6450_ADC7_REF_GND>;
+		label = "pm6450_ref_gnd";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm6450_vref_1p25 {
+		reg = <PM6450_ADC7_1P25VREF>;
+		label = "pm6450_vref_1p25";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm6450_die_temp {
+		reg = <PM6450_ADC7_DIE_TEMP>;
+		label = "pm6450_die_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm6450_quiet_therm {
+		reg = <PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
+		label = "pm6450_quiet_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pmk8350_adc_tm {
+	io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>,
+			<&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
+
+	pmk8350_xo_therm {
+		reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pm6450_quiet_therm {
+		reg = <PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&pmk8350_sdam_23 {
+	adc_scaling: scaling@bf {
+		reg = <0xbf 0x1>;
+		bits = <0 2>;
+	};
+};
+
+&pmk8350_sdam_1 {
+	ufs_dev: ufs_dev@94 {
+		reg = <0x94 0x1>;
+		bits = <0 0>;
+	};
+};
+
+&pm6450_gpios {
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio1";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+
+	quiet_therm {
+		quiet_therm_default: quiet_therm_default {
+			pins = "gpio2";
+			bias-high-impedance;
+		};
+	};
+
+	pm8010i_reset {
+		pm8010i_active: pm8010i_active {
+			pins = "gpio3";
+			function = "normal";
+			bias-disable;
+			output-high;
+			power-source = <0>;
+		};
+	};
+
+	pm8010j_reset {
+		pm8010j_active: pm8010j_active {
+			pins = "gpio4";
+			function = "normal";
+			bias-disable;
+			output-high;
+			power-source = <0>;
+		};
+	};
+};
+
+&pm6150l_revid {
+	status = "disabled";
+};
+
+&pm6150l_4 {
+	qcom,power-on@800 {
+		status = "disabled";
+	};
+};
+
+&pm6150l_clkdiv {
+	clocks = <&rpmhcc RPMH_CXO_CLK>;
+};
+
+&pm6150l_vadc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ufs_therm_default &wide_rfc_therm_default>;
+
+	pa_therm2 {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		label = "pa_therm2";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pa_therm1 {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		label = "pa_therm1";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	ufs_therm {
+		reg = <ADC5_GPIO1_100K_PU>;
+		label = "ufs_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	wide_rfc_therm {
+		reg = <ADC5_GPIO3_100K_PU>;
+		label = "wide_rfc_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm6150l_gpios {
+	ufs_therm {
+		ufs_therm_default: ufs_therm_default {
+			pins = "gpio5";
+			bias-high-impedance;
+		};
+	};
+
+	wide_rfc_therm {
+		wide_rfc_therm_default: wide_rfc_therm_default {
+			pins = "gpio7";
+			bias-high-impedance;
+		};
+	};
+};
+
+&pm6150l_adc_tm {
+	io-channels = <&pm6150l_vadc ADC5_AMUX_THM1_100K_PU>,
+			<&pm6150l_vadc ADC5_AMUX_THM3_100K_PU>,
+			<&pm6150l_vadc ADC5_GPIO1_100K_PU>,
+			<&pm6150l_vadc ADC5_GPIO3_100K_PU>;
+
+	/* Channel nodes */
+	pa_therm2 {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pa_therm1 {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	ufs_therm {
+		reg = <ADC5_GPIO1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	wide_rfc_therm {
+		reg = <ADC5_GPIO3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&flash_led {
+	status = "ok";
+	qcom,use-qti-battery-interface;
+};
+
+&pmr735a_spmi {
+	reg = <6 SPMI_USID>;
+};
+
+&pmr735a_tz {
+	interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+	io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&thermal_zones {
+	xo-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO1_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO3_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-4 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM1_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-5 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM3_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+/*
+ * Each QUP device that's a parent to PMIC must be listed as a critical device
+ * to GCC
+ */
+&gcc {
+	qcom,critical-devices = <&qupv3_se2_i2c>;
+};
+
+&qupv3_se2_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "ok";
+
+	pm8010i@8 {
+		compatible = "qcom,i2c-pmic";
+		reg = <0x8>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pm8010i_active>;
+
+		pm8010-chip@900 {
+			reg = <0x900>;
+
+			PM8010I_EN: qcom,pm8008-chip-en {
+				regulator-name = "pm8010i-chip-en";
+			};
+		};
+
+		qcom,revid@100 {
+			reg = <0x100>;
+		};
+	};
+
+	pm8010i@9 {
+		compatible = "qcom,i2c-pmic";
+		reg = <0x9>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm8010i-regulator {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pm8008_en-supply = <&PM8010I_EN>;
+			vdd_l1_l2-supply = <&S8B>;
+			vdd_l3_l4-supply = <&BOB>;
+			vdd_l5-supply = <&BOB>;
+			vdd_l6-supply = <&BOB>;
+			vdd_l7-supply = <&BOB>;
+
+			L1I: pm8010i_l1: regulator@4000 {
+				reg = <0x4000>;
+				regulator-name = "pm8010i_l1";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1200000>;
+				qcom,min-dropout-voltage = <88000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L2I: pm8010i_l2: regulator@4100 {
+				reg = <0x4100>;
+				regulator-name = "pm8010i_l2";
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <1150000>;
+				qcom,min-dropout-voltage = <64000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L3I: pm8010i_l3: regulator@4200 {
+				reg = <0x4200>;
+				regulator-name = "pm8010i_l3";
+				regulator-min-microvolt = <1328000>;
+				regulator-max-microvolt = <3000000>;
+				qcom,min-dropout-voltage = <176000>;
+				qcom,hpm-min-load = <0>;
+			};
+
+			L4I: pm8010i_l4: regulator@4300 {
+				reg = <0x4300>;
+				regulator-name = "pm8010i_l4";
+				regulator-min-microvolt = <1376000>;
+				regulator-max-microvolt = <2900000>;
+				qcom,min-dropout-voltage = <128000>;
+				qcom,hpm-min-load = <0>;
+			};
+
+			L6I: pm8010i_l6: regulator@4500 {
+				reg = <0x4500>;
+				regulator-name = "pm8010i_l6";
+				regulator-min-microvolt = <1376000>;
+				regulator-max-microvolt = <2900000>;
+				qcom,min-dropout-voltage = <128000>;
+				qcom,hpm-min-load = <0>;
+			};
+
+			L7I: pm8010i_l7: regulator@4600 {
+				reg = <0x4600>;
+				regulator-name = "pm8010i_l7";
+				regulator-min-microvolt = <1248000>;
+				regulator-max-microvolt = <3000000>;
+				qcom,min-dropout-voltage = <256000>;
+				qcom,hpm-min-load = <0>;
+			};
+		};
+	};
+
+	pm8010j@c {
+		compatible = "qcom,i2c-pmic";
+		reg = <0xc>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pm8010j_active>;
+
+		pm8010-chip@900 {
+			reg = <0x900>;
+
+			PM8010J_EN: qcom,pm8008-chip-en {
+				regulator-name = "pm8010j-chip-en";
+			};
+		};
+
+		qcom,revid@100 {
+			reg = <0x100>;
+		};
+	};
+
+	pm8010j@d {
+		compatible = "qcom,i2c-pmic";
+		reg = <0xd>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm8010j-regulator {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pm8008_en-supply = <&PM8010J_EN>;
+			vdd_l1_l2-supply = <&S8B>;
+			vdd_l3_l4-supply = <&S8E>;
+			vdd_l5-supply = <&BOB>;
+			vdd_l6-supply = <&BOB>;
+			vdd_l7-supply = <&BOB>;
+
+			L1J: pm8010j_l1: regulator@4000 {
+				reg = <0x4000>;
+				regulator-name = "pm8010j_l1";
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <1150000>;
+				qcom,min-dropout-voltage = <48000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L3J: pm8010j_l3: regulator@4200 {
+				reg = <0x4200>;
+				regulator-name = "pm8010j_l3";
+				regulator-min-microvolt = <1744000>;
+				regulator-max-microvolt = <1900000>;
+				qcom,min-dropout-voltage = <72000>;
+				qcom,hpm-min-load = <0>;
+			};
+
+			L4J: pm8010j_l4: regulator@4300 {
+				reg = <0x4300>;
+				regulator-name = "pm8010j_l4";
+				regulator-min-microvolt = <1664000>;
+				regulator-max-microvolt = <1888000>;
+				qcom,min-dropout-voltage = <152000>;
+				qcom,hpm-min-load = <0>;
+			};
+
+			L6J: pm8010j_l6: regulator@4500 {
+				reg = <0x4500>;
+				regulator-name = "pm8010j_l6";
+				regulator-min-microvolt = <1376000>;
+				regulator-max-microvolt = <2900000>;
+				qcom,min-dropout-voltage = <128000>;
+				qcom,hpm-min-load = <0>;
+			};
+		};
+	};
+};
+
+&soc {
+	display_panel_vddio: display_gpio_regulator@1 {
+		compatible = "qti-regulator-fixed";
+		regulator-name = "display_panel_vddio";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-enable-ramp-delay = <233>;
+		gpio = <&pm6150l_gpios 9 0>;
+		enable-active-high;
+		regulator-boot-on;
+		proxy-supply = <&display_panel_vddio>;
+		qcom,proxy-consumer-enable;
+		pinctrl-names = "default";
+		pinctrl-0 = <&display_panel_vddio_default>;
+	};
+
+	display_panel_avdd: display_gpio_regulator@2 {
+		compatible = "qti-regulator-fixed";
+		regulator-name = "display_panel_avdd";
+		regulator-min-microvolt = <5500000>;
+		regulator-max-microvolt = <5500000>;
+		regulator-enable-ramp-delay = <233>;
+		gpio = <&pm6150l_gpios 4 0>;
+		enable-active-high;
+		regulator-boot-on;
+		proxy-supply = <&display_panel_avdd>;
+		qcom,proxy-consumer-enable;
+		pinctrl-names = "default";
+		pinctrl-0 = <&display_panel_avdd_default>;
+	};
+
+	display_panel_extvdd: display_gpio_regulator@3 {
+		compatible = "qti-regulator-fixed";
+		regulator-name = "display_panel_extvdd";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-enable-ramp-delay = <233>;
+		gpio = <&pm6150l_gpios 3 0>;
+		enable-active-high;
+		regulator-boot-on;
+		proxy-supply = <&display_panel_extvdd>;
+		qcom,proxy-consumer-enable;
+		pinctrl-names = "default";
+		pinctrl-0 = <&display_panel_extvdd_default>;
+	};
+
+	display_panel_ibb: display_panel_ibb_stub {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "display_panel_ibb";
+		regulator-min-microvolt = <4600000>;
+		regulator-max-microvolt = <6000000>;
+	};
+};
+
+&pm6150l_gpios {
+	display_panel_supply_ctrl {
+		display_panel_vddio_default: display_panel_vddio_default {
+			pins = "gpio9";
+			function = "normal";
+			input-disable;
+			output-enable;
+			bias-disable;
+			power-source = <0>;
+			qcom,drive-strength = <2>;
+		};
+
+		display_panel_avdd_default: display_panel_avdd_default {
+			pins = "gpio4";
+			function = "normal";
+			input-disable;
+			output-enable;
+			bias-disable;
+			power-source = <0>;
+			qcom,drive-strength = <2>;
+		};
+
+		display_panel_extvdd_default: display_panel_extvdd_default {
+			pins = "gpio3";
+			function = "normal";
+			input-disable;
+			output-enable;
+			bias-disable;
+			power-source = <0>;
+			qcom,drive-strength = <2>;
+		};
+	};
+
+	lcd_backlight_ctrl {
+		lcd_backlight_en_default: lcd_backlight_en_default {
+			pins = "gpio10";
+			function = "normal";
+			input-disable;
+			output-enable;
+			bias-disable;
+			power-source = <0>;
+			qcom,drive-strength = <2>;
+		};
+	};
+};
+
+&pm6450_gpios {
+	lcd_backlight_ctrl {
+		lcd_backlight_pwm_default: lcd_backlight_pwm_default {
+			pins = "gpio7";
+			function = "func1";
+			input-disable;
+			output-enable;
+			bias-disable;
+			power-source = <1>;       /* 1.8V */
+			qcom,drive-strength = <2>;
+		};
+	};
+};

qcom/parrot-qrd-4gb-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn3990.dtsi"
+#include "parrot-qrd-4gb.dtsi"
+#include "parrot-qrd-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot QRD 4GB DDR";
+	compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
+	qcom,msm-id = <537 0x10000>;
+	qcom,board-id = <0x1000B 0x600>;
+};

qcom/parrot-qrd-4gb.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot-4gb.dtsi"
+#include "parrot-wcn3990.dtsi"
+#include "parrot-qrd-4gb.dtsi"
+#include "parrot-qrd-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot QRD 4GB DDR";
+	compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
+	qcom,board-id = <0x1000B 0x600>;
+};

qcom/parrot-qrd-4gb.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-qrd.dtsi"

qcom/parrot-qrd-nopmi-overlay.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn3990.dtsi"
+#include "parrot-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot QRD";
+	compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <0x1000B 0>;
+	qcom,pmic-id-size = <9>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+};

qcom/parrot-qrd-nopmi.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn3990.dtsi"
+#include "parrot-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot QRD";
+	compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+	qcom,pmic-id-size = <9>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+};

qcom/parrot-qrd-overlay.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn3990.dtsi"
+#include "parrot-qrd.dtsi"
+#include "parrot-qrd-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot QRD";
+	compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <0x1000B 0>;
+};

qcom/parrot-qrd-pm7250b.dtsi

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-pm7250b.dtsi"
+
+/ {
+	qcom,pmic-id-size = <9>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2E>;
+};
+
+&battery_charger {
+	qcom,thermal-mitigation = <11500000 11000000 10500000 10000000 9500000
+				9000000 8500000 8000000 7500000 7000000 6500000
+				6000000 5500000 5000000 4500000 4000000 3500000
+				3000000 2500000 2000000 1500000 1000000 500000>;
+	qcom,wireless-charging-not-supported;
+};
+
+&usb0 {
+	usb-role-switch;
+	extcon = <&eud>;
+
+	dwc3@a600000 {
+		usb-role-switch;
+		dr_mode = "otg";
+	};
+
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};

qcom/parrot-qrd-pm8350b-overlay.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn3990.dtsi"
+#include "parrot-qrd.dtsi"
+#include "parrot-qrd-pm8350b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot QRD";
+	compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <0x1000B 0>;
+};

qcom/parrot-qrd-pm8350b.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "parrot.dtsi"
+#include "parrot-wcn3990.dtsi"
+#include "parrot-qrd.dtsi"
+#include "parrot-qrd-pm8350b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot QRD";
+	compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+};

qcom/parrot-qrd-pm8350b.dtsi

@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "parrot-pm8350b.dtsi"
+
+/ {
+	qcom,pmic-id-size = <9>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x32 0x0 0x0 0x0 0x0 0x0>;
+};
+
+&battery_charger {
+	qcom,thermal-mitigation-step = <500000>;
+};
+
+&usb0 {
+	usb-role-switch;
+	extcon = <&eud>;
+
+	dwc3@a600000 {
+		usb-role-switch;
+		dr_mode = "otg";
+	};
+
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};

qcom/parrot-qrd-wcn6750-4gb-overlay.dts

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-wcn6750.dtsi"
+#include "parrot-qrd-wcn6750-4gb.dtsi"
+#include "parrot-qrd-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN6750 QRD 4GB DDR";
+	compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
+	qcom,msm-id = <537 0x10000>;
+	qcom,board-id = <0x1000B 0x601>;
+};