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ARM: dts: msm: Add initial DCVS devices for Kera

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Add initial set of DCVS device nodes for Kera. This
includes the QCOM DCVS devices, PMU device memlat device
nodes and mapping tables, and bwmon device nodes.

Change-Id: I7fc58b1e3c841d60bca5b3231fd29578422ddebb
Signed-off-by: Sayantan Chakraborty <quic_saycha@quicinc.com>
This commit is contained in:
Sayantan Chakraborty
2024-10-14 12:16:23 +05:30
parent dba59babc0
commit 592e7887ba
1 changed files with 450 additions and 0 deletions
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450
qcom/kera.dtsi
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@@ -594,6 +594,13 @@
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
dcvs_fp: qcom,dcvs-fp {
compatible = "qcom,dcvs-fp";
qcom,ddr-bcm-name = "MC4";
qcom,llcc-bcm-name = "SH5";
};
};
};
@@ -2114,6 +2121,449 @@
status = "disabled";
};
llcc_pmu: llcc-pmu@24095000 {
compatible = "qcom,llcc-pmu-ver2";
reg = <0x24095000 0x300>;
reg-names = "lagg-base";
};
qcom_pmu: qcom,pmu {
compatible = "qcom,pmu";
qcom,long-counter;
qcom,pmu-events-tbl =
< 0x0008 0xFF 0x02 0xFF >,
< 0x0011 0xFF 0x01 0xFF >,
< 0x0017 0xFF 0xFF 0xFF >,
< 0x0037 0xFF 0xFF 0xFF >,
< 0x1000 0xFF 0xFF 0xFF >;
};
ddr_freq_table: ddr-freq-table {
ddr4 {
qcom,ddr-type = <7>;
qcom,freq-tbl =
< 547200 >,
< 681600 >,
< 768000 >,
< 1017600 >,
< 1353600 >,
< 1555200 >,
< 1708800 >,
< 2092800 >;
};
ddr5 {
qcom,ddr-type = <8>;
qcom,freq-tbl =
< 547200 >,
< 1353600 >,
< 1555200 >,
< 1708800 >,
< 2092800 >,
< 2736000 >,
< 3187200 >,
< 3686400 >,
< 4224000 >;
};
};
llcc_freq_table: llcc-freq-table {
qcom,freq-tbl =
< 19200 >,
< 350000 >,
< 533000 >,
< 695000 >,
< 875000 >,
< 933000 >,
< 1066000 >;
};
ddrqos_freq_table: ddrqos-freq-table {
qcom,freq-tbl =
< 0 >,
< 1 >;
};
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom_l3_dcvs_hw: l3 {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <2>;
qcom,bus-width = <32>;
reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
reg-names = "l3-base", "l3tbl-base";
l3_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
qcom,shared-offset = <0x0090>;
};
};
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <0>;
qcom,bus-width = <4>;
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
ddr_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <1>;
qcom,fp-voter = <&dcvs_fp>;
};
};
qcom_llcc_dcvs_hw: llcc {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <1>;
qcom,bus-width = <16>;
qcom,freq-tbl = <&llcc_freq_table>;
llcc_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&gem_noc MASTER_APPSS_PROC
&gem_noc SLAVE_LLCC>;
};
llcc_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <1>;
qcom,fp-voter = <&dcvs_fp>;
};
};
qcom_ddrqos_dcvs_hw: ddrqos {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <3>;
qcom,bus-width = <1>;
qcom,freq-tbl = <&ddrqos_freq_table>;
ddrqos_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
};
};
qcom_memlat: qcom,memlat {
compatible = "qcom,memlat";
ddr {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,sampling-path = <&ddr_dcvs_fp>;
qcom,miss-ev = <0x1000>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
qcom,sampling-enabled;
ddr4-tbl {
qcom,ddr-type = <7>;
qcom,cpufreq-memfreq-tbl =
< 1113600 547000 >,
< 1497600 768000 >,
< 1843200 1017000 >;
};
ddr5-tbl {
qcom,ddr-type = <8>;
qcom,cpufreq-memfreq-tbl =
< 1113600 547000 >,
< 1497600 768000 >,
< 1843200 1555000 >;
};
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6>;
qcom,sampling-enabled;
ddr4-tbl {
qcom,ddr-type = <7>;
qcom,cpufreq-memfreq-tbl =
< 940800 547000 >,
< 1190400 1017000 >,
< 2208000 1708000 >,
< 2400000 2092000 >;
};
ddr5-tbl {
qcom,ddr-type = <8>;
qcom,cpufreq-memfreq-tbl =
< 940800 547000 >,
< 1190400 768000 >,
< 1612800 1555000 >,
< 1824000 1708000 >,
< 2208000 2092000 >,
< 2400000 3196000 >;
};
};
prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,sampling-enabled;
ddr4-tbl {
qcom,ddr-type = <7>;
qcom,cpufreq-memfreq-tbl =
< 960000 547000 >,
< 1209600 1017000 >,
< 1459200 1555000 >,
< 1804800 1708000 >,
< 2304000 2092000 >;
};
ddr5-tbl {
qcom,ddr-type = <8>;
qcom,cpufreq-memfreq-tbl =
< 960000 547000 >,
< 1209600 768000 >,
< 1459200 1555000 >,
< 1651200 1708000 >,
< 1804800 2092000 >,
< 2304000 3196000 >;
};
};
gold-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,sampling-enabled;
qcom,compute-mon;
ddr4-tbl {
qcom,ddr-type = <7>;
qcom,cpufreq-memfreq-tbl =
< 940800 547000 >,
< 1190400 768000 >,
< 1612800 1017000 >,
< 2208000 1708000 >,
< 2400000 2092000 >;
};
ddr5-tbl {
qcom,ddr-type = <8>;
qcom,cpufreq-memfreq-tbl =
< 940800 547000 >,
< 1190400 768000 >,
< 1612800 1555000 >,
< 2208000 2092000 >,
< 2400000 3196000 >;
};
};
prime-latfloor {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,sampling-enabled;
ddr4-tbl {
qcom,ddr-type = <7>;
qcom,cpufreq-memfreq-tbl =
< 2284800 547000 >,
< 2592000 2092000 >;
};
ddr5-tbl {
qcom,ddr-type = <8>;
qcom,cpufreq-memfreq-tbl =
< 2284800 547000 >,
< 2592000 3196000 >;
};
};
};
llcc {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
qcom,sampling-path = <&llcc_dcvs_fp>;
qcom,miss-ev = <0x37>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 883200 350000 >,
< 1401600 533000 >,
< 2016000 600000 >;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 633600 350000 >,
< 1190400 533000 >,
< 1401600 600000 >,
< 1824000 806000 >,
< 2803200 933000 >,
< 2918400 1066000 >,
< 3014400 1211000 >;
};
gold-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,sampling-enabled;
qcom,compute-mon;
qcom,cpufreq-memfreq-tbl =
< 2073600 350000 >,
< 3014400 600000 >;
};
};
l3 {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_l3_dcvs_hw>;
qcom,sampling-path = <&l3_dcvs_sp>;
qcom,miss-ev = <0x17>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 441600 364800 >,
< 595200 556800 >,
< 787200 710400 >,
< 902400 806400 >,
< 1113600 998400 >,
< 1228800 1094400 >,
< 1344000 1209600 >,
< 1497600 1363200 >,
< 1708800 1497600 >,
< 1804800 1516800 >,
< 2054400 1804800 >;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 480000 364800 >,
< 940800 556800 >,
< 1190400 710400 >,
< 1286400 902400 >,
< 1497600 1209600 >,
< 1708800 1363200 >,
< 2073600 1497600 >,
< 2400000 1516800 >,
< 2707200 1804800 >;
};
prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 480000 364800 >,
< 633600 556800 >,
< 960000 806400 >,
< 1324800 998400 >,
< 1651200 1209600 >,
< 1766400 1363200 >,
< 2208000 1497600 >,
< 2496000 1516800 >,
< 2918400 1804800 >;
};
prime-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,sampling-enabled;
qcom,compute-mon;
qcom,cpufreq-memfreq-tbl =
< 1920000 364800 >,
< 2512200 1209600 >,
< 3206400 1804800 >;
};
};
ddrqos {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
qcom,sampling-path = <&ddrqos_dcvs_sp>;
qcom,miss-ev = <0x1000>;
ddrqos_gold_lat: gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 2300000 0 >,
< 2496000 1 >;
};
ddrqos_prime_lat: prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 1478400 0 >,
< 3206400 1 >;
};
ddrqos_prime_latfloor: prime-latfloor {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 2169600 0 >,
< 3206400 1 >;
};
};
};
qcom_llcc_l3_vote: qcom,llcc-l3-vote {
qcom,target-dev = <&qcom_l3_dcvs_hw>;
qcom,secondary-map =
< 350000 364800 >,
< 533000 518400 >,
< 600000 614400 >,
< 806000 806400 >,
< 933000 902400 >,
< 1066000 998400 >,
< 1211200 1209600 >;
};
bwmon_llcc: qcom,bwmon-llcc@240B7300 {
compatible = "qcom,bwmon4";
reg = <0x240B7400 0x300>, <0x240B7300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
qcom,second-vote = <&qcom_llcc_l3_vote>;
};
bwmon_ddr: qcom,bwmon-ddr@24091000 {
compatible = "qcom,bwmon5";
reg = <0x24091000 0x1000>;
reg-names = "base";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
};
};
#include "tuna-gdsc.dtsi"