Merge df5683bebe on remote branch

Change-Id: I73d0a913232225e34c9f2f91629bb6190b59035d

Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml

@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. X1E80100 TLMM block
+
+maintainers:
+  - Rajendra Nayak <quic_rjendra@quicinc.com>
+
+description:
+  Top Level Mode Multiplexer pin controller in Qualcomm X1E80100 SoC.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,x1e80100-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+  "#interrupt-cells": true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 119
+
+  gpio-line-names:
+    maxItems: 238
+
+  "#gpio-cells": true
+  gpio-ranges: true
+  wakeup-parent: true
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-x1e80100-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-x1e80100-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-x1e80100-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+    unevaluatedProperties: false
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+        minItems: 1
+        maxItems: 36
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+        enum: [ aon_cci, aoss_cti, atest_char, atest_char0,
+                atest_char1, atest_char2, atest_char3, atest_usb,
+                audio_ext, audio_ref, cam_aon, cam_mclk, cci_async,
+                cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
+                cci_timer4, cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3,
+                cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
+                ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6, ddr_pxi7,
+                edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, eusb0_ac, eusb1_ac,
+                eusb2_ac, eusb3_ac, eusb5_ac, eusb6_ac, gcc_gp1, gcc_gp2,
+                gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0,
+                i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, mdp_vsync0,
+                mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5,
+                mdp_vsync6, mdp_vsync7, mdp_vsync8, pcie3_clk, pcie4_clk,
+                pcie5_clk, pcie6a_clk, pcie6b_clk, phase_flag, pll_bist, pll_clk,
+                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
+                qdss_gpio, qspi00, qspi01, qspi02, qspi03, qspi0_clk, qspi0_cs0,
+                qspi0_cs1, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
+                qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
+                qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2,
+                qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, sd_write, sdc4_clk,
+                sdc4_cmd, sdc4_data0, sdc4_data1, sdc4_data2, sdc4_data3, sys_throttle,
+                tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5,
+                tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
+                tsense_pwm1, tsense_pwm2, sense_pwm3, tsense_pwm4, usb0_dp, usb0_phy,
+                usb0_sbrx, usb0_sbtx, usb1_dp, usb1_phy, usb1_sbrx, usb1_sbtx,
+                usb2_dp, usb2_phy, usb2_sbrx, usb2_sbtx, vsense_trigger ]
+
+    required:
+      - pins
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    tlmm: pinctrl@f100000 {
+        compatible = "qcom,x1e80100-tlmm";
+        reg = <0x0f100000 0xf00000>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&tlmm 0 0 239>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+        gpio-wo-state {
+            pins = "gpio1";
+            function = "gpio";
+        };
+
+        uart-w-state {
+            rx-pins {
+                pins = "gpio26";
+                function = "qup2_se7";
+                bias-pull-up;
+            };
+
+            tx-pins {
+                pins = "gpio27";
+                function = "qup2_se7";
+                bias-disable;
+            };
+        };
+    };
+...

bindings/arm/msm/msm.yaml

@@ -76,7 +76,7 @@ properties:
           - enum:
               - qcom,parrot-atp
               - qcom,atp
-              -  qcom,parrot-idp
+              - qcom,parrot-idp
               - qcom,idp
               - qcom,parrot-qrd
               - qcom,qrd
@@ -95,4 +95,57 @@ properties:
               - qcom,qrd
           - const: qcom,parrotp
 
+      - description: Qualcomm Technologies, Inc. RAVELIN
+        items:
+          - enum:
+              - qcom,ravelin-atp
+              - qcom,atp
+              - qcom,ravelin-idp
+              - qcom,idp
+              - qcom,ravelin-qrd
+              - qcom,qrd
+              - qcom,ravelin-rumi
+              - qcom,rumi
+          - const: qcom,ravelin
+
+      - description: Qualcomm Technologies, Inc. RAVELINP
+        items:
+          - enum:
+              - qcom,ravelinp-atp
+              - qcom,atp
+              - qcom,ravelinp-idp
+              - qcom,idp
+              - qcom,ravelinp-qrd
+              - qcom,qrd
+          - const: qcom,ravelinp
+
+      - description: Qualcomm Technologies, Inc. TUNA
+        items:
+          - enum:
+              - qcom,tuna-rumi
+              - qcom,rumi
+          - const: qcom,tuna
+
+      - description: Qualcomm Technologies, Inc. MONACO
+        items:
+          - enum:
+              - qcom,monaco-atp
+              - qcom,atp
+              - qcom,monaco-idp
+              - qcom,idp
+              - qcom,monaco-wdp
+              - qcom,wdp
+          - const: qcom,monaco
+
+      - description: Qualcomm Technologies, Inc. MONACOP
+        items:
+          - enum:
+              - qcom,monaco-atp
+              - qcom,atp
+              - qcom,monaco-idp
+              - qcom,idp
+              - qcom,monaco-wdp
+              - qcom,wdp
+          - const: qcom,monacop
+
 additionalProperties: true

bindings/arm/msm/msm_hang_detect.yaml

@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/msm/msm_hang_detect.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: QTI MSM Core Hang Detection
+
+maintainers:
+  - Elliot Berman <eberman@quicinc.com>
+
+description: |
+  Core Hang Detection provides the three sysfs entries for configuring
+  threshold, PMU event mux select and to enable hang detection.
+
+  If core is hung for threshold time (value X 10ns) and no
+  heart beat event from pmu to core hang monitor detection, core hang
+  interrupt would be generated to reset the SOC via secure watchdog
+  to collect all cores context.
+
+  PMU event mux select can be programmed to one of the supported
+  events, for example-
+  1) Load Instruction executed,
+  2) Store Instructions executed
+  3) Instruction architecturally executed and etc.
+
+  Writing 1 into enable sysfs entry, enables core hang detection and
+  if there is no selected PMU mux event for 10ns core hang counter
+  gets incremented. Once counter reaches the programmed threshold value,
+  core hang interrupts generated to reset the SOC.
+
+properties:
+  compatible:
+    const: qcom,core-hang-detect
+
+  label:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: unique name used to create sysfs entry
+
+  qcom,chd-percpu-info:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+      Set of <&CPUx_Phandle CPUx_Threshold CPUx_Config>, where
+      CPUx_Phandle is the physical CPU,
+      CPUx_Threshold is APCS_ALIAS*_CORE_HANG_THRESHOLD register address,
+      CPUx_Config is APCS_ALIAS*_CORE_HANG_CONFIG register address,
+      all corresponding to the physical CPU.
+    minItems: 1
+
+required:
+  - compatible
+  - label
+  - qcom,chd-percpu-info
+
+additionalProperties: false
+
+examples:
+  - |
+    //For kalama:
+    qcom,chd {
+      compatible = "qcom,core-hang-detect";
+      label = "core";
+      qcom,chd-percpu-info = <&CPU0 0x17800058 0x17800060>,
+                             <&CPU1 0x17810058 0x17810060>,
+                             <&CPU2 0x17820058 0x17820060>,
+                             <&CPU3 0x17830058 0x17830060>,
+                             <&CPU4 0x17840058 0x17840060>,
+                             <&CPU5 0x17850058 0x17850060>,
+                             <&CPU6 0x17860058 0x17860060>,
+                             <&CPU7 0x17870058 0x17870060>;
+    };

bindings/arm/msm/qcom,llcc.yaml

@@ -34,6 +34,7 @@ properties:
       - qcom,sm8550-llcc
       - qcom,pineapple-llcc
       - qcom,sun-llcc
+      - qcom,x1e80100-llcc
 
   reg:
     minItems: 2
@@ -65,6 +66,7 @@ allOf:
             enum:
               - qcom,pineapple-llcc
               - qcom,sun-llcc
+              - qcom,x1e80100-llcc
     then:
       properties:
         reg:

bindings/arm/msm/sys-pm-violators.yaml

@@ -19,6 +19,7 @@ properties:
   compatible:
     enum:
       - qcom,sys-pm-parrot
+      - qcom,sys-pm-ravelin
       - qcom,sys-pm-lahaina
       - qcom,sys-pm-waipio
       - qcom,sys-pm-kalama
@@ -49,6 +50,7 @@ allOf:
               - qcom,sys-pm-sun
               - qcom,sys-pm-pineapple
               - qcom,sys-pm-parrot
+              - qcom,sys-pm-ravelin
     then:
       properties:
         reg:

bindings/clock/qcom,camcc-parrot.yaml

@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,camcc-parrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller
+
+maintainers:
+  - Kalpak Kawadkar <quic_kkawadka@quicinc.com>
+
+description: |
+  Camera clock control module which supports the clocks, resets and
+  power domains on Parrot.
+
+  See also:
+  - dt-bindings/clock/qcom,camcc-parrot.h
+
+properties:
+  compatible:
+    const: qcom,parrot-camcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Camera AHB clock from GCC
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: iface
+
+  vdd_cx-supply:
+    description: Phandle pointer to the vdd_cx logic rail supply
+
+  vdd_mxa-supply:
+    description: Phandle pointer to the vdd_mxa logic rail supply
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+
+allOf:
+  - $ref: "qcom,gcc.yaml#"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    camcc: clock-controller@ade0000 {
+         compatible = "qcom,parrot-camcc", "syscon";
+         reg = <0xade0000 0x20000>;
+         reg-name = "cc_base";
+         vdd_cx-supply = <&VDD_CX_LEVEL>;
+         vdd_mxa-supply = <&VDD_MXA_LEVEL>;
+         clocks = <&rpmhcc RPMH_CXO_CLK>,
+                <&gcc GCC_CAMERA_AHB_CLK>;
+                clock-names = "bi_tcxo", "iface";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+       };
+...

bindings/clock/qcom,debugcc.yaml

@@ -18,6 +18,7 @@ properties:
     enum:
       - qcom,pineapple-debugcc
       - qcom,sun-debugcc
+      - qcom,parrot-debugcc
 
   clocks:
     items:

bindings/clock/qcom,dispcc-parrot.yaml

@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-parrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Display Clock & Reset Controller
+
+maintainers:
+  - Jagadeesh Kona <quic_jkona@quicinc.com>
+
+description: |
+  Qualcomm Technologies, Inc. display clock control module which supports the clocks and
+  power domains on Parrot.
+
+  See also:
+    dt-bindings/clock/qcom,dispcc-parrot.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,parrot-dispcc
+
+  clocks:
+    items:
+      - description: Brard XO source
+      - description: Brard XO_AO source
+      - description: Sleep clock source
+      - description: AHB config clock from GCC
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: bi_tcxo_ao
+      - const: sleep_clk
+      - const: iface
+
+  vdd_cx-supply:
+    description: Phandle pointer to the vdd_cx logic rail supply
+
+  vdd_mxa-supply:
+    description: Phandle pointer to the vdd_mxa logic rail supply
+
+  '#clock-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,gcc-parrot.h>
+    dispcc: clock-controller@af00000 {
+        compatible = "qcom,parrot-dispcc", "syscon";
+        reg = <0xaf00000 0x20000>;
+        reg-name = "cc_base";
+        vdd_cx-supply = <&VDD_CX_LEVEL>;
+        vdd_mxa-supply = <&VDD_MXA_LEVEL>;
+        clocks = <&rpmhcc RPMH_CXO_CLK>,
+            <&rpmhcc RPMH_CXO_CLK_A>,
+            <&sleep_clk>,
+            <&gcc GCC_DISP_AHB_CLK>;
+        clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+    };
+...

bindings/clock/qcom,gcc-parrot.yaml

@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-parrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Global Clock & Reset Controller
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Global clock control module which supports the clocks, resets and
+  power domains on Parrot.
+
+  See also:
+  - dt-bindings/clock/qcom,gcc-parrot.h
+
+properties:
+  compatible:
+    const: qcom,parrot-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Sleep clock source
+      - description: PCIE 0 Pipe clock source (Optional clock)
+      - description: UFS Phy Rx symbol 0 clock source (Optional clock)
+      - description: UFS Phy Rx symbol 1 clock source (Optional clock)
+      - description: UFS Phy Tx symbol 0 clock source (Optional clock)
+      - description: USB3 Phy wrapper pipe clock source (Optional clock)
+    minItems: 2
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: sleep_clk
+      - const: pcie_0_pipe_clk # Optional clock
+      - const: ufs_phy_rx_symbol_0_clk # Optional clock
+      - const: ufs_phy_rx_symbol_1_clk # Optional clock
+      - const: ufs_phy_tx_symbol_0_clk # Optional clock
+      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
+    minItems: 2
+
+  vdd_cx-supply:
+    description: Phandle pointer to the vdd_cx logic rail supply
+
+  vdd_mxa-supply:
+    description: Phandle pointer to the vdd_mxa logic rail supply
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+
+allOf:
+  - $ref: "qcom,gcc.yaml#"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+        gcc: clock-controller@100000 {
+                compatible = "qcom,parrot-gcc", "syscon";
+                reg = <0x100000 0x1f4200>;
+                reg-name = "cc_base";
+                vdd_cx-supply = <&VDD_CX_LEVEL>;
+                vdd_mxa-supply = <&VDD_MXA_LEVEL>;
+                clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
+                        <&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>,
+                        <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
+                        <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
+                clock-names = "bi_tcxo", "sleep_clk",
+                        "pcie_0_pipe_clk", "ufs_phy_rx_symbol_0_clk",
+                        "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
+                        "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+    };
+...

bindings/clock/qcom,gpucc.yaml

@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
+title: Qualcomm Technologies, Inc. Graphics Clock & Reset Controller
 
 maintainers:
   - Taniya Das <tdas@codeaurora.org>
@@ -23,6 +23,7 @@ description: |
     dt-bindings/clock/qcom,gpucc-sm8250.h
     dt-bindings/clock/qcom,gpucc-pineapple.h
     dt-bindings/clock/qcom,gpucc-sun.h
+    dt-bindings/clock/qcom,gpucc-parrot.h
 
 properties:
   compatible:
@@ -37,6 +38,7 @@ properties:
       - qcom,sm8250-gpucc
       - qcom,pineapple-gpucc
       - qcom,sun-gpucc
+      - qcom,parrot-gpucc
 
   clocks:
     items:

bindings/clock/qcom,gx_clkctl.yaml

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gx_clkctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. GPU GX_CLKCTL controller
+
+maintainers:
+  - Jagadeesh Kona <quic_jkona@quicinc.com>
+
+description: |
+  Graphics GX_CLKCTL clock controller binding which supports
+  GX_CLKCTL GDSC power domain.
+
+  See also:
+    dt-bindings/clock/qcom,gxclkctl-sun.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sun-gx_clkctl
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the GPU CX GDSC power domain.
+    maxItems: 1
+
+  vdd_gx-supply:
+    description: Phandle pointer to the parent logic rail supply
+
+  '#power-domain-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - vdd_gx-supply
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gxclkctl-sun.h>
+    gxclkctl: clock-controller@3d68024 {
+      compatible = "qcom,sun-gx_clkctl";
+      reg = <0x3d68024 0x8>;
+      reg-name = "cc_base";
+      power-domains = <&gpucc GPU_CC_CX_GDSC>;
+      vdd_gx-supply = <&VDD_GFX_GFX_MXC_VOTER_LEVEL>;
+      #power-domain-cells = <1>;
+    };
+...

bindings/clock/qcom,rpmhcc.yaml

@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/clock/qcom,rpmhcc.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Technologies, Inc. RPMh Clocks Bindings
+title: Qualcomm Technologies, Inc. RPMh Clocks
 
 maintainers:
   - Taniya Das <tdas@codeaurora.org>
@@ -32,6 +32,7 @@ properties:
       - qcom,sm8450-rpmh-clk
       - qcom,pineapple-rpmh-clk
       - qcom,sun-rpmh-clk
+      - qcom,parrot-rpmh-clk
 
   clocks:
     maxItems: 1

bindings/clock/qcom,videocc.yaml

@@ -21,6 +21,7 @@ description: |
     dt-bindings/clock/qcom,videocc-sm8250.h
     dt-bindings/clock/qcom,videocc-pineapple.h
     dt-bindings/clock/qcom,videocc-sun.h
+    dt-bindings/clock/qcom,videocc-parrot.h
 
 properties:
   compatible:
@@ -34,6 +35,7 @@ properties:
       - qcom,pineapple-videocc-v2
       - qcom,sun-videocc
       - qcom,sun-videocc-v2
+      - qcom,parrot-videocc
 
   clocks:
     items:

bindings/interconnect/qcom,rpmh.yaml

@@ -160,6 +160,18 @@ properties:
       - qcom,pineapple-lpass_ag_noc
       - qcom,pineapple-lpass_lpiaon_noc
       - qcom,pineapple-lpass_lpicx_noc
+      - qcom,parrot-aggre1_noc
+      - qcom,parrot-aggre2_noc
+      - qcom,parrot-clk_virt
+      - qcom,parrot-cnoc2
+      - qcom,parrot-cnoc3
+      - qcom,parrot-gem_noc
+      - qcom,parrot-lpass_ag_noc
+      - qcom,parrot-mc_virt
+      - qcom,parrot-mmss_noc
+      - qcom,parrot-nsp_noc
+      - qcom,parrot-pcie_anoc
+      - qcom,parrot-system_noc
 
   '#interconnect-cells': true
 

bindings/interrupt-controller/qcom,pdc.yaml

@@ -34,6 +34,8 @@ properties:
           - qcom,sm8250-pdc
           - qcom,sm8350-pdc
           - qcom,sun-pdc
+          - qcom,parrot-pdc
+          - qcom,ravelin-pdc
       - const: qcom,pdc
 
   reg:

bindings/mailbox/qcom,apcs-kpss-global.yaml

@@ -4,7 +4,7 @@
 $id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
-title: Qualcomm APCS global block bindings
+title: Qualcomm Technologies, Inc. APCS global block
 
 description:
   This binding describes the APCS "global" block found in various Qualcomm
@@ -31,6 +31,7 @@ properties:
               - qcom,sm6125-apcs-hmss-global
               - qcom,sm6115-apcs-hmss-global
               - qcom,sm8150-apss-shared
+              - qcom,monaco-apcs-hmss-global
       - items:
           - enum:
               - qcom,msm8916-apcs-kpss-global

bindings/nvmem/qcom,qfprom.yaml

@@ -29,6 +29,7 @@ properties:
           - qcom,sdm630-qfprom
           - qcom,sdm845-qfprom
           - qcom,sm6115-qfprom
+          - qcom,sun-qfprom
       - const: qcom,qfprom
 
   reg:

bindings/pinctrl/qcom,monaco-tlmm.yaml

@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,monaco-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Monaco TLMM block
+
+maintainers:
+  - Pradnya Dahiwale <quic_pdahiwal@quicinc.com>
+description: |
+  This binding describes the Top Level Mode Multiplexer (TLMM) block found
+  in the Monaco platform.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+properties:
+  compatible:
+    const: "qcom,monaco-pinctrl"
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 105
+
+  gpio-line-names:
+    maxItems: 112
+
+  '#gpio-cells': true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+# PIN CONFIGURATION NODES:
+patternProperties:
+  '-state$':
+    oneOf:
+      - $ref: "#/$defs/qcom-monaco-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-monaco-tlmm-state"
+        additionalProperties: false
+$defs:
+  qcom-monaco-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in
+          this subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+        minItems: 1
+        maxItems: 36
+      function:
+        description:
+          Specify the alternative function to be configured for the
+          specified pins. Functions are only valid for gpio pins.
+        enum: [ AGERA_PLL, CCI_TIMER0, CCI_TIMER1, CCI_TIMER2, CCI_TIMER3,
+                CRI_TRNG, CRI_TRNG0, CRI_TRNG1, GCC_GP1, GCC_GP2, GCC_GP3,
+		GP_PDM0, GP_PDM1, GP_PDM2, JITTER_BIST, PA_INDICATOR, PLL_BIST,
+                QUP0_L0, QUP0_L1, QUP0_L2, QUP0_L3, SDC1_TB, SDC2_TB,
+                SSBI_WTR1, adsp_ext, atest_bbrx0, atest_bbrx1, atest_char,
+                atest_char0, atest_char1, atest_char2, atest_char3,
+                atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native,
+                atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
+                atest_usb11, atest_usb12, atest_usb13, atest_usb2,
+                atest_usb20, atest_usb21, atest_usb22, atest_usb23,
+                cam_mclk, cci_async, cci_i2c, dac_calib0, dac_calib1,
+                dac_calib10, dac_calib11, dac_calib12, dac_calib13,
+                dac_calib14, dac_calib15, dac_calib16, dac_calib17,
+                dac_calib18, dac_calib19, dac_calib2, dac_calib20,
+                dac_calib21, dac_calib22, dac_calib23, dac_calib24,
+                dac_calib25, dac_calib3, dac_calib4, dac_calib5,
+                dac_calib6, dac_calib7, dac_calib8, dac_calib9,
+                dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2,
+                ddr_pxi3, gsm0_tx, gsm1_tx, m_voc, mdp_vsync, mpm_pwr,
+                nav_gpio0, nav_gpio1, nav_gpio2, pbs0, pbs1, pbs10,
+                pbs11, pbs12, pbs13, pbs14, pbs15, pbs2, pbs3, pbs4,
+                pbs5, pbs6, pbs7, pbs8, pbs9, pbs_out, phase_flag0,
+                phase_flag1, phase_flag10, phase_flag11, phase_flag12,
+                phase_flag13, phase_flag14, phase_flag15, phase_flag16,
+                phase_flag17, phase_flag18, phase_flag19, phase_flag2,
+                phase_flag20, phase_flag21, phase_flag22, phase_flag23,
+                phase_flag24, phase_flag25, phase_flag26, phase_flag27,
+                phase_flag28, phase_flag29, phase_flag3, phase_flag30,
+                phase_flag31, phase_flag4, phase_flag5, phase_flag6,
+                phase_flag7, phase_flag8, phase_flag9, pll_bypassnl,
+                pll_clk, pll_reset, prng_rosc0, prng_rosc1, prng_rosc2,
+                prng_rosc3, pwm_0, pwm_1, pwm_2, pwm_3, pwm_4, pwm_5,
+                pwm_6, pwm_7, pwm_8, pwm_9, qdss_cti, qdss_gpio,
+                qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
+                qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
+                qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,
+                qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
+                qup00, qup01, qup02, qup03, qup04, qup05, qup06,
+                sdc3_clk, sdc3_cmd, sdc3_data, tgu_ch0, tgu_ch1
+                tgu_ch2, tgu_ch3, tsense_pwm, uim0_clk, uim0_data,
+                uim0_present, uim0_reset, usb2phy_ac, vfr_1,
+                vsense_trigger, wci_uart, wlan1_adc0, wlan1_adc1]
+
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    allOf:
+      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+      - if:
+          properties:
+            pins:
+              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
+        then:
+          required:
+            - function
+
+    additionalProperties: false
+
+examples:
+  - |
+    tlmm: pinctrl@500000 {
+      compatible = "qcom,monaco-pinctrl";
+      reg = <0x500000 0x300000>;
+      interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+    };
+

bindings/pinctrl/qcom,parrot-tlmm.yaml

@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,parrot-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. PARROT TLMM block
+
+maintainers:
+  - Naina Mehta <quic_nainmeht@quicinc.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block found in the
+  PARROT platform.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+      const: "qcom,parrot-tlmm"
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 105
+
+  gpio-line-names:
+    maxItems: 140
+
+  '#gpio-cells': true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+# PIN CONFIGURATION NODES:
+patternProperties:
+  '-state$':
+    oneOf:
+      - $ref: "#/$defs/qcom-parrot-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-parrot-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-parrot-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+
+    properties:
+      pins:
+        description:
+           List of gpio pins affected by the properties specified in
+           this subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+          minItems: 1
+          maxItems: 36
+      function:
+        description:
+           Specify the alternative function to be configured for the
+           specified pins. Functions are only valid for gpio pins.
+        enum: [atest_char_start, atest_char_status0, atest_char_status1,
+               atest_char_status2, atest_char_status3, atest_usb0_atereset,
+               atest_usb0_testdataout00, atest_usb0_testdataout01, atest_usb0_testdataout02,
+               atest_usb0_testdataout03, audio_ref_clk, cam_mclk, cci_async_in0,
+               cci_i2c_scl0, cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_sda0,
+               cci_i2c_sda1, cci_i2c_sda2, cci_i2c_sda3, cci_timer0, cci_timer1,
+               cci_timer2, cci_timer3, cmu_rng_entropy0, cmu_rng_entropy1, cmu_rng_entropy2,
+               cmu_rng_entropy3, coex_uart1_rx, coex_uart1_tx, cri_trng_rosc, cri_trng_rosc0,
+               cri_trng_rosc1, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, ddr_bist_start,
+               ddr_bist_stop, ddr_pxi0_test, ddr_pxi1_test, dp0_hot_plug, gcc_gp1_clk,
+               gcc_gp2_clk, gcc_gp3_clk, gpio, host2wlan_sol_mira, host2wlan_sol_mirb,
+               i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c_qup0, ibi_i3c_qup1,
+               jitter_bist_ref, mdp_vsync_e, mdp_vsync_p, mdp_vsync_s, mdp_vsync0_out,
+               mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, nav_gpio0, nav_gpio1,
+               nav_gpio2, PCIE0_CLK_REQ, phase_flag_status0, phase_flag_status1,
+               phase_flag_status10, phase_flag_status11, phase_flag_status12,
+               phase_flag_status13, phase_flag_status14, phase_flag_status15,
+               phase_flag_status16, phase_flag_status17, phase_flag_status18,
+               phase_flag_status19, phase_flag_status2, phase_flag_status20,
+               phase_flag_status21, phase_flag_status22, phase_flag_status23,
+               phase_flag_status24, phase_flag_status25, phase_flag_status26,
+               phase_flag_status27, phase_flag_status28, phase_flag_status29,
+               phase_flag_status3, phase_flag_status30, phase_flag_status31,
+               phase_flag_status4, phase_flag_status5, phase_flag_status6,
+               phase_flag_status7, phase_flag_status8, phase_flag_status9,
+               pll_bist_sync, pll_clk_aux, prng_rosc_test0, prng_rosc_test1,
+               prng_rosc_test2, prng_rosc_test3, qdss_cti_trig0, qdss_cti_trig1,
+               qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata0,
+               qdss_gpio_tracedata1, qdss_gpio_tracedata10, qdss_gpio_tracedata11,
+               qdss_gpio_tracedata12, qdss_gpio_tracedata13, qdss_gpio_tracedata14,
+               qdss_gpio_tracedata15, qdss_gpio_tracedata2, qdss_gpio_tracedata3,
+               qdss_gpio_tracedata4, qdss_gpio_tracedata5, qdss_gpio_tracedata6,
+               qdss_gpio_tracedata7, qdss_gpio_tracedata8, qdss_gpio_tracedata9,
+               qlink0_enable, qlink0_request, qlink0_wmss_reset, qlink1_enable,
+               qlink1_request, qlink1_wmss_reset, QSPI_CLK, QSPI_CS_N, QSPI0,
+               QSPI1, QSPI2, QSPI3, qup0_se0_l0, qup0_se0_l1, qup0_se0_l2,qup0_se0_l3,
+               qup0_se1_l0, qup0_se1_l1, qup0_se1_l2, qup0_se1_l3,qup0_se1_l4, qup0_se2_l0,
+               qup0_se2_l1, qup0_se2_l2, qup0_se2_l3, qup0_se3_l0, qup0_se3_l1, qup0_se3_l2,
+               qup0_se3_l3, qup0_se4_l0,  qup0_se4_l1, qup0_se4_l2, qup0_se4_l3, qup0_se5_l0,
+               qup0_se5_l1, qup0_se5_l2, qup0_se5_l3, qup0_se5_l4, qup0_se5_l5, qup0_se5_l6,
+               qup1_se0_l0, qup1_se0_l1, qup1_se0_l2, qup1_se0_l3, qup1_se1_l0, qup1_se1_l1,
+               qup1_se1_l2, qup1_se1_l3, qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3,
+               qup1_se2_l4, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2, qup1_se3_l3, qup1_se5_l0,
+               qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, sd_write_protect, tb_trig_sdc1,
+               tb_trig_sdc2, tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
+               tgu_ch3_trigout, tmess_prng_rosc0, tmess_prng_rosc1, tmess_prng_rosc2,
+               tmess_prng_rosc3, tsense_pwm1_out, tsense_pwm2_out, uim0_clk, uim0_data,
+               uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
+               usb0_hs_ac, usb0_phy_ps, vfr_0_mira, vfr_0_mirb, vfr_1,vsense_trigger_mirnat,
+               wlan1_adc_dtest0, wlan1_adc_dtest1, wlan2_adc_dtest0, wlan2_adc_dtest1]
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    allOf:
+      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+      - if:
+          properties:
+            pins:
+              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
+        then:
+          required:
+            - function
+
+    additionalProperties: false
+
+examples:
+  - |
+    tlmm: pinctrl@f000000 {
+      compatible = "qcom,parrot-tlmm";
+      reg = <0x0F000000 0x1000000>;
+      interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+    };
+

bindings/pinctrl/qcom,parrot-vm-tlmm.yaml

@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,parrot-vm-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. PARROT VM TLMM block
+
+maintainers:
+  - Naina Mehta <quic_nainmeht@quicinc.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block for VM.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,parrot-vm-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 105
+
+  gpio-line-names:
+    maxItems: 140
+
+  '#gpio-cells': true
+  gpios: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+# PIN CONFIGURATION NODES:
+patternProperties:
+  '-state$':
+    oneOf:
+      - $ref: "#/$defs/qcom-parrot-vm-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-parrot-vm-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-parrot-vm-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in
+            this subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+          minItems: 1
+          maxItems: 36
+      function:
+        description:
+          Specify the alternative function to be configured for the
+          specified pins. Functions are only valid for gpio pins.
+        enum: [atest_char_start, atest_char_status0, atest_char_status1,
+               atest_char_status2, atest_char_status3, atest_usb0_atereset,
+               atest_usb0_testdataout00, atest_usb0_testdataout01, atest_usb0_testdataout02,
+               atest_usb0_testdataout03, audio_ref_clk, cam_mclk, cci_async_in0,
+               cci_i2c_scl0, cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_sda0,
+               cci_i2c_sda1, cci_i2c_sda2, cci_i2c_sda3, cci_timer0, cci_timer1,
+               cci_timer2, cci_timer3, cmu_rng_entropy0, cmu_rng_entropy1, cmu_rng_entropy2,
+               cmu_rng_entropy3, coex_uart1_rx, coex_uart1_tx, cri_trng_rosc, cri_trng_rosc0,
+               cri_trng_rosc1, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, ddr_bist_start,
+               ddr_bist_stop, ddr_pxi0_test, ddr_pxi1_test, dp0_hot_plug, gcc_gp1_clk,
+               gcc_gp2_clk, gcc_gp3_clk, gpio, host2wlan_sol_mira, host2wlan_sol_mirb,
+               i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c_qup0, ibi_i3c_qup1,
+               jitter_bist_ref, mdp_vsync_e, mdp_vsync_p, mdp_vsync_s, mdp_vsync0_out,
+               mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, nav_gpio0, nav_gpio1,
+               nav_gpio2, PCIE0_CLK_REQ, phase_flag_status0, phase_flag_status1,
+               phase_flag_status10, phase_flag_status11, phase_flag_status12,
+               phase_flag_status13, phase_flag_status14, phase_flag_status15,
+               phase_flag_status16, phase_flag_status17, phase_flag_status18,
+               phase_flag_status19, phase_flag_status2, phase_flag_status20,
+               phase_flag_status21, phase_flag_status22, phase_flag_status23,
+               phase_flag_status24, phase_flag_status25, phase_flag_status26,
+               phase_flag_status27, phase_flag_status28, phase_flag_status29,
+               phase_flag_status3, phase_flag_status30, phase_flag_status31,
+               phase_flag_status4, phase_flag_status5, phase_flag_status6,
+               phase_flag_status7, phase_flag_status8, phase_flag_status9,
+               pll_bist_sync, pll_clk_aux, prng_rosc_test0, prng_rosc_test1,
+               prng_rosc_test2, prng_rosc_test3, qdss_cti_trig0, qdss_cti_trig1,
+               qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata0,
+               qdss_gpio_tracedata1, qdss_gpio_tracedata10, qdss_gpio_tracedata11,
+               qdss_gpio_tracedata12, qdss_gpio_tracedata13, qdss_gpio_tracedata14,
+               qdss_gpio_tracedata15, qdss_gpio_tracedata2, qdss_gpio_tracedata3,
+               qdss_gpio_tracedata4, qdss_gpio_tracedata5, qdss_gpio_tracedata6,
+               qdss_gpio_tracedata7, qdss_gpio_tracedata8, qdss_gpio_tracedata9,
+               qlink0_enable, qlink0_request, qlink0_wmss_reset, qlink1_enable,
+               qlink1_request, qlink1_wmss_reset, QSPI_CLK, QSPI_CS_N, QSPI0,
+               QSPI1, QSPI2, QSPI3, qup0_se0_l0, qup0_se0_l1, qup0_se0_l2,qup0_se0_l3,
+               qup0_se1_l0, qup0_se1_l1, qup0_se1_l2, qup0_se1_l3,qup0_se1_l4, qup0_se2_l0,
+               qup0_se2_l1, qup0_se2_l2, qup0_se2_l3, qup0_se3_l0, qup0_se3_l1, qup0_se3_l2,
+               qup0_se3_l3, qup0_se4_l0,  qup0_se4_l1, qup0_se4_l2, qup0_se4_l3, qup0_se5_l0,
+               qup0_se5_l1, qup0_se5_l2, qup0_se5_l3, qup0_se5_l4, qup0_se5_l5, qup0_se5_l6,
+               qup1_se0_l0, qup1_se0_l1, qup1_se0_l2, qup1_se0_l3, qup1_se1_l0, qup1_se1_l1,
+               qup1_se1_l2, qup1_se1_l3, qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3,
+               qup1_se2_l4, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2, qup1_se3_l3, qup1_se5_l0,
+               qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, sd_write_protect, tb_trig_sdc1,
+               tb_trig_sdc2, tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
+               tgu_ch3_trigout, tmess_prng_rosc0, tmess_prng_rosc1, tmess_prng_rosc2,
+               tmess_prng_rosc3, tsense_pwm1_out, tsense_pwm2_out, uim0_clk, uim0_data,
+               uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
+               usb0_hs_ac, usb0_phy_ps, vfr_0_mira, vfr_0_mirb, vfr_1,vsense_trigger_mirnat,
+               wlan1_adc_dtest0, wlan1_adc_dtest1, wlan2_adc_dtest0, wlan2_adc_dtest1]
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    allOf:
+      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+      - if:
+          properties:
+            pins:
+              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
+        then:
+          required:
+            - function
+
+    additionalProperties: false
+
+examples:
+  - |
+    tlmm: pinctrl@03000000 {
+      compatible = "qcom,parrot-vm-tlmm";
+      reg = <0x03000000 0xdc2000>;
+      interrupts-extended = <0 208 0>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      gpios = /bits/ 16 <0 1>;
+    };

bindings/pinctrl/qcom,ravelin-tlmm.yaml

@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ravelin-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. RAVELIN TLMM block
+
+maintainers:
+  - Yue Liu <quic_yueliu@quicinc.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block found in the
+  RAVELIN platform.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+      const: "qcom,ravelin-tlmm"
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 105
+
+  gpio-line-names:
+    maxItems: 135
+
+  '#gpio-cells': true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+# PIN CONFIGURATION NODES:
+patternProperties:
+  '-state$':
+    oneOf:
+      - $ref: "#/$defs/qcom-ravelin-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-ravelin-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-ravelin-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+
+    properties:
+      pins:
+        description:
+           List of gpio pins affected by the properties specified in
+           this subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+          minItems: 1
+          maxItems: 36
+      function:
+        description:
+           Specify the alternative function to be configured for the
+           specified pins. Functions are only valid for gpio pins.
+        enum: [ atest_char_start, atest_char_status0, atest_char_status1,
+                atest_char_status2, atest_char_status3, atest_usb0_atereset,
+                atest_usb0_testdataout00, atest_usb0_testdataout01,
+                atest_usb0_testdataout02, atest_usb0_testdataout03,
+                audio_ref_clk, cam_mclk, cci_async_in0, cci_i2c_scl0,
+                cci_i2c_scl1, cci_i2c_scl2, cci_i2c_sda0, cci_i2c_sda1,
+                cci_i2c_sda2, cci_timer0, cci_timer1, cci_timer2,
+                cci_timer3, cmu_rng_entropy0, cmu_rng_entropy1,
+                cmu_rng_entropy2, cmu_rng_entropy3, coex_uart1_rx,
+                coex_uart1_tx, cri_trng_rosc, cri_trng_rosc0, cri_trng_rosc1,
+                dbg_out_clk, ddr_bist_complete, ddr_bist_fail, ddr_bist_start,
+                ddr_bist_stop, ddr_pxi0_test, ddr_pxi1_test, gcc_gp1_clk,
+                gcc_gp2_clk, gcc_gp3_clk, gpio, host2wlan_sol, ibi_i3c_qup0,
+                ibi_i3c_qup1, jitter_bist_ref, mdp_vsync_e, mdp_vsync_p,
+                mdp_vsync_s, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,
+                mdp_vsync3_out, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk_req,
+                phase_flag_status0, phase_flag_status1, phase_flag_status10,
+                phase_flag_status11, phase_flag_status12, phase_flag_status13,
+                phase_flag_status14, phase_flag_status15, phase_flag_status16,
+                phase_flag_status17, phase_flag_status18, phase_flag_status19,
+                phase_flag_status2, phase_flag_status20, phase_flag_status21,
+                phase_flag_status22, phase_flag_status23, phase_flag_status24,
+                phase_flag_status25, phase_flag_status26, phase_flag_status27,
+                phase_flag_status28, phase_flag_status29, phase_flag_status3,
+                phase_flag_status30, phase_flag_status31, phase_flag_status4,
+                phase_flag_status5, phase_flag_status6, phase_flag_status7,
+                phase_flag_status8, phase_flag_status9, pll_bist_sync,
+                pll_clk_aux, prng_rosc_test0, prng_rosc_test1, prng_rosc_test2,
+                prng_rosc_test3, qdss_cti_trig0, qdss_cti_trig1,
+                qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata0,
+                qdss_gpio_tracedata1, qdss_gpio_tracedata10, qdss_gpio_tracedata11,
+                qdss_gpio_tracedata12, qdss_gpio_tracedata13, qdss_gpio_tracedata14,
+                qdss_gpio_tracedata15, qdss_gpio_tracedata2, qdss_gpio_tracedata3,
+                qdss_gpio_tracedata4, qdss_gpio_tracedata5, qdss_gpio_tracedata6,
+                qdss_gpio_tracedata7, qdss_gpio_tracedata8, qdss_gpio_tracedata9,
+                qlink0_enable, qlink0_request, qlink0_wmss_reset, qup0_se0_l0,
+                qup0_se0_l1, qup0_se0_l2, qup0_se0_l3, qup0_se1_l0, qup0_se1_l1,
+                qup0_se1_l2, qup0_se1_l3, qup0_se2_l0, qup0_se2_l1, qup0_se2_l2,
+                qup0_se2_l3, qup0_se3_l0, qup0_se3_l1, qup0_se3_l2, qup0_se3_l3,
+                qup0_se4_l0, qup0_se4_l1, qup0_se4_l2, qup0_se4_l3, qup0_se4_l4,
+                qup1_se0_l0, qup1_se0_l1, qup1_se0_l2, qup1_se0_l3, qup1_se1_l0,
+                qup1_se1_l1, qup1_se1_l2, qup1_se1_l3, qup1_se2_l0, qup1_se2_l1,
+                qup1_se2_l2, qup1_se2_l3, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2,
+                qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3,
+                qup1_se4_l4, sd_write_protect, tb_trig_sdc1, tb_trig_sdc2,
+                tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
+                tgu_ch3_trigout, tmess_prng_rosc0, tmess_prng_rosc1,
+                tmess_prng_rosc2, tmess_prng_rosc3, tsense_pwm1_out,
+                tsense_pwm2_out, uim0_clk, uim0_data, uim0_present, uim0_reset,
+                uim1_clk, uim1_data, uim1_present, uim1_reset, usb0_hs_ac,
+                usb0_phy_ps, vfr_0_mira, vfr_0_mirb, vfr_1,
+                vsense_trigger_mirnat, wlan1_adc_dtest0, wlan1_adc_dtest1]
+
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    allOf:
+      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+      - if:
+          properties:
+            pins:
+              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
+        then:
+          required:
+            - function
+
+    additionalProperties: false
+
+examples:
+  - |
+    tlmm: pinctrl@f000000 {
+      compatible = "qcom,ravelin-tlmm";
+      reg = <0x0F000000 0x1000000>;
+      interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+    };
+

bindings/pinctrl/qcom,ravelin-vm-tlmm.yaml

@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ravelin-vm-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. RAVELIN VM TLMM block
+
+maintainers:
+  - Tengfei Fan <quic_tengfan@quicinc.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block for VM.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,ravelin-vm-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended: true
+  interrupt-controller: true
+  '#interrupt-cells': true
+  gpio-controller: true
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 105
+
+  gpio-line-names:
+    maxItems: 140
+
+  '#gpio-cells': true
+  gpios: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+# PIN CONFIGURATION NODES:
+patternProperties:
+  '-state$':
+    oneOf:
+      - $ref: "#/$defs/qcom-ravelin-vm-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-ravelin-vm-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-ravelin-vm-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in
+            this subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
+            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+          minItems: 1
+          maxItems: 36
+      function:
+        description:
+          Specify the alternative function to be configured for the
+          specified pins. Functions are only valid for gpio pins.
+        enum: [ atest_char_start, atest_char_status0, atest_char_status1,
+                atest_char_status2, atest_char_status3, atest_usb0_atereset,
+                atest_usb0_testdataout00, atest_usb0_testdataout01,
+                atest_usb0_testdataout02, atest_usb0_testdataout03,
+                audio_ref_clk, cam_mclk, cci_async_in0, cci_i2c_scl0,
+                cci_i2c_scl1, cci_i2c_scl2, cci_i2c_sda0, cci_i2c_sda1,
+                cci_i2c_sda2, cci_timer0, cci_timer1, cci_timer2,
+                cci_timer3, cmu_rng_entropy0, cmu_rng_entropy1,
+                cmu_rng_entropy2, cmu_rng_entropy3, coex_uart1_rx,
+                coex_uart1_tx, cri_trng_rosc, cri_trng_rosc0, cri_trng_rosc1,
+                dbg_out_clk, ddr_bist_complete, ddr_bist_fail, ddr_bist_start,
+                ddr_bist_stop, ddr_pxi0_test, ddr_pxi1_test, gcc_gp1_clk,
+                gcc_gp2_clk, gcc_gp3_clk, gpio, host2wlan_sol, ibi_i3c_qup0,
+                ibi_i3c_qup1, jitter_bist_ref, mdp_vsync_e, mdp_vsync_p,
+                mdp_vsync_s, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,
+                mdp_vsync3_out, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk_req,
+                phase_flag_status0, phase_flag_status1, phase_flag_status10,
+                phase_flag_status11, phase_flag_status12, phase_flag_status13,
+                phase_flag_status14, phase_flag_status15, phase_flag_status16,
+                phase_flag_status17, phase_flag_status18, phase_flag_status19,
+                phase_flag_status2, phase_flag_status20, phase_flag_status21,
+                phase_flag_status22, phase_flag_status23, phase_flag_status24,
+                phase_flag_status25, phase_flag_status26, phase_flag_status27,
+                phase_flag_status28, phase_flag_status29, phase_flag_status3,
+                phase_flag_status30, phase_flag_status31, phase_flag_status4,
+                phase_flag_status5, phase_flag_status6, phase_flag_status7,
+                phase_flag_status8, phase_flag_status9, pll_bist_sync,
+                pll_clk_aux, prng_rosc_test0, prng_rosc_test1, prng_rosc_test2,
+                prng_rosc_test3, qdss_cti_trig0, qdss_cti_trig1,
+                qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata0,
+                qdss_gpio_tracedata1, qdss_gpio_tracedata10, qdss_gpio_tracedata11,
+                qdss_gpio_tracedata12, qdss_gpio_tracedata13, qdss_gpio_tracedata14,
+                qdss_gpio_tracedata15, qdss_gpio_tracedata2, qdss_gpio_tracedata3,
+                qdss_gpio_tracedata4, qdss_gpio_tracedata5, qdss_gpio_tracedata6,
+                qdss_gpio_tracedata7, qdss_gpio_tracedata8, qdss_gpio_tracedata9,
+                qlink0_enable, qlink0_request, qlink0_wmss_reset, qup0_se0_l0,
+                qup0_se0_l1, qup0_se0_l2, qup0_se0_l3, qup0_se1_l0, qup0_se1_l1,
+                qup0_se1_l2, qup0_se1_l3, qup0_se2_l0, qup0_se2_l1, qup0_se2_l2,
+                qup0_se2_l3, qup0_se3_l0, qup0_se3_l1, qup0_se3_l2, qup0_se3_l3,
+                qup0_se4_l0, qup0_se4_l1, qup0_se4_l2, qup0_se4_l3, qup0_se4_l4,
+                qup1_se0_l0, qup1_se0_l1, qup1_se0_l2, qup1_se0_l3, qup1_se1_l0,
+                qup1_se1_l1, qup1_se1_l2, qup1_se1_l3, qup1_se2_l0, qup1_se2_l1,
+                qup1_se2_l2, qup1_se2_l3, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2,
+                qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3,
+                qup1_se4_l4, sd_write_protect, tb_trig_sdc1, tb_trig_sdc2,
+                tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
+                tgu_ch3_trigout, tmess_prng_rosc0, tmess_prng_rosc1,
+                tmess_prng_rosc2, tmess_prng_rosc3, tsense_pwm1_out,
+                tsense_pwm2_out, uim0_clk, uim0_data, uim0_present, uim0_reset,
+                uim1_clk, uim1_data, uim1_present, uim1_reset, usb0_hs_ac,
+                usb0_phy_ps, vfr_0_mira, vfr_0_mirb, vfr_1,
+                vsense_trigger_mirnat, wlan1_adc_dtest0, wlan1_adc_dtest1]
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    allOf:
+      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+      - if:
+          properties:
+            pins:
+              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
+        then:
+          required:
+            - function
+
+    additionalProperties: false
+
+examples:
+  - |
+    tlmm: pinctrl@03000000 {
+      compatible = "qcom,ravelin-vm-tlmm";
+      reg = <0x03000000 0xdc2000>;
+      interrupts-extended = <0 208 0>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      gpios = /bits/ 16 <0 1>;
+    };

bindings/pinctrl/qcom,tlmm-vm-mem-access.yaml

@@ -1,12 +1,14 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
---
+---
 $id: http://devicetree.org/schemas/pinctrl/qcom,tlmm-vm-mem-access.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Technologies, Inc. TLMM VM memory access driver binding
+title: Qualcomm Technologies, Inc. TLMM VM memory access driver
 
 maintainers:
+   - Murali Nalajala <quic_mnalajal@quicinc.com>
+   - Cong Zhang <quic_congzhan@quicinc.com>
 
 description: |+
    The driver facilitates initial memory access to TLMM VM driver.
@@ -17,15 +19,36 @@ properties:
 
   qcom,master:
     description: Specify if this device is on the primary virtual machine.
+    type: boolean
 
-  tlmm-vm-gpio-list:
-    description: List of shared gpios.
+patternProperties:
+  "^.*$":
+    type: object
+    description: child node representing a VM instance
 
-example:
+    properties:
+      tlmm-vm-gpio-list:
+        description: List of shared gpios.
+
+      qcom,vmid:
+        description: VMID for the VM instance
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      qcom,label:
+        description: Unique label for the VM instance
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+additionalProperties: false
+
+examples:
   - |
     tlmm-vm-mem-access {
-	compatible = "qcom,tlmm-vm-mem-access";
-	qcom,master;
-	tlmm-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0>;
+        compatible = "qcom,tlmm-vm-mem-access";
+        qcom,master;
+        tuivm {
+            qcom,label = <0x01>;
+            qcom,vmid = <45>;
+            tlmm-vm-gpio-list = <&tlmm 1 0 &tlmm 2 0>;
+        };
     };
 ...

bindings/qdsp/msm-cdsp-loader.yaml

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/qdsp/msm-cdsp-loader.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Technologies, Inc. CDSP Loader Driver
+
+description:
+  The MSM CDSP Loader driver implements a mechanism to load the Compute
+  CDSP firmware images.
+
+maintainers:
+  - Anirudh Raghavendra <quic_araghave@quicinc.com>
+
+additionalProperties: false
+
+properties:
+    compatible :
+      items:
+        - const: qcom,msm-cdsp-loader
+        - const: qcom,proc-img-to-load
+required:
+  - compatible
+examples:
+  - |
+    qcom,msm-cdsp-loader {
+        compatible = "qcom,cdsp-loader";
+        qcom,proc-img-to-load = "cdsp";
+    };

bindings/remoteproc/qcom,adsp.yaml

@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/remoteproc/qcom,adsp.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm ADSP Peripheral Image Loader binding
+title: Qualcomm Technologies, Inc. ADSP Peripheral Image Loader
 
 maintainers:
   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
@@ -62,6 +62,15 @@ properties:
       - qcom,sun-cdsp-pas
       - qcom,sun-modem-pas
       - qcom,sun-soccp-pas
+      - qcom,parrot-adsp-pas
+      - qcom,parrot-cdsp-pas
+      - qcom,parrot-modem-pas
+      - qcom,parrot-wpss-pas
+      - qcom,ravelin-adsp-pas
+      - qcom,ravelin-modem-pas
+      - qcom,ravelin-wpss-pas
+      - qcom,monaco-modem-pas
+      - qcom,monaco-adsp-pas
 
   reg:
     maxItems: 1

bindings/soc/qcom/cpuss-sleep-stats.yaml

@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/qcom/cpuss-sleep-stats.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Technologies, Inc. cpuss sleep stats
+
+maintainers:
+  - Maulik Shah <quic_mkshah@quicinc.com>
+  - Minghao Zhang <quic_minghao@quicinc.com>
+
+description:
+  The low power mode counts and residency in the low power mode is maintained in
+  the hardware. The cpu sleep stats allows to read this configuration and display
+  the same.
+  This driver creates debugfs entry for all enabled lpm and provide LPM count and
+  residency.
+
+properties:
+  compatible:
+    enum:
+      - qcom,cpuss-sleep-stats
+      - qcom,cpuss-sleep-stats-v4
+
+  reg:
+    maxItems: 10
+    description: cpuss sleep stats RAM base register region.
+
+  reg-names:
+    items:
+      - const: seq_lpm_cntr_cfg_cpu0
+      - const: seq_lpm_cntr_cfg_cpu1
+      - const: seq_lpm_cntr_cfg_cpu2
+      - const: seq_lpm_cntr_cfg_cpu3
+      - const: seq_lpm_cntr_cfg_cpu4
+      - const: seq_lpm_cntr_cfg_cpu5
+      - const: seq_lpm_cntr_cfg_cpu6
+      - const: seq_lpm_cntr_cfg_cpu7
+      - const: l3_seq_lpm_cntr_cfg
+      - const: apss_seq_mem_base
+      - const: base
+
+  num-cpus:
+   const: 8
+   description: provides information about the number of CPUs in the system.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - qcom,cpuss-sleep-stats
+then:
+  required:
+    - num-cpus
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,cpuss-sleep-stats
+    then:
+      properties:
+        reg:
+          items:
+            - description: cpuss sleep stats RAM base register region.
+        reg-names:
+          items:
+            - description: names corresponding to each reg property value.
+        num-cpus:
+          items:
+            - description: provides information about the number of CPUs in the system.
+
+additionalProperties: false
+
+examples:
+  - |
+    cpuss-sleep-stats@18000054 {
+        compatible = "qcom,cpuss-sleep-stats";
+        reg = <0x18000054 0x4>, <0x18010054 0x4>, <0x18020054 0x4>,
+              <0x18030054 0x4>, <0x18040054 0x4>, <0x18050054 0x4>,
+              <0x18060054 0x4>, <0x18070054 0x4>, <0x18080098 0x4>,
+              <0x180C0000 0x10000>;
+        reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
+                    "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
+                    "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
+                    "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
+                    "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
+        num-cpus = <8>;
+     };
+
+  - |
+    cpuss-sleep-stats@17850000 {
+      compatible = "qcom,cpuss-sleep-stats-v4";
+      reg = <0x17850000 0x4000>;
+      reg-names = "base";
+    };

bindings/soc/qcom/qcom,bwprof.yaml

@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,bwprof.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Bwprof profiling driver
+
+maintainers:
+  - Shivnandan Kumar <quic_kshivnan@quicinc.com>
+  - Amir Vajid <quic_avajid@quicinc.com>
+
+description:
+  The QTI BWPROF Driver is responsible for monitoring bandwidth counters on
+  Qualcomm Technologies, Inc. (QTI) chipset that represent the read/write traffic
+  through different interconnects in the system. The driver provides this data to
+  userspace clients at modest time intervals for the purpose of bandwidth
+  profiling
+
+properties:
+  compatible:
+    enum:
+      - qcom,bwprof
+
+  reg:
+    items:
+      - description: mem freq base address
+
+  reg-names:
+    items:
+      - const: mem-freq
+
+  "#address-cells":
+    enum: [1, 2]
+
+  "#size-cells":
+    enum: [1, 2]
+
+  qcom,bus-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The width of the bus in bits.
+
+patternProperties:
+  "^qcom,bwprof[0-9-a-z]*@[0-9]*$":
+    type: object
+    description:
+      bwprof use subnodes for bwmon monitor instance.
+
+    properties:
+      compatible:
+        enum:
+          - qcom,bwprof-mon
+
+      reg:
+        description: bwprof mon base address.
+
+      reg-names:
+        items:
+          - const: base
+
+      client:
+        $ref: /schemas/types.yaml#/definitions/string
+        description: The client of bandwidth monitor, which can be either "total", "cpu", or "gpu".
+
+    additionalProperties: false
+
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - '#address-cells'
+  - '#size-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    bwprof: qcom,bwprof-ddr@19090000 {
+            compatible = "qcom,bwprof";
+            #address-cells = <1>;
+            #size-cells = <1>;
+            qcom,bus-width = <16>;
+            reg = <0x190BA050 0x10>;
+            reg-names = "mem-freq";
+
+            bwprof_0: qcom,bwprof0@19092000 {
+                    compatible = "qcom,bwprof-mon";
+                    reg = <0x19092000 0x1000>;
+                    reg-names = "base";
+                    client = "total";
+            };
+
+            bwprof_1: qcom,bwprof1@19093000 {
+                    compatible = "qcom,bwprof-mon";
+                    reg = <0x19093000 0x1000>;
+                    reg-names = "base";
+                    client = "cpu";
+            };
+
+            bwprof_2: qcom,bwprof2@19094000 {
+                    compatible = "qcom,bwprof-mon";
+                    reg = <0x19094000 0x1000>;
+                    reg-names = "base";
+                    client = "gpu";
+            };
+
+    };

bindings/soc/qcom/qcom,dynamic-memory-dump.yaml

@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/qcom/qcom,dynamic-memory-dump.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qcom Dynamic Memory Dump.
+
+maintainers:
+  - Yuanfang Zhang <quic_yuanfang@quicinc.com>
+
+description:
+  QTI dynamic memory dump driver support for dynamic allocate memory for dump entry, it allows
+  enabling dump entry via sysfs node. The memory reserved for dump entry can be reclaimed if
+  this dump entry is not enabled.
+
+properties:
+  compatible:
+    items:
+      - const: qcom,dynamic-mem-dump
+
+  memory-region:
+    description:
+      List of phandles to the reserved memory regions associated with this
+      device.
+
+required:
+  - compatible
+  - memory-region
+
+additionalProperties: false
+
+examples:
+  - |
+    dynamic_mem_dump {
+        compatible = "qcom,dynamic-mem-dump";
+        memory-region = <&dynamic_mem_dump>;
+    };
+

bindings/ufs/qcom,ufs.yaml

@@ -35,6 +35,7 @@ properties:
           - qcom,sm8450-ufshc
           - qcom,ufs-phy-qrbtc-sdm845
           - qcom,ufs-phy-qmp-v4-pineapple
+          - qcom,ufs-phy-qmp-v4-waipio
           - qcom,ufs-phy-qmp-v4-sun
       - const: qcom,ufshc
       - const: jedec,ufs-2.0

bindings/usb/qcom,snps-hs-usb-femto.yaml

@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/qcom,snps-hs-usb-femto.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Synopsis Femto High-Speed Phy
+
+maintainers:
+  - Wesley Cheng <quic_wcheng@quicinc.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,usb-hsphy-snps-femto
+          - qcom,usb-hsphy-snps-femto-lemans
+  reg:
+    description: Address and length of the registers set for the phy.
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    minItems: 1
+    items:
+      - const: hsusb_phy_base
+      - const: eud_enable_reg
+
+  vdd-supply:
+    description: vdd supply for HSPHY digital circuit operation
+
+  vdd18-supply:
+    description: 1.8 V for HSPHY.
+
+  vdd33-supply:
+    description: 3.3 V for HSPHY
+
+  qcom,vdd-voltage-level:
+    description: Voltage level of the vdd supply.
+                 This is set to min value to vote from usb.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
+  clocks:
+    description: |
+      A list of phandles to the phy clocks::
+      - ref_clk_src:: Reference clk source required for enumeration.
+      - ref_clk:: Reference clk required for enumeration.
+    minItems: 1
+    maxItems: 3
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: ref_clk_src
+      - const: ref_clk
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    items:
+      - const: phy_reset
+
+  qcom,param-override-seq:
+    description: Required if override x0/1/2 need to be changed.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+      items:
+        -
+          description: address
+        -
+          description: value
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmcc.h>
+    #include <dt-bindings/clock/qcom,gcc-blair.h>
+
+    usb2_phy0: hsphy@162b000 {
+          compatible = "qcom,usb-hsphy-snps-femto";
+          reg = <0x162B000 0x114>,
+                <0x0162A000 0x1000>;
+          reg-names = "hsusb_phy_base",
+                      "eud_enable_reg";
+
+          vdd-supply = <&L7A>;
+          vdda18-supply = <&L10A>;
+          vdda33-supply = <&L7E>;
+          qcom,vdd-voltage-level = <0 880000 880000>;
+
+          clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+          <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+          clock-names = "ref_clk_src", "ref_clk";
+
+          resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+          reset-names = "phy_reset";
+          qcom,param-override-seq =
+                     <0xa6 0x6c	/* override_x0 */
+                      0x85 0x70	/* override_x1 */
+                      0x16 0x74>;	/* override x2 */
+    };
+

qcom/Makefile

@@ -114,6 +114,27 @@ dtb-y += $(sun_tuivm-dtb-y)
 endif
 endif
 
+MONACO_BASE_DTB += monaco.dtb monacop.dtb
+
+MONACO_BOARDS += \
+        monaco-idp-v1-overlay.dtbo \
+        monaco-standalone-idp-v1-overlay.dtbo \
+        monaco-idp-v2-overlay.dtbo \
+        monaco-standalone-idp-v2-overlay.dtbo \
+        monaco-idp-v3-overlay.dtbo \
+        monaco-standalone-idp-v3-overlay.dtbo \
+        monaco-idp-v1.1-overlay.dtbo \
+        monaco-wdp-v1-overlay.dtbo \
+        monaco-wdp-v1.1-overlay.dtbo \
+        monaco-standalone-wdp-v1-overlay.dtbo \
+        monaco-atp-v1-overlay.dtbo \
+        monaco-standalone-atp-v1-overlay.dtbo
+
+monaco-dtb-$(CONFIG_ARCH_MONACO) += \
+        $(call add-overlays, $(MONACO_BOARDS) ,$(MONACO_BASE_DTB))
+monaco-overlays-dtb-$(CONFIG_ARCH_MONACO) += $(MONACO_BOARDS) $(MONACO_BASE_DTB)
+dtb-y += $(monaco-dtb-y)
+
 always-y        := $(dtb-y)
 subdir-y        := $(dts-dirs)
 clean-files     := *.dtb *.dtbo

qcom/monaco-atp-v1-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-atp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco ATP V1.0";
+	qcom,board-id = <0x010021 0x0>;
+};

qcom/monaco-atp-v1.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-idp-v1.dtsi"

qcom/monaco-dma-heaps.dtsi

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+		compatible = "qcom,dma-heaps";
+
+		qcom,qseecom {
+			qcom,dma-heap-name = "qcom,qseecom";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_mem>;
+		};
+
+		qcom,qseecom_ta {
+			qcom,dma-heap-name = "qcom,qseecom-ta";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_ta_mem>;
+		};
+
+		qcom,user_contig {
+			qcom,dma-heap-name = "qcom,user-contig";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&user_contig_mem>;
+		};
+
+		qcom,display {
+			qcom,dma-heap-name = "qcom,display";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			qcom,max-align = <9>;
+			memory-region = <&non_secure_display_memory>;
+		};
+	};
+};

qcom/monaco-gdsc.dtsi

@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	/* GDSCs in GCC */
+	gcc_camss_top_gdsc: qcom,gdsc@1458004 {
+		compatible = "qcom,gdsc";
+		reg = <0x1458004 0x4>;
+		regulator-name = "gcc_camss_top_gdsc";
+		status = "disabled";
+	};
+
+	gcc_emac0_gdsc: qcom,gdsc@145c004 {
+		compatible = "qcom,gdsc";
+		reg = <0x145c004 0x4>;
+		regulator-name = "gcc_emac0_gdsc";
+		status = "disabled";
+	};
+
+	gcc_pcie_0_gdsc: qcom,gdsc@145d004 {
+		compatible = "qcom,gdsc";
+		reg = <0x145d004 0x4>;
+		regulator-name = "gcc_pcie_0_gdsc";
+		status = "disabled";
+	};
+
+	gcc_usb20_prim_gdsc: qcom,gdsc@141c004 {
+		compatible = "qcom,gdsc";
+		reg = <0x141c004 0x4>;
+		regulator-name = "gcc_usb20_prim_gdsc";
+		status = "disabled";
+	};
+
+	gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {
+		compatible = "qcom,gdsc";
+		reg = <0x141a004 0x4>;
+		regulator-name = "gcc_usb30_prim_gdsc";
+		status = "disabled";
+	};
+
+	gcc_vcodec0_gdsc: qcom,gdsc@14580ac {
+		compatible = "qcom,gdsc";
+		reg = <0x14580ac 0x4>;
+		regulator-name = "gcc_vcodec0_gdsc";
+		status = "disabled";
+	};
+
+	gcc_venus_gdsc: qcom,gdsc@1458088 {
+		compatible = "qcom,gdsc";
+		reg = <0x1458088 0x4>;
+		regulator-name = "gcc_venus_gdsc";
+		status = "disabled";
+	};
+
+	hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
+		compatible = "qcom,gdsc";
+		reg = <0x147d078 0x4>;
+		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
+		compatible = "qcom,gdsc";
+		reg = <0x147d074 0x4>;
+		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {
+		compatible = "qcom,gdsc";
+		reg = <0x147d060 0x4>;
+		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+		status = "disabled";
+	};
+
+	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {
+		compatible = "qcom,gdsc";
+		reg = <0x147d07c 0x4>;
+		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+		status = "disabled";
+	};
+
+	/* GDSCs in DISPCC */
+	mdss_core_gdsc: qcom,gdsc@5f03000 {
+		compatible = "qcom,gdsc";
+		reg = <0x5f03000 0x4>;
+		regulator-name = "mdss_core_gdsc";
+		proxy-supply = <&mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		status = "disabled";
+	};
+
+	/* GDSCs in GPUCC */
+	gpu_gx_sw_reset: syscon@5994008 {
+		compatible = "syscon";
+		reg = <0x5994008 0x4>;
+	};
+
+	gpu_cx_hw_ctrl: syscon@5994540 {
+		compatible = "syscon";
+		reg = <0x5994540 0x4>;
+	};
+
+	gpu_gx_domain_addr: syscon@5994508 {
+		compatible = "syscon";
+		reg = <0x5994508 0x4>;
+	};
+
+	gpu_cx_gdsc: qcom,gdsc@5994064 {
+		compatible = "qcom,gdsc";
+		reg = <0x5994064 0x4>;
+		regulator-name = "gpu_cx_gdsc";
+		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
+		qcom,gds-timeout = <500>;
+		qcom,clk-dis-wait-val = <8>;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	gpu_gx_gdsc: qcom,gdsc@599400c {
+		compatible = "qcom,gdsc";
+		reg = <0x599400c 0x4>;
+		regulator-name = "gpu_gx_gdsc";
+		sw-reset = <&gpu_gx_sw_reset>;
+		domain-addr = <&gpu_gx_domain_addr>;
+		qcom,reset-aon-logic;
+		status = "disabled";
+	};
+};

qcom/monaco-haptics-fifo-data.dtsi

@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/input/qcom,hv-haptics.h>
+
+&pm5100_haptics {
+	effect_6 {
+		qcom,effect-id = <17>;
+		qcom,wf-vmax-mv = <4800>;
+		qcom,wf-fifo-data = [
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			];
+			qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>;
+			qcom,wf-brake-disable;
+			qcom,wf-auto-res-disable;
+	};
+
+	effect_7 {
+		qcom,effect-id = <18>;
+		qcom,wf-vmax-mv = <4800>;
+		qcom,wf-fifo-data = [
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			];
+			qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>;
+			qcom,wf-brake-disable;
+			qcom,wf-auto-res-disable;
+	};
+
+	effect_8 {
+		qcom,effect-id = <19>;
+		qcom,wf-vmax-mv = <4800>;
+		qcom,wf-fifo-data = [
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			];
+			qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>;
+			qcom,wf-brake-disable;
+			qcom,wf-auto-res-disable;
+	};
+
+	effect_9 {
+		qcom,effect-id = <20>;
+		qcom,wf-vmax-mv = <4800>;
+		qcom,wf-fifo-data = [
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			];
+			qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>;
+			qcom,wf-brake-disable;
+			qcom,wf-auto-res-disable;
+	};
+};

qcom/monaco-idp-v1-common.dtsi

@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-thermal-overlay.dtsi"
+#include "monaco-haptics-fifo-data.dtsi"
+
+&sdhc_1 {
+	status = "ok";
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+
+	vdd-supply = <&L25A>;
+	qcom,vdd-voltage-level = <3080000 3080000>;
+	qcom,vdd-current-level = <0 250000>;
+
+	vdd-io-supply = <&L15A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 250000>;
+};
+
+&pm5100_sdam_2 {
+	hap_cl_brake: cl_brake@7c {
+		reg = <0x7c 0x1>;
+		bits = <0 8>;
+	};
+};
+
+&pm5100_haptics {
+	nvmem-cell-names = "hap_cl_brake";
+	nvmem-cells = <&hap_cl_brake>;
+	nvmem-names = "hap_cfg_sdam";
+	nvmem = <&pm5100_sdam_23>;
+	status = "okay";
+};

qcom/monaco-idp-v1-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-idp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco IDP V1.0";
+	qcom,board-id = <0x010022 0x0>;
+};

qcom/monaco-idp-v1.1-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-idp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco IDP V1.1";
+	qcom,board-id = <0x010122 0x0>;
+};

qcom/monaco-idp-v1.dtsi

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-idp-v1-common.dtsi"
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h>
+#include <dt-bindings/iio/qti_power_supply_iio.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+&pm5100_charger {
+	qcom,remote-fg;
+	#io-channel-cells = <1>;
+	io-channels = <&pm5100_adc PM5100_ADC5_GEN3_USB_SNS_V_16>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_USB_IN_I>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_CHG_TEMP>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_DIE_TEMP>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_VPH_PWR>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_BAT_ID_100K_PU>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_BATT_THM_100K_PU>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_VBAT_SNS_QBG>;
+
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "chg_temp",
+			   "die_temp",
+			   "vph_voltage",
+			   "batt-id",
+			   "batt-temp",
+			   "batt-volt";
+};
+
+
+&pm5100_gpios {
+	nfc_clk {
+		nfc_clk_default: nfc_clk_default {
+		pins = "gpio4";
+		function = "normal";
+		input-enable;
+		power-source = <1>;
+		};
+	};
+};

qcom/monaco-idp-v2-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-idp-v2.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco IDP V2.0";
+	qcom,board-id = <0x020022 0x0>;
+};

qcom/monaco-idp-v2.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-idp-v1.dtsi"

qcom/monaco-idp-v3-overlay.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-idp-v3.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco IDP V3.0";
+	qcom,board-id = <0x030022 0x0>;
+};

qcom/monaco-idp-v3.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-idp-v1.dtsi"

qcom/monaco-pmic.dtsi

@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/iio/qti_power_supply_iio.h>
+
+&pm5100_gpios {
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio9";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <1>;
+		};
+	};
+
+	pmx_sde: pmx_sde {
+		sde_dsi_active: sde_dsi_active {
+			pinconf {
+				pins = "gpio1", "gpio2";
+				function = "normal";
+				qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+				bias-disable;
+				output-high;
+			};
+		};
+
+		sde_dsi_suspend: sde_dsi_suspend {
+			pinconf {
+				pins = "gpio1", "gpio2";
+				function = "normal";
+				qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+				bias-pull-down;
+				output-low;
+			};
+		};
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm5100_gpios 9 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+
+	pmic-pon-log {
+		compatible = "qcom,pmic-pon-log";
+		nvmem = <&pm5100_sdam_5>;
+		nvmem-names = "pon_log";
+	};
+};
+
+&pm5100_adc {
+	#thermal-sensor-cells = <1>;
+	status = "ok";
+
+	pm5100_xo_therm {
+		qcom,adc-tm-type = <1>;
+	};
+
+	pm5100_pa_therm_0 {
+		reg = <PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
+		label = "pm5100_pa_therm_0";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+
+	pm5100_quiet_therm {
+		reg = <PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
+		label = "pm5100_quiet_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+
+	pm5100_msm_therm {
+		reg = <PM5100_ADC5_GEN3_AMUX6_THM_100K_PU>;
+		label = "pm5100_msm_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+
+	pm5100_bat_id {
+		qcom,hw-settle-time = <16000>;
+	};
+};
+
+&thermal_zones {
+	xo-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX1_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	pa-therm0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	quiet-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdm-skin-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX6_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+&soc {
+	reboot_reason {
+		compatible = "qcom,reboot-reason";
+		nvmem-cells = <&restart_reason>;
+		nvmem-cell-names = "restart_reason";
+	};
+
+	monaco_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi"
+		#include "qbg-battery-profile-qrd-zwd-520mAh.dtsi"
+		#include "qbg-battery-profile-305mAh.dtsi"
+	};
+};
+
+&pm5100_charger {
+	status = "okay";
+	qcom,battery-data = <&monaco_batterydata>;
+	dpdm-supply = <&usb2_phy0>;
+	nvmem-cell-names = "charger_debug_mask", "charger_soc";
+	nvmem-cells = <&charger_debug_mask>, <&charger_soc>;
+	qcom,auto-recharge-soc = <98>;
+	qcom,suspend-input-on-debug-batt;
+	qcom,chg-term-src = <1>;
+	qcom,chg-term-current-ma = <(-20)>;
+	qcom,fcc-stepping-enable;
+	qcom,fcc-step-delay-ms = <1000>;
+	qcom,fcc-step-size-ua = <100000>;
+	qcom,fcc-step-start-ua = <200000>;
+	qcom,concurrency-mode-supported;
+};

qcom/monaco-qupv3.dtsi

@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 * Qup0 5: SE 5
+	 * Qup0 6: SE 6
+	 * Qup0 7: SE 7
+	 */
+
+	/* GPI Instance */
+	gpi_dma0: qcom,gpi-dma@4a00000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x4a00000 0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0xf6 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0xf>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		status = "ok";
+	};
+
+	/* QUPv3_0  wrapper  instance */
+	qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x4ac0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		iommus = <&apps_smmu 0xe3 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		ranges;
+		status = "ok";
+
+		/* Debug UART Instance */
+		qupv3_se6_2uart: qcom,qup_uart@4a98000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x4a98000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_2uart_tx_active>, <&qupv3_se6_2uart_rx_active>;
+			pinctrl-1 = <&qupv3_se6_2uart_sleep>;
+			status = "disabled";
+		};
+
+		/* HS UART Instance */
+		qupv3_se5_4uart: qcom,qup_uart@4a94000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x4a94000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+					<&tlmm 29 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
+			<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
+			pinctrl-1 = <&qupv3_se5_cts>, <&qupv3_se5_rts>,
+			<&qupv3_se5_tx>, <&qupv3_se5_rx>;
+			pinctrl-2 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
+			<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
+			pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
+			<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se0_i2c: i2c@4a80000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a80000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+			dmas = <&gpi_dma0 0 0 3 64 0>,
+				<&gpi_dma0 1 0 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se0_spi: spi@4a80000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a80000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
+				<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se0_spi_sleep>;
+			dmas = <&gpi_dma0 0 0 1 64 0>,
+				<&gpi_dma0 1 0 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se1_i2c: i2c@4a84000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a84000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+			dmas = <&gpi_dma0 1 0 3 64 0>,
+				<&gpi_dma0 1 1 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se1_spi: spi@4a84000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a84000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
+				<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se1_spi_sleep>;
+			dmas = <&gpi_dma0 0 1 1 64 0>,
+				<&gpi_dma0 1 1 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se2_i2c: i2c@4a88000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a88000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+			dmas = <&gpi_dma0 0 2 3 64 0>,
+				<&gpi_dma0 1 2 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se2_spi: spi@4a88000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a88000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
+				<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se2_spi_sleep>;
+			dmas = <&gpi_dma0 0 2 1 64 0>,
+				<&gpi_dma0 1 2 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se3_i2c: i2c@4a8c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a8c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+			dmas = <&gpi_dma0 0 3 3 64 0>,
+				<&gpi_dma0 1 3 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se3_spi: spi@4a8c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a8c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
+				<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se3_spi_sleep>;
+			dmas = <&gpi_dma0 0 3 1 64 0>,
+				<&gpi_dma0 1 3 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se4_i2c: i2c@4a90000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a90000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+			dmas = <&gpi_dma0 0 4 3 64 0>,
+				<&gpi_dma0 1 4 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se4_spi: spi@4a90000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a90000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
+				<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se4_spi_sleep>, <&qupv3_se4_spi_cs_sleep> ;
+			dmas = <&gpi_dma0 0 4 1 64 0>,
+				<&gpi_dma0 1 4 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se5_i2c: i2c@4a94000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a94000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+			dmas = <&gpi_dma0 0 5 3 64 0>,
+				<&gpi_dma0 1 5 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se5_spi: spi@4a94000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a94000 0x4000>;
+			reg-names = "se_phys";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
+				<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se5_spi_sleep>;
+			dmas = <&gpi_dma0 0 5 1 64 0>,
+				<&gpi_dma0 1 5 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se6_i2c: i2c@4a98000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a98000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+			dmas = <&gpi_dma0 0 6 3 64 0>,
+				<&gpi_dma0 1 6 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se6_spi: spi@4a98000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a98000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
+				<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se6_spi_sleep>;
+			dmas = <&gpi_dma0 0 6 1 64 0>,
+				<&gpi_dma0 1 6 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se7_i2c_a: i2c_a@4a9c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a9c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc  SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_i2c_sda_a>, <&qupv3_se7_i2c_scl_a>;
+			pinctrl-1 = <&qupv3_se7_i2c_sleep_a>;
+			dmas = <&gpi_dma0 0 7 3 64 0>,
+				<&gpi_dma0 1 7 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se7_spi_a: spi@4a9c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a9c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_spi_mosi_a>, <&qupv3_se7_spi_miso_a>,
+				<&qupv3_se7_spi_clk_a>, <&qupv3_se7_spi_cs_a>;
+			pinctrl-1 = <&qupv3_se0_spi_sleep>;
+			dmas = <&gpi_dma0 0 7 1 64 0>,
+				<&gpi_dma0 1 7 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se7_i2c_b: i2c_b@4a9c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a9c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_i2c_sda_b>, <&qupv3_se7_i2c_scl_b>;
+			pinctrl-1 = <&qupv3_se7_i2c_sleep_b>;
+			dmas = <&gpi_dma0 0 7 3 64 0>,
+				<&gpi_dma0 1 7 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+	};
+};

qcom/monaco-regulators.dtsi

@@ -0,0 +1,552 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+
+&rpm_bus {
+	/* PM5100 L1 - VDD_CX supply */
+	rpm-regulator-smpa1 {
+		status = "okay";
+		qcom,resource-name = "rwcx";
+		qcom,resource-id = <0>;
+		proxy-supply = <&VDD_CX_LEVEL>;
+		VDD_CX_LEVEL:
+		S1A_LEVEL: pm5100_s1_level: regulator-s1-level {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_s1_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,init-voltage-level =
+				<RPM_SMD_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPM_SMD_REGULATOR_LEVEL_TURBO
+				 RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		VDD_CX_FLOOR_LEVEL:
+		S1A_FLOOR_LEVEL:
+		pm5100_s1_floor_level: regulator-s1-floor-level {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_s1_floor_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-floor-level;
+			qcom,always-send-voltage;
+		};
+
+		VDD_CX_LEVEL_AO:
+		S1A_LEVEL_AO: pm5100_s1_level_ao: regulator-s1-level-ao {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_s1_level_ao";
+			qcom,set = <1>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		cx_cdev: cx-cdev-lvl {
+			/* compatible = "qcom,regulator-cooling-device"; */
+			regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>;
+			regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NONE
+					RPM_SMD_REGULATOR_LEVEL_NOM>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	rpm-regulator-smpa3 {
+		status = "okay";
+		S3A: pm5100_s3: regulator-s3 {
+			regulator-min-microvolt = <1144000>;
+			regulator-max-microvolt = <1320000>;
+			qcom,init-voltage = <1320000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-smpa4 {
+		status = "okay";
+		S4A: pm5100_s4: regulator-s4 {
+			regulator-min-microvolt = <1816000>;
+			regulator-max-microvolt = <1904000>;
+			qcom,init-voltage = <1904000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-smpa5 {
+		status = "okay";
+		S5A: pm5100_s5: regulator-s5 {
+			regulator-min-microvolt = <664000>;
+			regulator-max-microvolt = <1000000>;
+			qcom,init-voltage = <952000>;
+			status = "okay";
+		};
+	};
+
+	/* VDD_LPI_CX supply */
+	rpm-regulator-ldoa4 {
+		status = "okay";
+		qcom,resource-name = "rwlc";
+		qcom,resource-id = <0>;
+		VDD_LPI_CX_LEVEL:
+		L4A_LEVEL: pm5100_l4_level: regulator-l4-level {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l4_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+	};
+
+	/* VDD_LPI_MX supply */
+	rpm-regulator-ldoa5 {
+		status = "okay";
+		qcom,resource-name = "rwlm";
+		qcom,resource-id = <0>;
+		VDD_LPI_MX_LEVEL:
+		L5A_LEVEL: pm5100_l5_level: regulator-l5-level {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l5_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+	};
+
+	rpm-regulator-ldoa1 {
+		status = "okay";
+		L1A: pm5100_l1: regulator-l1 {
+			regulator-min-microvolt = <504000>;
+			regulator-max-microvolt = <752000>;
+			qcom,init-voltage = <504000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa2 {
+		status = "okay";
+		L2A: pm5100_l2: regulator-l2 {
+			regulator-min-microvolt = <312000>;
+			regulator-max-microvolt = <888000>;
+			qcom,init-voltage = <824000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa3 {
+		status = "okay";
+		qcom,resource-name = "rwmx";
+		qcom,resource-id = <0>;
+		proxy-supply = <&VDD_MXA_LEVEL>;
+
+		VDD_MX_LEVEL:
+		VDD_MXA_LEVEL:
+		VDD_EBI_LEVEL:
+		L3A_LEVEL:
+		pm5100_l3_level: regulator-pm5100-l3-level {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l3_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPM_SMD_REGULATOR_LEVEL_TURBO
+				 RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		VDD_MX_LEVEL_AO:
+		VDD_MXA_LEVEL_AO:
+		VDD_EBI_LEVEL_AO:
+		L3A_LEVEL_AO:
+		pm5100_l3_level_ao: regulator-pm5100-l3-level-ao {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l3_level_ao";
+			qcom,set = <1>;
+			regulator-min-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		mx_cdev: mx-cdev-lvl {
+			/* compatible = "qcom,regulator-cooling-device"; */
+			regulator-cdev-supply = <&VDD_MXA_LEVEL>;
+			regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NONE
+					RPM_SMD_REGULATOR_LEVEL_NOM>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	rpm-regulator-ldoa7 {
+		status = "okay";
+		L7A: pm5100_l7: regulator-l7 {
+			regulator-min-microvolt = <624000>;
+			regulator-max-microvolt = <624000>;
+			qcom,init-voltage = <624000>;
+			status = "okay";
+		};
+	};
+
+	/* WCSS_CX and WCSS_MX */
+	rpm-regulator-ldoa8 {
+		status = "okay";
+		qcom,supported-modes =
+			<RPM_SMD_REGULATOR_MODE_RET
+			RPM_SMD_REGULATOR_MODE_LPM
+			RPM_SMD_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000 30000>;
+		WCSS_CX:
+		WCSS_MX:
+		L8A: pm5100_l8: regulator-l8 {
+			regulator-min-microvolt = <312000>;
+			regulator-max-microvolt = <752000>;
+			qcom,init-voltage = <752000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa9 {
+		status = "okay";
+		L9A: pm5100_l9: regulator-l9 {
+			regulator-min-microvolt = <1232000>;
+			regulator-max-microvolt = <1232000>;
+			qcom,init-voltage = <1232000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa10 {
+		status = "okay";
+		L10A: pm5100_l10: regulator-l10 {
+			regulator-min-microvolt = <1128000>;
+			regulator-max-microvolt = <1128000>;
+			qcom,init-voltage = <1128000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa11 {
+		status = "okay";
+		L11A: pm5100_l11: regulator-l11 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			qcom,init-voltage = <1000000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa12 {
+		status = "okay";
+		L12A: pm5100_l12: regulator-l12 {
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <904000>;
+			qcom,init-voltage = <904000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa13 {
+		status = "okay";
+		qcom,supported-modes =
+			<RPM_SMD_REGULATOR_MODE_RET
+			RPM_SMD_REGULATOR_MODE_LPM
+			RPM_SMD_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000 30000>;
+		L13A: pm5100_l13: regulator-l13 {
+			regulator-min-microvolt = <1304000>;
+			regulator-max-microvolt = <1304000>;
+			qcom,init-voltage = <1304000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa14 {
+		status = "okay";
+		L14A: pm5100_l14: regulator-l14 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa15 {
+		status = "okay";
+		L15A: pm5100_l15: regulator-l15 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa16 {
+		status = "okay";
+		L16A: pm5100_l16: regulator-l16 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa17 {
+		status = "okay";
+		L17A: pm5100_l17: regulator-l17 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa18 {
+		status = "okay";
+		L18A: pm5100_l18: regulator-l18 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa19 {
+		status = "okay";
+		L19A: pm5100_l19: regulator-l19 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa20 {
+		status = "okay";
+		L20A: pm5100_l20: regulator-l20 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa21 {
+		status = "okay";
+		L21A: pm5100_l21: regulator-l21 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa22 {
+		status = "okay";
+		L22A: pm5100_l22: regulator-l22 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa23 {
+		status = "okay";
+		L23A: pm5100_l23: regulator-l23 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa24 {
+		status = "okay";
+		L24A: pm5100_l24: regulator-l24 {
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <3304000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa25 {
+		status = "okay";
+		L25A: pm5100_l25: regulator-l25 {
+			parent-supply = <&L12A>;
+			regulator-min-microvolt = <3080000>;
+			regulator-max-microvolt = <3080000>;
+			qcom,init-voltage = <3080000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa26 {
+		status = "okay";
+		L26A: pm5100_l26: regulator-l26 {
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <3304000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa27 {
+		status = "okay";
+		L27A: pm5100_l27: regulator-l27 {
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <2704000>;
+			qcom,init-voltage = <2704000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa28 {
+		status = "okay";
+		L28A: pm5100_l28: regulator-l28 {
+			regulator-min-microvolt = <2904000>;
+			regulator-max-microvolt = <2904000>;
+			qcom,init-voltage = <2904000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa29 {
+		status = "okay";
+		L29A: pm5100_l29: regulator-l29 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-boba {
+		status = "okay";
+		qcom,supported-modes =
+			<RPM_SMD_REGULATOR_MODE_PASS
+			RPM_SMD_REGULATOR_MODE_LPM
+			RPM_SMD_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1000000 2000000>;
+
+		BOB: pm5100a_bob: regulator-pm5100a-bob {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <4800000>;
+			qcom,init-voltage = <3300000>;
+			qcom,init-bob-mode = <RPM_SMD_REGULATOR_MODE_PASS>;
+			status = "okay";
+		};
+
+		BOB_AO: pm5100a_bob_ao: regulator-pm5100a-bob-ao {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <4800000>;
+			qcom,init-voltage = <3300000>;
+			qcom,init-bob-mode = <RPM_SMD_REGULATOR_MODE_AUTO>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom1 {
+		status = "okay";
+		L1C: pm8010_l1: regulator-l1 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom2 {
+		status = "okay";
+		L2C: pm8010_l2: regulator-l2 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom3 {
+		status = "okay";
+		L3C: pm8010_l3: regulator-l3 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom4 {
+		status = "okay";
+		L4C: pm8010_l4: regulator-l4 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom5 {
+		status = "okay";
+		L5C: pm8010_l5: regulator-l5 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom6 {
+		status = "okay";
+		L6C: pm8010_l6: regulator-l6 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom7 {
+		status = "okay";
+		L7C: pm8010_l7: regulator-l7 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			qcom,init-voltage = <3000000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-chg-boost {
+		status = "okay";
+		SPKR_BOOST: pm5100_chg_boost: regulator-chg-boost {
+			regulator-min-microvolt = <4100000>;
+			regulator-max-microvolt = <5600000>;
+			qcom,init-voltage = <4100000>;
+			status = "okay";
+		};
+	};
+};

qcom/monaco-standalone-atp-v1-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-standalone-atp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco standalone ATP V1.0";
+	qcom,board-id = <0x010021 0x1>;
+};

qcom/monaco-standalone-atp-v1.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-standalone-idp-v1.dtsi"

qcom/monaco-standalone-idp-v1-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-standalone-idp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco standalone IDP V1.0";
+	qcom,board-id = <0x010022 0x1>;
+};

qcom/monaco-standalone-idp-v1.dtsi

@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-idp-v1-common.dtsi"
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h>
+#include <dt-bindings/iio/qti_power_supply_iio.h>
+
+&pm5100_qbg {
+	status = "ok";
+	qcom,battery-data = <&monaco_batterydata>;
+	nvmem-cell-names = "qbg_debug_mask_low", "qbg_debug_mask_high", "skip_esr_state";
+	nvmem-cells = <&qbg_debug_mask_low>, <&qbg_debug_mask_high>, <&skip_esr_state>;
+	#io-channel-cells = <1>;
+	io-channels = <&pm5100_adc PM5100_ADC5_GEN3_BATT_THM_100K_PU>,
+			<&pm5100_adc PM5100_ADC5_GEN3_BAT_ID_100K_PU>,
+			<&pm5100_charger PSY_IIO_CHARGE_DONE>,
+			<&pm5100_charger PSY_IIO_RECHARGE_SOC>,
+			<&pm5100_charger PSY_IIO_FORCE_RECHARGE>,
+			<&pm5100_charger PSY_IIO_SYS_SOC>;
+	io-channel-names = "batt-temp",
+			"batt-id",
+			"charge_done",
+			"recharge_soc",
+			"force_recharge",
+			"sys_soc";
+	qcom,vbat-cutoff-mv = <3100>;
+	qcom,ibat-cutoff-ma = <10>;
+	qcom,vph-min-mv = <2500>;
+	qcom,iterm-ma = <20>;
+	qcom,vbatt-empty-threshold-mv = <3000>;
+};
+
+&pm5100_charger {
+	#io-channel-cells = <1>;
+	io-channels = <&pm5100_adc PM5100_ADC5_GEN3_USB_SNS_V_16>,
+			<&pm5100_adc PM5100_ADC5_GEN3_USB_IN_I>,
+			<&pm5100_adc PM5100_ADC5_GEN3_CHG_TEMP>,
+			<&pm5100_adc PM5100_ADC5_GEN3_DIE_TEMP>,
+			<&pm5100_adc PM5100_ADC5_GEN3_VPH_PWR>,
+			<&pm5100_qbg PSY_IIO_RESISTANCE_ID>,
+			<&pm5100_qbg PSY_IIO_VOLTAGE_NOW>,
+			<&pm5100_qbg PSY_IIO_TEMP>,
+			<&pm5100_qbg PSY_IIO_CAPACITY>,
+			<&pm5100_qbg PSY_IIO_VOLTAGE_OCV>,
+			<&pm5100_qbg PSY_IIO_VOLTAGE_AVG>,
+			<&pm5100_qbg PSY_IIO_DEBUG_BATTERY>,
+			<&pm5100_qbg PSY_IIO_CURRENT_NOW>,
+			<&pm5100_qbg PSY_IIO_VOLTAGE_MAX>,
+			<&pm5100_qbg PSY_IIO_CHARGE_FULL>,
+			<&pm5100_qbg PSY_IIO_CHARGE_COUNTER>,
+			<&pm5100_qbg PSY_IIO_CYCLE_COUNT>,
+			<&pm5100_qbg PSY_IIO_CHARGE_FULL_DESIGN>,
+			<&pm5100_qbg PSY_IIO_TIME_TO_FULL_NOW>;
+
+	io-channel-names = "usb_in_voltage",
+				"usb_in_current",
+				"chg_temp",
+				"die_temp",
+				"vph_voltage",
+				"resistance_id",
+				"voltage_now",
+				"temp",
+				"capacity",
+				"voltage_ocv",
+				"voltage_avg",
+				"debug_battery",
+				"current_now",
+				"voltage_max",
+				"charge_full",
+				"charge_counter",
+				"cycle_count",
+				"charge_full_design",
+				"time_to_full_now";
+};
+

qcom/monaco-standalone-idp-v2-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-standalone-idp-v2.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco standalone IDP V2.0";
+	qcom,board-id = <0x020022 0x1>;
+};

qcom/monaco-standalone-idp-v2.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-standalone-idp-v1.dtsi"

qcom/monaco-standalone-idp-v3-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-standalone-idp-v3.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco standalone IDP V3.0";
+	qcom,board-id = <0x030022 0x1>;
+};

qcom/monaco-standalone-idp-v3.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-standalone-idp-v1.dtsi"

qcom/monaco-standalone-wdp-v1-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-standalone-wdp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco standalone WDP V1.0";
+	qcom,board-id = <0x010024 0x1>;
+};

qcom/monaco-standalone-wdp-v1.dtsi

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-standalone-idp-v1.dtsi"
+#include "monaco-thermal-wdp.dtsi"

qcom/monaco-thermal-overlay.dtsi

@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&thermal_zones {
+	pm5100-tz {
+		cooling-maps {
+			trip0_cpu0 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&CPU0 1 1>;
+			};
+
+			trip1_cpu2 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			trip1_cpu3 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl0 {
+		cooling-maps {
+			cpu0_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&CPU0 2 2>;
+			};
+
+			cpu2_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			cpu3_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl1 {
+		cooling-maps {
+			cpu0_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&CPU0 2 2>;
+			};
+
+			cpu1_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&msm_gpu 4 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl2 {
+		cooling-maps {
+			/* Need to update once we get fine tuned data */
+		};
+	};
+
+	socd {
+		cooling-maps {
+			soc_cpu0 {
+				trip = <&socd_trip>;
+				cooling-device = <&CPU0 1 1>;
+			};
+
+			soc_cpu2 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			soc_cpu3 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&socd_trip>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+};

qcom/monaco-thermal-wdp.dtsi

@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&pm5100_adc {
+	pm5100_pa_therm_0 {
+		reg = <PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
+	};
+
+	pm5100_quiet_therm {
+		status = "disabled";
+	};
+
+	pm5100_cam_therm {
+		reg = <PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
+		label = "pm5100_cam_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+};
+
+&thermal_zones {
+	quiet-therm {
+		status = "disabled";
+	};
+
+	pa-therm0 {
+		polling-delay-passive = <1000>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
+		trips {
+			pa_bat_trip0: pa-bat-trip0 {
+				temperature = <42000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			pa_silver_trip: pa-silver-trip {
+				temperature = <44000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pa_cx_trip: pa-cx-trip {
+				temperature = <44000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+
+			pa_bat_trip1: pa-bat-trip1 {
+				temperature = <45000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			pa_gpu_trip: pa-gpu-trip {
+				temperature = <48000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pa_bat_trip2: pa-bat-trip2 {
+				temperature = <48000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			pa_silver_cdev {
+				trip = <&pa_silver_trip>;
+				/* throttle to 864000KHz */
+				cooling-device = <&CPU0 0 2>;
+			};
+
+			pa_gpu_cdev {
+				trip = <&pa_gpu_trip>;
+				/* throttle to 700000000Hz */
+				cooling-device = <&msm_gpu 0 3>;
+			};
+
+			queit_cdev2 {
+				trip = <&pa_cx_trip>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			pa_cdev3 {
+				trip = <&pa_cx_trip>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			pa_cdev4 {
+				trip = <&pa_bat_trip0>;
+				cooling-device = <&pm5100_charger 7 7>;
+			};
+
+			pa_cdev5 {
+				trip = <&pa_bat_trip1>;
+				cooling-device = <&pm5100_charger 9 9>;
+			};
+
+			pa_cdev6 {
+				trip = <&pa_bat_trip2>;
+				cooling-device = <&pm5100_charger 15 15>;
+			};
+		};
+	};
+
+	cam-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cam_therm0_trip0: cam-therm0-trip0 {
+				temperature = <42000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			cam_therm0_trip1: cam-therm0-trip1 {
+				temperature = <44000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			cam_therm0_trip2: cam-therm0-trip2 {
+				temperature = <52000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cam_therm0_cdev0:cam-therm0-cdev0 {
+				trip = <&cam_therm0_trip0>;
+				cooling-device = <&modem_pa 1 1>;
+			};
+
+			cam_therm0_cdev1:cam-therm0-cdev1 {
+				trip = <&cam_therm0_trip1>;
+				cooling-device = <&modem_pa 2 2>;
+			};
+
+			cam_therm0_cdev2:cam-therm0-cdev2 {
+				trip = <&cam_therm0_trip2>;
+				cooling-device = <&modem_pa 3 3>;
+			};
+		};
+	};
+};

qcom/monaco-thermal.dtsi

@@ -0,0 +1,475 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&msm_gpu {
+	#cooling-cells = <2>;
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	lmh_dcvs0: qcom,limits-dcvs@f550800 {
+		compatible = "qcom,msm-hw-limits";
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,affinity = <0>;
+		reg = <0xf550800 0x1000>,
+			<0xf521000 0x1000>;
+	};
+
+	qcom,cpu-pause {
+		compatible = "qcom,thermal-pause";
+
+		cpu0_pause: cpu0-pause {
+			qcom,cpus = <&CPU0>;
+			qcom,cdev-alias = "thermal-pause-1";
+			#cooling-cells = <2>;
+		};
+
+		cpu1_pause: cpu1-pause {
+			qcom,cpus = <&CPU1>;
+			qcom,cdev-alias = "thermal-pause-2";
+			#cooling-cells = <2>;
+		};
+
+		cpu2_pause: cpu2-pause {
+			qcom,cpus = <&CPU2>;
+			qcom,cdev-alias = "thermal-pause-4";
+			#cooling-cells = <2>;
+		};
+
+		cpu3_pause: cpu3-pause {
+			qcom,cpus = <&CPU3>;
+			qcom,cdev-alias = "thermal-pause-8";
+			#cooling-cells = <2>;
+		};
+
+	/* Thermal-engine cooling devices */
+		pause-cpu0 {
+			qcom,cpus = <&CPU0>;
+			qcom,cdev-alias = "pause-cpu0";
+		};
+
+		pause-cpu1 {
+			qcom,cpus = <&CPU1>;
+			qcom,cdev-alias = "pause-cpu1";
+		};
+
+		pause-cpu2 {
+			qcom,cpus = <&CPU2>;
+			qcom,cdev-alias = "pause-cpu2";
+		};
+
+		pause-cpu3 {
+			qcom,cpus = <&CPU3>;
+			qcom,cdev-alias = "pause-cpu3";
+		};
+	};
+
+	tsens0:tsens@4410000 {
+		//compatible = "qcom,tsens26xx";
+		reg = <0x04410000 0x20>,
+			<0x04411000 0x140>;
+		reg-names = "tsens_srot_physical",
+				"tsens_tm_physical";
+		interrupts-extended = <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+				<&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<&mpm 89 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "tsens-upper-lower",
+				"tsens-critical",
+				"tsens-0C";
+		tsens-reinit-wa;
+		0C-sensor-num = <16>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	qmi-tmd-devices {
+		compatible = "qcom,qmi-cooling-devices";
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_INST_ID>;
+
+			modem_pa: modem_pa {
+				qcom,qmi-dev-name = "pa";
+				#cooling-cells = <2>;
+			};
+
+			modem_tj: modem_tj {
+				qcom,qmi-dev-name = "modem";
+				#cooling-cells = <2>;
+			};
+
+			modem_skin: modem_skin {
+				qcom,qmi-dev-name = "modem_skin";
+				#cooling-cells = <2>;
+			};
+
+			modem_wlan: modem_wlan {
+				qcom,qmi-dev-name = "wlan";
+				#cooling-cells = <2>;
+			};
+
+			modem_tmd_rf_cal: modem_tmd_rf_cal {
+				qcom,qmi-dev-name = "tmd_rf_cal";
+				#cooling-cells = <2>;
+			};
+		};
+
+		adsp {
+			qcom,instance-id = <QMI_ADSP_INST_ID>;
+
+			adsp_vdd: adsp_vdd {
+				qcom,qmi-dev-name = "cpuv_restriction_cold";
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
+	qmi_sensor: qmi-ts-sensors {
+		compatible = "qcom,qmi-sensors";
+		#thermal-sensor-cells = <1>;
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_INST_ID>;
+			qcom,qmi-sensor-names = "rf_cal";
+		};
+	};
+
+	lmh_cpu_vdd: qcom,lmh-cpu-vdd@f550800 {
+		//compatible = "qcom,lmh-cpu-vdd";
+		reg =  <0xf550800 0x1000>;
+		#cooling-cells = <2>;
+	};
+
+	qcom,devfreq-cdev {
+		compatible = "qcom,devfreq-cdev";
+		qcom,devfreq = <&msm_gpu>;
+	};
+
+	qcom,cpufreq-cdev {
+		compatible = "qcom,cpufreq-cdev";
+		cpu-cluster0 {
+			qcom,cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
+		};
+	};
+};
+
+&thermal_zones {
+	mapss {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 0>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	wlan {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 1>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 2>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu0_2_config: cpu-0-2-config {
+				temperature = <100000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu0_cdev {
+				trip = <&cpu0_2_config>;
+				cooling-device = <&cpu0_pause 1 1>;
+			};
+
+			cpu2_cdev {
+				trip = <&cpu0_2_config>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+		};
+	};
+
+	cpuss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 3>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu1_3_config: cpu-1-3-config {
+				temperature = <100000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu1_cdev {
+				trip = <&cpu1_3_config>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			cpu3_cdev {
+				trip = <&cpu1_3_config>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+		};
+	};
+
+	mdm-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 4>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			mdm0_cx_mon: mdm0-cx-mon {
+				temperature = <90000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			mdm0-cx-cdev0 {
+				trip = <&mdm0_cx_mon>;
+				cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
+			};
+
+			mdm0-cx-cdev1 {
+				trip = <&mdm0_cx_mon>;
+				cooling-device = <&modem_tj 3 3>;
+			};
+		};
+	};
+
+	mdm-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 5>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			mdm1_cx_mon: mdm1-cx-mon {
+				temperature = <90000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			mdm1-cx-cdev0 {
+				trip = <&mdm1_cx_mon>;
+				cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
+			};
+
+			mdm1-cx-cdev1 {
+				trip = <&mdm1_cx_mon>;
+				cooling-device = <&modem_tj 3 3>;
+			};
+		};
+	};
+
+	gpu {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 6>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			gpu_step_trip: gpu-trip {
+				temperature = <85000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			gpu_cx_mon: gpu-cx-mon {
+				temperature = <90000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu-cdev {
+				trip = <&gpu_step_trip>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+
+			gpu-cx-cdev0 {
+				trip = <&gpu_cx_mon>;
+				cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
+			};
+
+			gpu-cx-cdev1 {
+				trip = <&gpu_cx_mon>;
+				cooling-device = <&modem_tj 3 3>;
+			};
+		};
+	};
+
+	camera {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 7>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	zeroc {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 16>;
+		trips {
+			zeroc_0_trip: active-config0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lmh_cpu_cdev {
+				trip = <&zeroc_0_trip>;
+				cooling-device = <&lmh_cpu_vdd 1 1>;
+			};
+
+			cx_vdd_cdev {
+				trip = <&zeroc_0_trip>;
+				cooling-device = <&cx_cdev 1 1>;
+			};
+
+			mx_vdd_cdev {
+				trip = <&zeroc_0_trip>;
+				cooling-device = <&mx_cdev 1 1>;
+			};
+
+			adsp_vdd_cdev {
+				trip = <&zeroc_0_trip>;
+				cooling-device = <&adsp_vdd 1 1>;
+			};
+		};
+	};
+
+	rf_cal {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_RF_CAL)>;
+		trips {
+			rf_cal_trip: rf-cal-config {
+				temperature = <2000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			bcl_off_cdev {
+				trip = <&rf_cal_trip>;
+				cooling-device = <&bcl_off 1 1>;
+			};
+
+			tmd_rf_cal_cdev {
+				trip = <&rf_cal_trip>;
+				cooling-device = <&modem_tmd_rf_cal 1 1>;
+			};
+		};
+	};
+};

qcom/monaco-usb.dtsi

@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-monaco.h>
+#include <dt-bindings/interconnect/qcom,monaco.h>
+
+&soc {
+	/* Primary USB port related controller */
+	usb0: hsusb@4e00000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x4e00000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq", "hs_phy_irq";
+
+		clocks = <&gcc GCC_USB20_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_USB2_PRIM_CLKREF_CLK>,
+			<&gcc GCC_USB20_SLEEP_CLK>,
+			<&gcc GCC_USB20_MOCK_UTMI_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+				"xo", "sleep_clk", "utmi_clk";
+
+		resets = <&gcc GCC_USB20_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
+		dpdm-supply = <&usb2_phy0>;
+		extcon = <&eud>;
+
+		qcom,core-clk-rate = <60000000>;
+		qcom,default-bus-vote = <2>; /* use svs bus voting */
+
+		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
+		interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
+				<&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
+				<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
+
+		qcom,pm-qos-latency = <2>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			0x110 /* GSI_DBL_ADDR_L */
+			0x120 /* GSI_DBL_ADDR_H */
+			0x130 /* GSI_RING_BASE_ADDR_L */
+			0x144 /* GSI_RING_BASE_ADDR_H */
+			0x1a4>; /* GSI_IF_STS */
+
+		dwc3@4e00000 {
+			compatible = "snps,dwc3";
+			reg = <0x4e00000 0xcd00>;
+
+			iommus = <&apps_smmu 0x120 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
+
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
+			snps,disable-clk-gating;
+			snps,is-utmi-l1-suspend;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+		};
+
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@1613000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x1613000 0x120>,
+			<0x01612000 0x4>;
+		reg-names = "hsusb_phy_base",
+			"eud_enable_reg";
+
+		vdd-supply = <&L12A>;
+		vdda18-supply = <&L14A>;
+		vdda33-supply = <&L25A>;
+		qcom,vdd-voltage-level = <0 904000 904000>;
+
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+};

qcom/monaco-wdp-v1-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-wdp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco WDP V1.0";
+	qcom,board-id = <0x010024 0x0>;
+};

qcom/monaco-wdp-v1.1-overlay.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-wdp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco WDP V1.1";
+	qcom,board-id = <0x010124 0x0>;
+};

qcom/monaco-wdp-v1.dtsi

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco-idp-v1.dtsi"
+#include "monaco-thermal-wdp.dtsi"
+

qcom/monaco.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "monaco.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco SoC";
+	compatible = "qcom,monaco";
+	qcom,board-id = <0 0>;
+};

qcom/monacop.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "monacop.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. MonacoP SoC";
+	compatible = "qcom,monacop";
+	qcom,board-id = <0 0>;
+};

qcom/monacop.dtsi

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "monaco.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. MonacoP";
+	compatible = "qcom,monacop";
+	qcom,msm-id = <517 0x10000>;
+};
+
+&soc {
+	qcom,rmnet-ipa {
+		status = "disabled";
+	};
+};

qcom/msm-arm-smmu-monaco.dtsi

@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interconnect/qcom,monaco.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@0x59a0000 {
+		status = "okay";
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
+		reg = <0x59a0000 0x10000>,
+			<0x59da000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x05>;
+		qcom,num-smr-override = <0x04>;
+		#global-interrupts = <1>;
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cx_gdsc>;
+		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+			clock-names = "gcc_gpu_memnoc_gfx",
+				"gcc_gpu_snoc_dvm_gfx",
+				"gpu_cc_hlos1_vote_gpu_smmu_clk";
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,actlr =
+			/* ALL CBs of GFX: +15 deep PF */
+			<0x0 0x3ff 0x32B>;
+
+		gfx_0_tbu: gfx_0_tbu@0x59dd000 {
+				compatible = "qcom,qsmmuv500-tbu";
+				reg = <0x59dd000 0x1000>,
+					<0x59da200 0x8>;
+				reg-names = "base", "status-reg";
+				qcom,stream-id-range = <0x0 0x400>;
+				interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,iova-width = <49>;
+		};
+	};
+
+	apps_smmu: apps-smmu@0xc600000 {
+				status = "okay";
+				compatible = "qcom,qsmmu-v500";
+				reg = <0xc600000 0x80000>,
+					<0xc7f2000 0x20>;
+				reg-names = "base", "tcu-base";
+				#iommu-cells = <2>;
+				qcom,skip-init;
+				qcom,use-3-lvl-tables;
+				qcom,num-context-banks-override = <0x32>;
+				qcom,num-smr-override = <0x28>;
+				qcom,handoff-smrs = <0x420 0x2>;
+				#global-interrupts = <1>;
+				#size-cells = <1>;
+				#address-cells = <1>;
+				ranges;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+
+				interconnects = <&bimc MASTER_AMPSS_M0
+						 &config_noc SLAVE_TCU>;
+
+				qcom,active-only;
+
+				qcom,actlr =
+					/* For rt TBU +3 deep PF */
+					<0x400 0x3ff 0x103>,
+					/* For nrt TBU +3 deep PF */
+					<0x800 0x3ff 0x103>;
+
+				anoc_1_tbu: anoc_1_tbu@0xc7f5000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc7f5000 0x1000>,
+						<0xc7f2200 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x0 0x400>;
+					interconnects = <&bimc MASTER_AMPSS_M0
+							 &config_noc SLAVE_IMEM_CFG>,
+							 <&bimc MASTER_AMPSS_M0
+							 &config_noc SLAVE_TCU>;
+					qcom,active-only;
+					qcom,iova-width = <36>;
+				};
+
+				mm_rt_tbu: mm_rt_tbu@0xc7f9000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc7f9000 0x1000>,
+						<0xc7f2208 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x400 0x400>;
+					qcom,regulator-names = "vdd";
+					vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>;
+					interconnects = <&mmrt_virt MASTER_MDP_PORT0
+							 &mmrt_virt SLAVE_SNOC_BIMC_RT>,
+							 <&bimc MASTER_AMPSS_M0
+							 &config_noc SLAVE_TCU>;
+					qcom,active-only;
+					qcom,iova-width = <36>;
+				};
+
+				mm_nrt_tbu: mm_nrt_tbu@0xc7fd000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc7fd000 0x1000>,
+						<0xc7f2210 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x800 0x400>;
+					qcom,regulator-names = "vdd";
+					vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>;
+					interconnects = <&mmnrt_virt MASTER_CAMNOC_SF
+							 &mmnrt_virt SLAVE_SNOC_BIMC_NRT>,
+							 <&bimc MASTER_AMPSS_M0
+							 &config_noc SLAVE_TCU>;
+					qcom,active-only;
+					qcom,iova-width = <36>;
+				};
+
+	};
+
+	dma_dev {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	iommu_test_device {
+		compatible = "qcom,iommu-debug-test";
+
+		kgsl_iommu_test_device {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x7 0>;
+		};
+
+		apps_iommu_test_device {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x1E0 0x0>;
+		};
+
+		apps_iommu_coherent_test_device {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x1E1 0x0>;
+			dma-coherent;
+		};
+	};
+};

qcom/msm-rdbg-monaco.dtsi

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+  /* smp2p information */
+	qcom,smp2p_interrupt_rdbg_2_out {
+		compatible = "qcom,smp2p-interrupt-rdbg-2-out";
+		qcom,smem-states = <&smp2p_rdbg2_out 0>;
+		qcom,smem-state-names = "rdbg-smp2p-out";
+	};
+
+	qcom,smp2p_interrupt_rdbg_2_in {
+		compatible = "qcom,smp2p-interrupt-rdbg-2-in";
+		interrupts-extended = <&smp2p_rdbg2_in 0 0>;
+		interrupt-names = "rdbg-smp2p-in";
+	};
+
+};

qcom/pineapple-mtp.dtsi

@@ -186,6 +186,25 @@
 	usb-repeater = <&pm8550b_eusb2_repeater>;
 };
 
+&usb0 {
+	usb-role-switch;
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};
+
 &qupv3_se4_spi {
 	#address-cells = <1>;
 	#size-cells = <0>;

qcom/pineapple-qrd.dtsi

@@ -355,10 +355,6 @@
 		 0x00 0x59>;
 };
 
-&usb0 {
-	usb-role-switch;
-};
-
 &qupv3_se6_i2c {
 	status = "ok";
 
@@ -405,6 +401,25 @@
 	gpios = <&tlmm 29 0>;
 
 	ssusb_redriver = <&redriver>;
+
+	qcom,wcd_usbss = <&wcd_usbss>;
+
+	usb-role-switch;
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
 };
 
 &regulator_ocp_notifier {

qcom/pineapple-usb.dtsi

@@ -80,6 +80,7 @@
 			tx-fifo-resize;
 			dr_mode = "otg";
 			maximum-speed = "super-speed-plus";
+			usb-role-switch;
 		};
 	};
 

qcom/pineapple.dtsi

@@ -982,7 +982,6 @@
 
 		memory-region = <&spss_region_mem>;
 
-		qcom,signal-aop;
 		qcom,qmp = <&aoss_qmp>;
 
 		qcom,spss-scsr-bits = <24 25>;
@@ -2158,7 +2157,6 @@
 		clocks = <&rpmhcc RPMH_CXO_CLK>;
 		clock-names = "xo";
 
-		qcom,signal-aop;
 		qcom,qmp = <&aoss_qmp>;
 
 		interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>,
@@ -2237,7 +2235,6 @@
 		mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
 		reg-names = "cx", "mx";
 
-		qcom,signal-aop;
 		qcom,qmp = <&aoss_qmp>;
 
 		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
@@ -2315,7 +2312,6 @@
 		clocks = <&rpmhcc RPMH_CXO_CLK>;
 		clock-names = "xo";
 
-		qcom,signal-aop;
 		qcom,qmp = <&aoss_qmp>;
 
 		interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>,

qcom/platform_map.bzl

@@ -130,6 +130,26 @@ _platform_map = {
             {"name": "pineapple-vm-rumi.dtb"},
         ],
     },
+    "monaco": {
+        "dtb_list": [
+            {"name": "monaco.dtb"},
+            {"name": "monacop.dtb"},
+        ],
+        "dtbo_list": [
+            {"name": "monaco-idp-v1-overlay.dtbo"},
+            {"name": "monaco-idp-v1.1-overlay.dtbo"},
+            {"name": "monaco-standalone-idp-v1-overlay.dtbo"},
+            {"name": "monaco-idp-v2-overlay.dtbo"},
+            {"name": "monaco-standalone-idp-v2-overlay.dtbo"},
+            {"name": "monaco-idp-v3-overlay.dtbo"},
+            {"name": "monaco-standalone-idp-v3-overlay.dtbo"},
+            {"name": "monaco-wdp-v1-overlay.dtbo"},
+            {"name": "monaco-wdp-v1.1-overlay.dtbo"},
+            {"name": "monaco-standalone-wdp-v1-overlay.dtbo"},
+            {"name": "monaco-atp-v1-overlay.dtbo"},
+            {"name": "monaco-standalone-atp-v1-overlay.dtbo"},
+        ],
+    },
 }
 
 def _get_dtb_lists(target, dt_overlay_supported):

qcom/pm5100-rpm-regulator.dtsi

@@ -0,0 +1,619 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&rpm_bus {
+	rpm-regulator-smpa1 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s1 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_s1";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa2 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <2>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s2 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_s2";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa3 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <3>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s3 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_s3";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa4 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <4>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s4 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_s4";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa5 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <5>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s5 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_s5";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa1 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l1 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l1";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa2 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <2>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l2 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l2";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa3 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <3>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l3 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l3";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa4 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <4>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l4 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l4";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa5 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <5>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l5 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l5";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa6 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <6>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l6 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l6";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa7 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <7>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l7 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l7";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa8 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <8>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l8 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l8";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa9 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <9>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l9 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l9";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa10 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <10>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l10 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l10";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa11 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <11>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l11 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l11";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa12 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <12>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l12 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l12";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa13 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <13>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l13 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l13";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa14 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <14>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l14 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l14";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa15 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <15>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l15 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l15";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa16 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <16>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l16 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l16";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa17 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <17>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l17 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l17";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa18 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <18>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l18 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l18";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa19 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <19>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l19 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l19";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa20 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <20>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l20 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l20";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa21 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <21>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l21 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l21";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa22 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <22>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l22 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l22";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa23 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <23>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l23 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l23";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa24 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <24>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l24 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l24";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa25 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <25>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l25 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l25";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa26 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <26>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l26 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l26";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa27 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <27>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l27 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l27";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa28 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <28>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l28 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l28";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa29 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <29>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l29 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_l29";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-boba {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "boba";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <4>;
+		qcom,regulator-hw-type = "pmic5-bob";
+		qcom,send-defaults;
+		status = "disabled";
+
+		regulator-pm5100a-bob {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100a_bob";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+
+		regulator-pm5100a-bob-ao {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100a_bob_ao";
+			qcom,set = <1>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-chg-boost {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "bsta";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-chg-boost {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm5100_chg_boost";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+};

qcom/pm5100.dtsi

@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/input/qcom,hv-haptics.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm5100@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pon_hlos@1300 {
+			/* compatible = "qcom,qpnp-power-on"; */
+			reg = <0x1300>;
+			interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>,
+				     <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "kpdpwr", "resin";
+
+			qcom,pon_1 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+				linux,code = <KEY_POWER>;
+			};
+
+			qcom,pon_2 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+				linux,code = <KEY_VOLUMEDOWN>;
+			};
+		};
+
+	pm5100_charger: qcom,qpnp-smblite {
+			/* compatible = "qcom,qpnp-pm5100-smblite"; */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#cooling-cells = <2>;
+
+			qcom,thermal-mitigation = <1500000 1400000
+				1300000 1200000 1100000 1000000 900000
+				800000 700000 600000 500000 400000
+				300000 200000 100000>;
+
+			qcom,chgr@2600 {
+				reg = <0x1000>;
+				interrupts =
+					<0x0 0x26 0x1 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x26 0x0 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x26 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x26 0x7 IRQ_TYPE_EDGE_RISING>;
+
+				interrupt-names = "chgr-error",
+						  "chg-state-change",
+						  "buck-oc",
+						  "vph-ov";
+			};
+
+			qcom,dcdc@2700 {
+				reg = <0x2700>;
+				interrupts =
+					<0x0 0x27 0x0 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x27 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x27 0x6 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x27 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "boost-mode-sw-en",
+						  "skip-mode",
+						  "input-current-limiting",
+						  "switcher-power-ok";
+			};
+
+			qcom,batif@2800 {
+				reg = <0x2800>;
+				interrupts =
+					<0x0 0x28 0x0 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x28 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x28 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x28 0x4 IRQ_TYPE_EDGE_RISING>;
+
+				interrupt-names = "bat-temp",
+						  "bat-low",
+						  "bat-ov",
+						  "bsm-active";
+			};
+
+			qcom,usb@2900 {
+				reg = <0x2900>;
+				interrupts =
+					<0x0 0x29 0x0 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x29 0x1 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x29 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x29 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x29 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x29 0x6 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x29 0x7 IRQ_TYPE_EDGE_RISING>;
+
+				interrupt-names = "usbin-plugin",
+						  "usbin-collapse",
+						  "usbin-uv",
+						  "usbin-ov",
+						  "usbin-gtvt",
+						  "usbin-icl-change",
+						  "usbin-src-change";
+			};
+
+			qcom,misc@2c00 {
+				reg = <0x2c00>;
+				interrupts =
+					<0x0 0x2c 0x0 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x1 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x2 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x3 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x5 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x6 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "wdog-snarl",
+						  "wdog-bark",
+						  "aicl-fail",
+						  "aicl-done",
+						  "imp-trigger",
+						  "all-chnl-cond-done",
+						  "temp-change";
+			};
+		};
+
+		pm5100_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			io-channels = <&pm5100_adc PM5100_ADC5_GEN3_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm5100_adc: vadc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			reg-names = "adc5-gen3-base";
+			qcom,debug-base = <0x8300>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#io-channel-cells = <1>;
+			status = "disabled";
+
+			pm5100_ref_gnd {
+				reg = <PM5100_ADC5_GEN3_OFFSET_REF>;
+				label = "pm5100_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm5100_vref_1p25 {
+				reg = <PM5100_ADC5_GEN3_1P25VREF>;
+				label = "pm5100_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm5100_die_temp {
+				reg = <PM5100_ADC5_GEN3_DIE_TEMP>;
+				label = "pm5100_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm5100_xo_therm {
+				reg = <PM5100_ADC5_GEN3_AMUX1_THM_100K_PU>;
+				label = "pm5100_xo_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <700>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm5100_usb_in_i_uv {
+				reg = <PM5100_ADC5_GEN3_USB_IN_I>;
+				label = "pm5100_usb_in_i_uv";
+				qcom,pre-scaling = <1 1>;
+				qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_USB_IN_I>;
+			};
+
+			pm5100_chg_temp {
+				reg = <PM5100_ADC5_GEN3_CHG_TEMP>;
+				label = "pm5100_chg_temp";
+				qcom,pre-scaling = <1 1>;
+				qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_CHG_TEMP>;
+			};
+
+			pm5100_usb_in_v {
+				reg = <PM5100_ADC5_GEN3_USB_SNS_V_16>;
+				label = "pm5100_usb_in_v";
+				qcom,pre-scaling = <1 16>;
+			};
+
+			pm5100_boost_out_v {
+				reg = <PM5100_ADC5_GEN3_VIN_DIV16_MUX>;
+				label = "pm5100_boost_out_v";
+				qcom,pre-scaling = <1 6>;
+			};
+
+			pm5100_bat_therm {
+				reg = <PM5100_ADC5_GEN3_BATT_THM_100K_PU>;
+				label = "pm5100_bat_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+				qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_THERM_100K>;
+			};
+
+			pm5100_bat_id {
+				reg = <PM5100_ADC5_GEN3_BAT_ID_100K_PU>;
+				label = "pm5100_bat_id";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+				qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_ID_100K>;
+			};
+
+			pm5100_vph_pwr {
+				reg = <PM5100_ADC5_GEN3_VPH_PWR>;
+				label = "pm5100_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+
+			pm5100_vbat_sns {
+				reg = <PM5100_ADC5_GEN3_VBAT_SNS_QBG>;
+				label = "pm5100_vbat_sns";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
+		pm5100_gpios: pinctrl@8800 {
+			/* compatible = "qcom,pm5100-gpio"; */
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm5100_rtc: rtc@6400 {
+			/* compatible = "qcom,pm5100-rtc"; */
+			reg = <0x6400>, <0x6500>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x65 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pm5100_cdc: qcom,pm5100-cdc {
+			/* compatible = "qcom,pm5100-spmi"; */
+		};
+
+		pm5100_bcl: bcl@4700 {
+			compatible = "qcom,bcl-v5";
+			reg = <0x4700 0x100>;
+			interrupts = <0x0 0x47 0x0 IRQ_TYPE_NONE>,
+					<0x0 0x47 0x1 IRQ_TYPE_NONE>,
+					<0x0 0x47 0x2 IRQ_TYPE_NONE>;
+			interrupt-names = "bcl-lvl0",
+						"bcl-lvl1",
+						"bcl-lvl2";
+			qcom,pmic7-threshold;
+			qcom,ibat-ccm-hw-support;
+			#thermal-sensor-cells = <1>;
+		};
+
+		bcl_soc:bcl-soc {
+			compatible = "qcom,msm-bcl-soc";
+			#thermal-sensor-cells = <0>;
+		};
+
+		bcl_off: bcl-off@4700 {
+			/* compatible = "qcom,bcl-off"; */
+			reg =  <0x4700 0x100>;
+			#cooling-cells = <2>;
+		};
+
+		pm5100_sdam_2: sdam@7100 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			restart_reason: restart@48 {
+				reg = <0x48 0x1>;
+				bits = <1 7>;
+			};
+
+			charger_debug_mask: debug@94 {
+				reg = <0x94 0x1>;
+			};
+
+			qbg_debug_mask_low: debug@96 {
+				reg = <0x96 0x1>;
+			};
+
+			qbg_debug_mask_high: debug@97 {
+				reg = <0x97 0x1>;
+			};
+
+		};
+
+		pm5100_sdam_5: sdam@7400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7400>;
+		};
+
+		pm5100_sdam_7: sdam@7600 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7600>;
+		};
+
+		pm5100_sdam_8: sdam@7700 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7700>;
+			charger_soc: charger_soc@47 {
+				reg = <0x65 0x2>;
+			};
+		};
+
+		pm5100_sdam_22: sdam@8500 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8500>;
+
+			/* GPS demod state */
+			skip_esr_state: demod@46 {
+				reg = <0x46 0x1>;
+			};
+		};
+
+		pm5100_sdam_23: sdam@8600 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8600>;
+		};
+
+		pm5100_qbg: qpnp,qbg@4f00 {
+			status = "disabled";
+			/* compatible = "qcom,qbg"; */
+			#address-cells = <1>;
+			reg = <0x4f00>;
+			interrupt-names = "qbg-sdam", "qbg-vbatt-empty";
+			interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x4F 0x1 IRQ_TYPE_EDGE_RISING>;
+			qcom,num-data-sdams = <5>;
+			qcom,sdam-base = <0x7600>;
+			qcom,adc-cmn-wb-base = <0x3000>;
+			qcom,adc-cmn-base = <0x3900>;
+		};
+
+		pm5100_haptics: qcom,hv-haptics@f000 {
+			compatible = "qcom,pm5100-haptics";
+			reg = <0xf000>, <0xf100>;
+			interrupts = <0x0 0xf0 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "fifo-empty";
+			qcom,vmax-mv = <2500>;
+			qcom,brake-mode = <BRAKE_CLOSE_LOOP>;
+			qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>;
+			qcom,lra-period-us = <4167>;
+			qcom,drv-sig-shape = <WF_SINE>;
+			qcom,brake-sig-shape = <WF_SINE>;
+			status = "disabled";
+
+			effect_0 {
+				/* CLICK */
+				qcom,effect-id = <0>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-pattern-preload;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_1 {
+				/* DOUBLE_CLICK */
+				qcom,effect-id = <1>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_2 {
+				/* TICK */
+				qcom,effect-id = <2>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_3 {
+				/* THUD */
+				qcom,effect-id = <3>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_4 {
+				/* POP */
+				qcom,effect-id = <4>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_5 {
+				/* HEAVY CLICK */
+				qcom,effect-id = <5>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_0 {
+				/* NOOP */
+				qcom,primitive-id = <0>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0  S_PERIOD_T_LRA  0>,
+							<0  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_1 {
+				/* CLICK */
+				qcom,primitive-id = <1>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_2 {
+				/* THUD */
+				qcom,primitive-id = <2>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_3 {
+				/* SPIN */
+				qcom,primitive-id = <3>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_4 {
+				/* QUICK_RISE */
+				qcom,primitive-id = <4>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_5 {
+				/* SLOW_RISE */
+				qcom,primitive-id = <5>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_6 {
+				/* QUICK_FALL */
+				qcom,primitive-id = <6>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_7 {
+				/* LIGHT_TICK */
+				qcom,primitive-id = <7>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_8 {
+				/* LOW_TICK */
+				qcom,primitive-id = <8>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+		};
+	};
+};
+
+&thermal_zones {
+	pm5100-tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm5100_tz>;
+
+		trips {
+			pm5100_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pm5100_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pm5100_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+
+	pm5100-ibat-lvl0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_bcl 0>;
+
+		trips {
+			ibat_lvl0:ibat-lvl0 {
+				temperature = <1500>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm5100-ibat-lvl1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_bcl 1>;
+
+		trips {
+			ibat_lvl1:ibat-lvl1 {
+				temperature = <1900>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm5100-bcl-lvl0 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_bcl 5>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			bcl_lvl0: bcl-lvl0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm5100-bcl-lvl1 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_bcl 6>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			bcl_lvl1: bcl-lvl1 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm5100-bcl-lvl2 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_bcl 7>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			bcl_lvl2: bcl-lvl2 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	socd {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&bcl_soc>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			socd_trip:socd-trip {
+				temperature = <90>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+	};
+};

qcom/pm8010-rpm-regulator.dtsi

@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&rpm_bus {
+	rpm-regulator-ldom1 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l1 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm8010_l1";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom2 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <2>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l2 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm8010_l2";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom3 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <3>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l3 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm8010_l3";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom4 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <4>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l4 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm8010_l4";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom5 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <5>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l5 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm8010_l5";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom6 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <6>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l6 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm8010_l6";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom7 {
+		/* compatible = "qcom,rpm-smd-regulator-resource"; */
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <7>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l7 {
+			/* compatible = "qcom,rpm-smd-regulator"; */
+			regulator-name = "pm8010_l7";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+};

qcom/pm8010.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -58,7 +58,7 @@
 			trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "critical";
+				type = "hot";
 			};
 
 			trip2 {
@@ -85,7 +85,7 @@
 			trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "critical";
+				type = "hot";
 			};
 
 			trip2 {

qcom/pm8550.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -201,7 +201,7 @@
 			pm8550_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550_trip2: trip2 {

qcom/pm8550ve.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -127,7 +127,7 @@
 			pm8550ve_d_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550ve_d_trip2: trip2 {
@@ -155,7 +155,7 @@
 			pm8550ve_f_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550ve_f_trip2: trip2 {
@@ -183,7 +183,7 @@
 			pm8550ve_g_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550ve_g_trip2: trip2 {
@@ -211,7 +211,7 @@
 			pm8550ve_i_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550ve_i_trip2: trip2 {

qcom/pm8550vs.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -175,7 +175,7 @@
 			pm8550vs_c_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550vs_c_trip2: trip2 {
@@ -203,7 +203,7 @@
 			pm8550vs_d_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550vs_d_trip2: trip2 {
@@ -231,7 +231,7 @@
 			pm8550vs_e_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550vs_e_trip2: trip2 {
@@ -259,7 +259,7 @@
 			pm8550vs_f_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550vs_f_trip2: trip2 {
@@ -287,7 +287,7 @@
 			pm8550vs_g_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550vs_g_trip2: trip2 {
@@ -315,7 +315,7 @@
 			pm8550vs_j_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pm8550vs_j_trip2: trip2 {

qcom/pmd802x.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -111,7 +111,7 @@
 			pmd802x_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pmd802x_trip2: trip2 {

qcom/pmih010x.dtsi

@@ -274,7 +274,7 @@
 			pmih010x_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pmih010x_trip2: trip2 {
@@ -301,7 +301,7 @@
 			pmih010x_lite_trip1: trip1 {
 				temperature = <135000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pmih010x_lite_trip2: trip2 {

qcom/pmk8550.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/input/input.h>
@@ -46,6 +46,10 @@
 				bits = <1 7>;
 			};
 
+			wr_thermal_flag: wr_thermal-flag@58 {
+				reg = <0x58 0x1>;
+			};
+
 			alarm_log: alarm-log@76 {
 				reg = <0x76 0x6>;
 			};

qcom/pmr735d.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -53,7 +53,7 @@
 			pmr735d_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "passive";
+				type = "hot";
 			};
 
 			pmr735d_trip2: trip2 {

qcom/qbg-battery-profile-305mAh.dtsi

@@ -0,0 +1,666 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+qcom,qbg-305mAh-averaged {
+	qcom,battery-type = "305MAH_AVERAGED";
+	qcom,batt-id-kohm = <10>;
+	qcom,capacity = <306>;
+	qcom,max-voltage-uv = <4400000>;
+	qcom,fastchg-current-ma = <305>;
+	qcom,checksum = <4291097>; /*@5, 0.005V, 4% */
+	qcom,soh-range = <0 100>;
+	/*Nominal_Impedance in 10nohm @ SOC 50% 25C* 0:fresh cell, 1: aged cell*/
+	qcom,battery-impedance = <95906000 191812000>;
+	/*Nominal_Capacity in mAh. 0: fresh cell, 1:aged cell*/
+	qcom,battery-capacity = <290 229>;
+	/*SOC delta (in percent) dropped from EOC SOC to enable recharge*/
+	qcom,recharge-soc-delta =<5>;
+	/*vfloat delta (in mV) dropped from regular vfloat in recharge*/
+	qcom,recharge-vflt-delta =<50>;
+	/*termination current (in mA) in recharge*/
+	qcom,recharge-iterm-ma = <6>;
+
+	qcom,jeita-fcc-ranges = <0  150 300000
+				151 420 300000
+				421 450 300000>;
+
+	qcom,jeita-fv-ranges = <0  150 4350000
+				151 420 4400000
+				421 450 4350000>;
+
+	qcom,jeita-soft-fcc-ua = <156000 200000>;
+	qcom,jeita-soft-fv-uv = <4350000 4350000>;
+
+	/* COOL = 15 DegC, WARM = 45 DegC */
+	qcom,jeita-soft-thresholds = <0x084E 0x02F5>;
+	/* COLD = 0 DegC, HOT = 45.1 DegC */
+	qcom,jeita-hard-thresholds = <0x0E46 0x02F2>;
+	/* COOL = 18 DegC, WARM = 44 DegC*/
+	qcom,jeita-soft-hys-thresholds = <0x0775 0x030E>;
+
+	qcom,bp-c-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    39    58    78    97>,
+			<  136   195   292   429   605>,
+			<  703   820  1230  1660  2089>,
+			< 2519  2949  3378  3808  4238>,
+			< 4668  5097  5527  5957  6386>,
+			< 6679  7011  7441  7793  8046>,
+			< 8476  8906  9335  9765 10000>;
+		qcom,ocv = <30000 31624 32313 32890 33333>,
+			<33923 34535 35328 36111 36802>,
+			<36976 37009 37107 37404 37703>,
+			<37930 38068 38190 38327 38495>,
+			<38696 38937 39240 39626 40124>,
+			<40429 40749 41160 41525 41800>,
+			<42271 42754 43237 43691 43888>;
+	};
+
+	qcom,bp-c-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>,
+			<43661 53533 33154 43966 47535 43707 43717 53512>,
+			<43664 54313 33152 43605 47154 43711 43736 53256>,
+			<43748 10827 33152 43587 47238 43699 43743 54029>,
+			<43723 10257 33152 43640 47977 43703 43730 53790>,
+			<43554 12213 33164 43532 48042 43663 43732 56388>,
+			<43625 11560 33206 43730 47803 43655 43567 56850>,
+			<43918  8255 32859 43724 42418 43678 43559 55529>,
+			<43783  9997 33173 43744 42220 43753 43583 56047>,
+			<43255 15048 33252 43672 42915 43765 43581 50963>,
+			<43029 14912 33276 43648 42942 43712 43576 50743>,
+			<43422 15280 33244 43698 43005 43534 43579 49501>,
+			<44644 15111 33212 43659 42051 43576 43570 50814>,
+			<44246 14406 33270 43675 48101 43712 43577 50428>,
+			<41603 16039 33087 43666 47963 43760 43570 50947>,
+			<41853 15987 33222 43759 47130 43751 43577 50697>,
+			<41263 16376 33173 43718 47602 43670 43579 49503>,
+			<42904 16145 33183 43559 48866 43674 43579 50856>,
+			<42058 15543 33257 43313 47326 43664 43994 51104>,
+			<47652 15573 33214 42336 41919 43716 45031 50181>,
+			<47254 15760 32774 47854 41975 43719 44905 50334>,
+			<47427 12947 32811 42307 41914 43719 44978 50721>,
+			<48957 13263 32831 42199 41777 43719 43504 49549>,
+			<48623 12326 32865 42222 41119 43718 43129 49576>,
+			<45656 12574 33192 42352 41210 43713 43476 49464>,
+			<45245 13834 32976 47687 41196 43713 44793 49501>,
+			<45513 14161 32968 47714 41132 43718 43331 49435>,
+			<47035 13682 32986 47768 41794 43738 43116 49621>,
+			<46299  3001 32780 47692 41445 43728 43037 50616>,
+			<46532  2216 32855 48003 42610 43743 43021 55738>,
+			<35766  2306 33037 47884 48090 43713 43202 55029>,
+			<34912  4057 33124 47963 48182 43713 43196 11457>,
+			<36573  3528 34768 41839 36598 43753 43935 15406>,
+			<35983  1015 34644 43082 33289 43655 43549  2911>,
+			<36282   225 34228 43555 35807 43657 43740 13762>;
+	};
+
+	qcom,bp-c-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>,
+			<43661 53533 33154 43966 47535 43707 43717 53512>,
+			<43664 54313 33152 43605 47154 43711 43736 53256>,
+			<43748 10827 33152 43587 47238 43699 43743 54029>,
+			<43723 10257 33152 43640 47977 43703 43730 53790>,
+			<43554 12213 33164 43532 48042 43663 43732 56388>,
+			<43625 11560 33206 43730 47803 43655 43567 56850>,
+			<43918  8255 32859 43724 42418 43678 43559 55529>,
+			<43783  9997 33173 43744 42220 43753 43583 56047>,
+			<43255 15048 33252 43672 42915 43765 43581 50963>,
+			<43029 14912 33276 43648 42942 43712 43576 50743>,
+			<43422 15280 33244 43698 43005 43534 43579 49501>,
+			<44644 15111 33212 43659 42051 43576 43570 50814>,
+			<44246 14406 33270 43675 48101 43712 43577 50428>,
+			<41603 16039 33087 43666 47963 43760 43570 50947>,
+			<41853 15987 33222 43759 47130 43751 43577 50697>,
+			<41263 16376 33173 43718 47602 43670 43579 49503>,
+			<42904 16145 33183 43559 48866 43674 43579 50856>,
+			<42058 15543 33257 43313 47326 43664 43994 51104>,
+			<47652 15573 33214 42336 41919 43716 45031 50181>,
+			<47254 15760 32774 47854 41975 43719 44905 50334>,
+			<47427 12947 32811 42307 41914 43719 44978 50721>,
+			<48957 13263 32831 42199 41777 43719 43504 49549>,
+			<48623 12326 32865 42222 41119 43718 43129 49576>,
+			<45656 12574 33192 42352 41210 43713 43476 49464>,
+			<45245 13834 32976 47687 41196 43713 44793 49501>,
+			<45513 14161 32968 47714 41132 43718 43331 49435>,
+			<47035 13682 32986 47768 41794 43738 43116 49621>,
+			<46299  3001 32780 47692 41445 43728 43037 50616>,
+			<46532  2216 32855 48003 42610 43743 43021 55738>,
+			<35766  2306 33037 47884 48090 43713 43202 55029>,
+			<34912  4057 33124 47963 48182 43713 43196 11457>,
+			<36573  3528 34768 41839 36598 43753 43935 15406>,
+			<35983  1015 34644 43082 33289 43655 43549  2911>,
+			<36282   225 34228 43555 35807 43657 43740 13762>;
+	};
+
+	qcom,bp-c-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>,
+			<43661 53533 33154 43966 47535 43707 43717 53512>,
+			<43664 54313 33152 43605 47154 43711 43736 53256>,
+			<43748 10827 33152 43587 47238 43699 43743 54029>,
+			<43723 10257 33152 43640 47977 43703 43730 53790>,
+			<43554 12213 33164 43532 48042 43663 43732 56388>,
+			<43625 11560 33206 43730 47803 43655 43567 56850>,
+			<43918  8255 32859 43724 42418 43678 43559 55529>,
+			<43783  9997 33173 43744 42220 43753 43583 56047>,
+			<43255 15048 33252 43672 42915 43765 43581 50963>,
+			<43029 14912 33276 43648 42942 43712 43576 50743>,
+			<43422 15280 33244 43698 43005 43534 43579 49501>,
+			<44644 15111 33212 43659 42051 43576 43570 50814>,
+			<44246 14406 33270 43675 48101 43712 43577 50428>,
+			<41603 16039 33087 43666 47963 43760 43570 50947>,
+			<41853 15987 33222 43759 47130 43751 43577 50697>,
+			<41263 16376 33173 43718 47602 43670 43579 49503>,
+			<42904 16145 33183 43559 48866 43674 43579 50856>,
+			<42058 15543 33257 43313 47326 43664 43994 51104>,
+			<47652 15573 33214 42336 41919 43716 45031 50181>,
+			<47254 15760 32774 47854 41975 43719 44905 50334>,
+			<47427 12947 32811 42307 41914 43719 44978 50721>,
+			<48957 13263 32831 42199 41777 43719 43504 49549>,
+			<48623 12326 32865 42222 41119 43718 43129 49576>,
+			<45656 12574 33192 42352 41210 43713 43476 49464>,
+			<45245 13834 32976 47687 41196 43713 44793 49501>,
+			<45513 14161 32968 47714 41132 43718 43331 49435>,
+			<47035 13682 32986 47768 41794 43738 43116 49621>,
+			<46299  3001 32780 47692 41445 43728 43037 50616>,
+			<46532  2216 32855 48003 42610 43743 43021 55738>,
+			<35766  2306 33037 47884 48090 43713 43202 55029>,
+			<34912  4057 33124 47963 48182 43713 43196 11457>,
+			<36573  3528 34768 41839 36598 43753 43935 15406>,
+			<35983  1015 34644 43082 33289 43655 43549  2911>,
+			<36282   225 34228 43555 35807 43657 43740 13762>;
+	};
+
+	qcom,bp-c-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 35713 43533 42854 43686 43740 58470>,
+			<43661 53556 35433 43557 42989 43699 43734 59267>,
+			<43664 54518 35387 43563 42926 43662 43562 59135>,
+			<43748 10753 35528 43736 42603 43672 43561 57641>,
+			<43723 10460 35485 43721 42539 43753 43567 57373>,
+			<43554 11897 46404 43756 42659 43718 43553 58261>,
+			<43625 11665 46340 43661 41428 43538 43579 60704>,
+			<43918  8447 46434 43711 41387 43982 43571 60589>,
+			<43783 10183 46336 43694 41015 43442 43531 61136>,
+			<43255 14983 46394 43688 41822 44783 43522 59466>,
+			<43029 14959 46578 43688 41738 44688 43575 60224>,
+			<43422 14916 46572 43688 41841 44668 43569 60206>,
+			<44644 15297 46473 43154 41827 43968 43898 59625>,
+			<44246 14545 46519 41863 44885 43565 44059 61155>,
+			<41603 14603 46465 41969 44264 43555 44443 59728>,
+			<41853 15908 46160 41731 44193 43564 44152 59493>,
+			<41263 16302 46146 41855 44208 43566 44248 60287>,
+			<42904 16321 46147 41128 44185 43560 44175 60369>,
+			<42058 16244 46195 41167 44231 43733 44196 60193>,
+			<47652 15553 46086 40980 44460 43732 44897 60252>,
+			<47254 15805 46122 41038 41679 43732 44945 59515>,
+			<47427 15733 46090 41394 40998 43733 44919 60971>,
+			<48957 12885 46209 41392 41024 43729 44372 61171>,
+			<48623 12311 46929 41005 44104 43732 44202 38362>,
+			<45656 13978 46956 40966 44239 43562 44805 38105>,
+			<45245 14211 46877 41087 44138 43562 44908 37920>,
+			<45513 13328 46951 41832 44210 43563 43332 38848>,
+			<47035  2810 46915 41197 44171 43733 44773 38140>,
+			<46299  2877 46940 41060 44251 43735 44757 38162>,
+			<46532  2102 46967 41028 44132 43734 44699 60127>,
+			<35766  3788 46899 41229 44332 43728 44696 59634>,
+			<34912  3220 46902 42649 41815 43731 43281 60675>,
+			<36573   648 46929 42683 47850 43729 43008 63899>,
+			<35983   852 46174 41925 48379 43729 43882 63418>,
+			<36282    91 35476 44681 48555 43767 43633 63337>;
+	};
+
+	qcom,bp-c-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 47424 44718 44638 43713 43932 32945>,
+			<43661 53538 48772 44779 44557 43738 43859 33766>,
+			<43664 54419 48879 44799 44754 43736 43239 33357>,
+			<43748 10960 48893 44745 44780 43743 43058 33321>,
+			<43723 10399 48841 44742 44734 43730 43123 33420>,
+			<43554 11817 48837 44760 43283 43733 43414 36316>,
+			<43625 11341 48837 44739 43460 43565 43472 35895>,
+			<43918  8362 48820 43351 43306 43579 43101 36612>,
+			<43783 10149 47437 44558 43115 43569 44623 36431>,
+			<43255  9576 47361 44796 43126 43534 44740 36530>,
+			<43029 15066 47384 44779 43219 43530 44973 35269>,
+			<43422 14907 47362 44791 43040 43575 45000 35300>,
+			<44644 14937 47581 44976 44675 43572 44817 36477>,
+			<44246 14518 47607 44832 44646 43575 44139 36825>,
+			<41603 14829 47612 44851 44981 43572 44427 36804>,
+			<41853 16000 47591 44205 45009 43571 44316 36727>,
+			<41263 15902 47491 44160 45030 43581 41713 36840>,
+			<42904 16260 47534 44170 44974 43580 44315 36600>,
+			<42058 16157 47218 44180 44627 43577 44433 35157>,
+			<47652 15605 47200 44244 44964 43557 44078 36539>,
+			<47254 15746 47208 44152 44842 43559 44834 36406>,
+			<47427 12979 47130 44475 44094 43559 44649 36707>,
+			<48957 13282 47165 44477 44383 43578 44742 35937>,
+			<48623 12384 47311 44075 41502 43576 44177 36037>,
+			<45656 13846 47311 44871 44570 43582 45041 35617>,
+			<45245 14151 47307 44871 44732 43582 45041 35757>,
+			<45513 13703 47346 44887 43346 43582 45009 35411>,
+			<47035  2658 47334 44223 44770 43583 44928 35778>,
+			<46299  2207 47252 44214 44592 43583 44597 35653>,
+			<46532  2530 47263 44173 44660 43582 44756 35019>,
+			<35766  4021 47258 44247 45002 43582 44552 35223>,
+			<34912  3496 47294 44145 44204 43582 44556 36572>,
+			<36573   591 47320 44427 41595 43577 43373 33328>,
+			<35983     1 47539 44668 42550 43557 43855 34343>,
+			<36282   474 48838 44588 41374 43731 43829 34533>;
+	};
+
+	qcom,bp-c-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 42133 43465 43515 43567 43802 48586>,
+			<43661 53744 42121 43460 43454 43553 43412 48219>,
+			<43664 55132 42175 43482 43103 43556 44718 48145>,
+			<43748 10895 42157 43480 43135 43579 44651 48173>,
+			<43723 11109 42835 43483 43036 43582 45019 48382>,
+			<43554 11961 42826 43463 43222 43571 44088 48990>,
+			<43625 11485 42863 43464 43157 43530 44543 49119>,
+			<43918  9018 42756 43395 43194 43522 44238 48736>,
+			<43783  9743 42793 43101 43187 43527 45015 48840>,
+			<43255  9712 42945 43106 43190 43548 44988 47445>,
+			<43029 15030 42959 43052 43868 43542 44978 47404>,
+			<43422 15083 42993 43063 43842 43551 44818 47400>,
+			<44644 14899 42987 43429 43500 43549 44559 49054>,
+			<44246 15214 42905 43400 43517 43550 44858 49031>,
+			<41603 14415 42891 43470 43319 43536 44101 48933>,
+			<41853 14691 42919 43309 43271 43546 44465 48897>,
+			<41263 16065 42587 43476 43270 43547 44430 49115>,
+			<42904 15940 42619 43313 43465 43524 44328 49077>,
+			<42058 16174 42503 43282 43508 43522 44154 49083>,
+			<47652 15504 42537 43328 43475 43529 44913 49043>,
+			<47254 15804 42712 44723 43377 43528 44652 48924>,
+			<47427 12938 42697 44686 44753 43529 43356 48381>,
+			<48957 13252 42721 44711 44636 43533 43314 48188>,
+			<48623 12731 42730 43320 44638 43526 43323 48981>,
+			<45656 13916 42629 43496 43009 43533 44948 47599>,
+			<45245 13475 42637 43415 43008 43520 44963 47506>,
+			<45513 13801 42637 43412 43026 43521 44561 47593>,
+			<47035  2655 42628 43490 43448 43520 44769 47365>,
+			<46299  2267 42629 43492 43471 43526 43329 48828>,
+			<46532  2349 42653 43472 43320 43524 44685 48683>,
+			<35766  4035 42723 43361 43332 43525 44756 49145>,
+			<34912  3576 42751 43382 44583 43525 44730 48304>,
+			<36573   902 42695 44672 44941 43544 44769 48514>,
+			<35983   114 42608 43313 41563 43526 43115 45139>,
+			<36282   265 42141 43253 44158 43539 43805 45990>;
+	};
+
+	qcom,bp-c-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 41227 43112 43026 43569 43403 47305>,
+			<43661 53643 41253 43118 43069 43573 44718 47282>,
+			<43664 55052 41260 43112 43052 43531 44591 47961>,
+			<43748 54633 41431 43028 43228 43528 44963 47994>,
+			<43723 11214 41438 43024 43212 43534 44833 47879>,
+			<43554 10499 41423 43013 43245 43522 44252 48070>,
+			<43625 11454 41464 43016 43189 43526 44539 48063>,
+			<43918  9115 41365 43047 43842 43544 44300 47627>,
+			<43783  9955 41355 43217 43878 43551 44289 47845>,
+			<43255  9634 41377 43213 43781 43627 44387 42320>,
+			<43029  9585 41387 43196 43824 43616 44109 42287>,
+			<43422 15021 41055 43860 43825 43619 44105 42434>,
+			<44644 15092 41029 43230 43025 43631 44641 47702>,
+			<44246 15150 41034 43200 43033 43625 44918 47734>,
+			<41603 14337 41086 43203 43089 43616 44202 48056>,
+			<41853 14628 41064 43218 43402 43627 44887 48025>,
+			<41263 16022 40975 43209 43396 43625 44811 48045>,
+			<42904 15995 41005 43042 43027 43536 44082 47625>,
+			<42058 16346 41176 43022 43119 43551 44900 47636>,
+			<47652 15492 41162 43114 43434 43524 44571 48033>,
+			<47254 15803 41188 43105 43481 43524 43279 47915>,
+			<47427 12943 41108 43121 43378 43546 43519 47937>,
+			<48957 13265 41093 43122 43333 43545 43501 47966>,
+			<48623 12682 41097 43219 43300 43538 43458 48045>,
+			<45656 13904 41138 43190 43157 43541 44746 42470>,
+			<45245 13484 41150 43187 43232 43624 44726 42491>,
+			<45513 13806 41145 43166 43254 43627 44768 42451>,
+			<47035  2647 41139 43225 43044 43626 44548 42323>,
+			<46299  2257 41096 43055 43125 43540 44738 47861>,
+			<46532  2367 41102 43042 43407 43541 44686 47621>,
+			<35766  4054 41088 43060 43320 43543 43359 48021>,
+			<34912  3528 41112 43108 43329 43537 44681 47997>,
+			<36573   914 41108 43094 44581 43626 44686 47213>,
+			<35983   117 40995 43438 44225 43624 43457 48705>,
+			<36282   263 41340 43829 44176 43645 43807 48659>;
+	};
+
+	qcom,bp-d-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    39    58    78    97>,
+			<  136   195   292   429   605>,
+			<  703   820  1230  1660  2089>,
+			< 2519  2949  3378  3808  4238>,
+			< 4668  5097  5527  5957  6386>,
+			< 6679  7011  7441  7793  8046>,
+			< 8476  8906  9335  9765 10000>;
+		qcom,ocv = <31073 31787 32126 32450 32757>,
+			<33307 33966 34776 35568 36347>,
+			<36629 36779 36885 37084 37355>,
+			<37558 37757 37937 38107 38291>,
+			<38507 38759 39063 39479 39993>,
+			<40313 40635 41062 41430 41705>,
+			<42182 42666 43143 43619 43880>;
+	};
+
+	qcom,bp-d-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53660 64259 21845 21845 43689 43705 21845>,
+			<43661 55283 63747 21845 21845 43688 43685 21845>,
+			<43664 54516 65027 21845 21845 43691 43707 21845>,
+			<43748 54781 65312 21845 21845 43691 43711 21845>,
+			<43723 10979 64671 21845 21845 43690 43697 21845>,
+			<43554 10413 64559 21845 21845 43690 43650 21845>,
+			<43625 11995 65471 21845 21845 43690 43768 21845>,
+			<43918 11772 65193 21845 21845 43690 43556 21845>,
+			<43783  9046 63525 21845 12654 43690 43541 21845>,
+			<43255  9875 64334 21845 62536 43690 43642 21845>,
+			<43029 10122 64245 21845 64090 43690 43632 21845>,
+			<43422 10052 58432 21845 61360 43690 43646 21845>,
+			<44644  9577 58479 21845 60678 43690 43941 21845>,
+			<44246 14944 58905 21845 37937 43690 43613 21845>,
+			<41603 15156 57646 21845 38947 43690 43936 21845>,
+			<41853 14584 57594 30648 33702 43691 43917 21845>,
+			<41263 14427 60725 27562 36567 43691 43908 21845>,
+			<42904 14628 60593  3502 35555 43691 44003 21845>,
+			<42058 16013 60942  9504 46887 43691 44024 21845>,
+			<47652 15979 59707 54774 45349 43691 44020 21845>,
+			<47254 16375 59901 55359 45899 43691 43992 21845>,
+			<47427 16213 59745 52773 45785 43691 43987 21845>,
+			<48957 15390 59604 61929 48535 43691 43813 21845>,
+			<48623 15678 59596 61556 48189 43691 43885 21845>,
+			<45656 12909 60290 61479 48571 43691 43146 21845>,
+			<45245 13157 59995 61550 45702 43691 43256 21845>,
+			<45513 12699 59988 63155 45060 43691 43042 21845>,
+			<47035 14233 60017 52167 46878 43691 43300 21845>,
+			<46299 13643 60023 49709 33362 43691 44591 21845>,
+			<46532  3038 59973 49605 33792 43691 44671 21845>,
+			<35766  2091 60209 49630 33206 43691 43171 21845>,
+			<34912  3638 60014 53309 35892 43691 43236 21845>,
+			<36573  3469 59923  8750 35237 43691 43149 21845>,
+			<35983   186 60411 14552 35339 43691 43993 21845>,
+			<36282   379 60263 15528 46403 43691 43599 21845>;
+	};
+
+	qcom,bp-d-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 54802 38511 21845 21845 43708 43690 21845>,
+			<43661 54507 38770 21845 21845 43685 43706 21845>,
+			<43664 54697 38133 21845 21845 43681 43700 21845>,
+			<43748 54638 38012 21845 21845 43682 43674 21845>,
+			<43723 10798 38302 21845 21845 43694 43759 21845>,
+			<43554 11093 38352 21845 21845 43690 43741 21845>,
+			<43625 11926 38099 21845 26496 43690 43594 21845>,
+			<43918 11742 38511 17769 63508 43690 43826 21845>,
+			<43783  8197 36957  6979 33067 43690 43253 21845>,
+			<43255 10134 37434 11872 46839 43691 43115 21845>,
+			<43029  9351 40418 55369 45818 43691 43080 21845>,
+			<43422  9308 40097 53114 48256 43691 43116 21845>,
+			<44644 15047 40617 51903 45701 43691 43232 21845>,
+			<44246 15336 39176 63993 47360 43691 43165 21845>,
+			<41603 15195 39341 57419 47910 43691 43195 21845>,
+			<41853 14393 40628 60164 47721 43691 43851 21845>,
+			<41263 14745 39321 38593 47752 43688 43865 21845>,
+			<42904 14701 39386 40090 47661 43688 43880 21678>,
+			<42058 16115 40618 39879 47661 43688 43805 23876>,
+			<47652 15943 39269 34621 47760 43688 43797 22748>,
+			<47254 16163 39392 32897 47752 43688 43880 17639>,
+			<47427 15509 39233 33481 47846 43688 43883 17982>,
+			<48957 15770 40653 33286 42310 43688 43143 17979>,
+			<48623 13013 39191 33379 47966 43688 43066 18219>,
+			<45656 13140 39385 33336 48818 43688 43220 17499>,
+			<45245 12787 39380 32865 48374 43688 43413 22649>,
+			<45513 14314 39185 39738 45069 43688 44835 22280>,
+			<47035 13569 39340 39696 36710 43688 43349 21845>,
+			<46299  2657 39328 38978 36513 43688 43041 21845>,
+			<46532  2853 39348 40563 35809 43688 43194 21845>,
+			<35766  2519 39310 38436 46217 43688 43221 21845>,
+			<34912  3883 38978 61153 46097 43688 43206 21845>,
+			<36573  3351 39018 58953 46669 43688 43165 21845>,
+			<35983   149 38922 64705 48475 43691 43892 21845>,
+			<36282   278 38920 61786 48986 43691 43803 21845>;
+	};
+
+	qcom,bp-d-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53322 33863 21845 21845 43708 43690 21845>,
+			<43661 55283 34269 21845 21845 43685 43690 21845>,
+			<43664 54316 34256 21845 21845 43686 43673 21845>,
+			<43748 54543 34294 21845 21845 43682 43730 21845>,
+			<43723 10782 34189 21845 21845 43695 43540 21845>,
+			<43554 10290 33841  6719 19581 43691 44006 21845>,
+			<43625 11898 34689 56657 63547 43691 43165 21845>,
+			<43918 11526 32845 61446 35202 43691 43513 21845>,
+			<43783  8312 33572 38179 48098 43691 43379 21594>,
+			<43255 10006 33686 40556 42268 43691 44774 17106>,
+			<43029  9219 33700 39137 42289 43691 43343 20084>,
+			<43422  9717 33316 34286 42425 43691 43404 19116>,
+			<44644 15062 36217 39155 42200 43691 43256 19098>,
+			<44246 15246 36132 33160 41293 43691 43188 30752>,
+			<41603 15172 33415 36549 41325 43688 43232 27956>,
+			<41853 14444 36216 46143 42557 43688 43050  5309>,
+			<41263 14786 33442 45669 42558 43688 43236  7830>,
+			<42904 14683 36160 48664 42559 43688 43197  1950>,
+			<42058 16088 36183 47657 42931 43689 43881   701>,
+			<47652 15953 33454 42987 42970 43689 43791  2362>,
+			<47254 16138 36198 42505 42912 43689 43881 13587>,
+			<47427 15403 36193 42244 42639 43689 43226 14166>,
+			<48957 15645 33414 47258 42212 43694 43127 13661>,
+			<48623 13232 33411 48814 47742 43694 43123  2532>,
+			<45656 12343 33436 48939 47339 43692 43131  3977>,
+			<45245 14050 33522 48174 48368 43701 43319   311>,
+			<45513 13314 33323 48604 46167 43721 44868  4246>,
+			<47035 13695 36319 48194 46605 43774 43038  7383>,
+			<46299  2962 36155 46822 48393 43750 43361  4642>,
+			<46532  2301 36101 46419 49096 43756 44559  4387>,
+			<35766  3748 36350 46384 48252 43678 43504  5425>,
+			<34912  3246 36279 35769 48415 43675 43440 28174>,
+			<36573   672 36322 36309 48558 43699 43048 24705>,
+			<35983   237 36172 39178 48677 43690 43998 31375>,
+			<36282   309 33509 37768 47195 43690 43585 31013>;
+	};
+
+	qcom,bp-d-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53271 35077 22500 21845 43664 43690 21845>,
+			<43661 55175 34854 31526 21845 43674 43690 21845>,
+			<43664 54513 35674  7356 21974 43651 43690 21845>,
+			<43748 54741 35833 13192 30774 43659 43549 21845>,
+			<43723 10812 35350 55025  3927 43699 43826 21845>,
+			<43554 10300 46360 57507 64861 43681 43395 21845>,
+			<43625 11863 46177 36167 35314 43689 44670 26318>,
+			<43918 11622 46227 46964 48874 43689 44183    81>,
+			<43783  8301 46261 48620 42875 43689 44663 12523>,
+			<43255 10014 46935 48002 42614 43689 43488 10129>,
+			<43029  9339 46959 47988 42924 43694 43290  8490>,
+			<43422  9513 46873 42332 42530 43694 43123  8719>,
+			<44644 15085 46992 42601 41093 43694 43235 11942>,
+			<44246 15272 47011 42578 41498 43693 43084 56599>,
+			<41603 14504 46976 41110 41773 43709 43434 50432>,
+			<41853 14414 47078 41145 44352 43743 44210 50116>,
+			<41263 14810 47081 41943 44097 43734 45020 51453>,
+			<42904 14709 47050 41679 44258 43563 44716 61813>,
+			<42058 16074 47007 41703 44806 43560 44710 64931>,
+			<47652 16266 47030 41560 44198 43560 44912 64648>,
+			<47254 15540 47094 41735 41641 43561 44444 64959>,
+			<47427 15805 47101 41149 41538 43554 44211 64920>,
+			<48957 13036 46985 41384 41127 43560 44825 62142>,
+			<48623 13062 47037 42658 41218 43734 45033 61588>,
+			<45656 12751 47060 42824 42219 43741 44812 62670>,
+			<45245 13944 47059 41996 47951 43743 45024 51312>,
+			<45513 13374 47012 42380 48566 43736 43300 52568>,
+			<47035  2737 46709 47294 47275 43721 43488 52316>,
+			<46299  3028 46710 47279 48111 43773 43420 52578>,
+			<46532  2104 46708 47987 48038 43769 43416 50102>,
+			<35766  3800 47020 47296 47747 43775 43298 49554>,
+			<34912  3273 47018 47150 47850 43768 43463 51026>,
+			<36573   767 46689 47245 42096 43751 43415 50437>,
+			<35983   245 46837 48031 41435 43757 43095 55964>,
+			<36282   289 46721 47688 41007 43753 43133 50459>;
+	};
+
+	qcom,bp-d-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 54219 48371 21845 21845 43690 43690 21845>,
+			<43661 54913 49007 21845 21845 43690 43690 21845>,
+			<43664 55252 49112 29304 21845 43709 43577 21845>,
+			<43748 54376 49035 14095 21845 43667 43187 21845>,
+			<43723 54623 48767 52307   206 43773 43306 21845>,
+			<43554 10417 48846 46060 34294 43562 44814 56827>,
+			<43625 11780 48798 41983 47583 43561 44156 58008>,
+			<43918 11634 48775 44406 42177 43741 44292 60060>,
+			<43783  8282 47486 44470 41913 43729 44378 37438>,
+			<43255 10065 47457 44045 44442 43565 44323 39292>,
+			<43029  9663 47397 44133 44300 43552 44125 39294>,
+			<43422  9473 47413 44057 44266 43554 44902 39755>,
+			<44644 15039 47405 45020 44676 43567 44643 34664>,
+			<44246 14966 47593 44942 44777 43577 44610 32807>,
+			<41603 15169 47563 44934 44714 43569 44915 33463>,
+			<41853 14364 47196 44965 43367 43530 44240 36070>,
+			<41263 14807 47547 45004 44663 43573 44377 36281>,
+			<42904 16027 47521 45021 44816 43529 44536 36227>,
+			<42058 15985 47531 45012 44861 43528 44256 35896>,
+			<47652 16185 47223 44836 44985 43530 44198 36654>,
+			<47254 15553 47208 44813 44649 43572 44186 36449>,
+			<47427 15821 47215 44816 44547 43569 44283 36566>,
+			<48957 12861 47116 44925 44985 43570 44198 36429>,
+			<48623 12445 47104 44071 44510 43581 44894 36162>,
+			<45656 13971 47315 44434 41441 43580 44690 34454>,
+			<45245 14291 47301 44332 41440 43577 43519 34545>,
+			<45513 13329 47322 44393 41915 43554 43076 32803>,
+			<47035  2764 47302 44387 44525 43560 43320 33769>,
+			<46299  2940 47308 44296 44042 43563 44707 33307>,
+			<46532  2115 47307 44504 44239 43563 44773 33501>,
+			<35766  3692 47301 44425 44179 43564 44569 33511>,
+			<34912  3072 47308 44128 44275 43555 44553 33335>,
+			<36573   557 47142 44248 44167 43556 44760 33295>,
+			<35983   201 47174 44214 44810 43582 44682 33493>,
+			<36282   450 47543 44888 45049 43581 43347 33510>;
+	};
+
+	qcom,bp-d-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53902 42383 33702 40084 43665 43923 53967>,
+			<43661 53736 42104 46522 34491 43737 43111 51998>,
+			<43664 54804 41999 45870 36264 43552 43312 65357>,
+			<43748 54412 42195 48804 34951 43572 44746 57387>,
+			<43723 54736 42235 42413 46864 43524 44978 60067>,
+			<43554 11108 42174 44291 48176 43624 44264 39592>,
+			<43625 11982 42846 44962 48039 43539 44425 35956>,
+			<43918 11739 42877 44683 42986 43582 41645 35605>,
+			<43783  8392 42815 43388 41558 43577 41494 46618>,
+			<43255 10133 42998 43291 44765 43528 41582 48436>,
+			<43029  9255 42983 43387 44704 43522 41611 48531>,
+			<43422  9677 42985 43342 43274 43522 44819 48255>,
+			<44644  9595 42892 43448 43245 43526 44856 48889>,
+			<44246 14889 42580 43435 43220 43537 44925 48820>,
+			<41603 15161 42597 43078 43065 43539 44202 47462>,
+			<41853 14528 42502 43126 43128 43539 44182 47466>,
+			<41263 14821 42507 43454 43363 43626 44203 48748>,
+			<42904 16004 42540 43516 44658 43627 44805 48298>,
+			<42058 15943 42715 43491 44561 43626 44624 49001>,
+			<47652 16141 42738 43402 43356 43543 44603 48640>,
+			<47254 15569 42653 43455 43498 43551 44556 47459>,
+			<47427 15839 42638 43400 43079 43524 44959 47559>,
+			<48957 12811 42685 43405 43454 43524 45035 47399>,
+			<48623 12432 42680 43295 44608 43547 44954 48979>,
+			<45656 13956 42687 44775 44102 43525 43423 45666>,
+			<45245 14287 42672 44598 44093 43520 43101 45599>,
+			<45513 13322 42676 44665 44576 43575 43479 48209>,
+			<47035  2789 42632 44678 43358 43580 43488 49000>,
+			<46299  2923 42624 43346 43479 43581 43321 49037>,
+			<46532  2169 42654 43380 43414 43571 43329 48754>,
+			<35766  3588 42746 43317 43439 43574 44688 48861>,
+			<34912  3130 42739 43511 43091 43531 44744 48874>,
+			<36573   710 42691 43516 43085 43533 44658 48875>,
+			<35983   146 42536 43505 43109 43525 44807 48839>,
+			<36282   390 42533 43470 43114 43545 44199 48653>;
+	};
+
+	qcom,bp-d-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53934 41328 47651 35472 43932 43196 60132>,
+			<43661 53365 41244 42846 46743 43953 43491 37497>,
+			<43664 55019 41231 42697 45215 43943 43343 40560>,
+			<43748 55101 41278 40981 45727 43946 44756 39496>,
+			<43723 54389 41257 41911 48354 43614 44987 34720>,
+			<43554 11165 41423 44189 47224 43639 44211 35992>,
+			<43625 11944 41448 43351 42398 43626 44419 46439>,
+			<43918 11651 41395 43422 42669 43530 41659 45354>,
+			<43783  8320 41054 43083 41872 43529 41489 45735>,
+			<43255  9819 41060 43115 44692 43524 41570 47211>,
+			<43029  9361 40983 43107 43398 43544 41477 47872>,
+			<43422  9631 40985 43452 43428 43525 44063 47991>,
+			<44644  9482 41010 43160 43851 43541 45010 42279>,
+			<44246 15096 41173 43185 43149 43622 44632 42296>,
+			<41603 15299 41160 43239 43258 43646 44074 42341>,
+			<41853 14485 41197 43149 43221 43623 44891 42346>,
+			<41263 14734 41118 43166 43452 43621 45028 47847>,
+			<42904 16052 41102 43237 44787 43647 44764 47921>,
+			<42058 15936 41146 43158 44773 43644 43360 48091>,
+			<47652 16142 41812 43162 43509 43643 43390 47818>,
+			<47254 15575 41819 43258 43023 43622 44665 42269>,
+			<47427 15824 41807 43263 43263 43628 44839 42443>,
+			<48957 12802 41840 43210 43051 43626 44839 42297>,
+			<48623 12437 41851 43116 44697 43541 44622 47879>,
+			<45656 13954 41850 43477 44990 43536 43518 47556>,
+			<45245 14326 41850 43275 44668 43545 43395 47609>,
+			<45513 13374 41854 43278 43511 43523 43373 47951>,
+			<47035  2796 41841 43314 43221 43523 44984 48063>,
+			<46299  2834 41800 43394 43223 43535 44789 47662>,
+			<46532  2144 41795 43119 43051 43529 43365 47770>,
+			<35766  3599 41811 43058 43153 43524 44783 42340>,
+			<34912  3106 41135 43253 43136 43545 44751 42285>,
+			<36573   715 41150 43161 43137 43542 44755 42441>,
+			<35983   130 41090 43199 43158 43616 44591 42441>,
+			<36282   434 41112 43172 43237 43642 44591 42452>;
+	};
+};

qcom/qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi

@@ -0,0 +1,557 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+qcom,qbg-battery-profile-alium-860-89032-0000-3600mAh {
+	qcom,battery-type = "ALIUM_860_89032_0000_3600MAH";
+	qcom,batt-id-kohm = <107>;
+	qcom,capacity = <3588>;
+	qcom,max-voltage-uv = <4350000>;
+	qcom,fastchg-current-ma = <3600>;
+	qcom,checksum = <4563678>; /*@5, 0.005V, 10% */
+	qcom,soh-range = <0 100>;
+	/* Nominal_Capacity in mAh. 0: fresh cell, 1:aged cell */
+	qcom,battery-capacity = <3408 2691>;
+	/* SOC delta (in percent) dropped from EOC SOC to enable recharge */
+	qcom,recharge-soc-delta =<5>;
+	/* vfloat delta (in mV) dropped from regular vfloat in recharge */
+	qcom,recharge-vflt-delta =<50>;
+	/* termination current (in mA) in recharge */
+	qcom,recharge-iterm-ma = <300>;
+	qcom,bp-c-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    19    39    58    78>,
+			<   97   136   214   312   449>,
+			<  605   722  1093  1640  2617>,
+			< 3886  5019  5683  6210  6621>,
+			< 7031  7343  7519  7871  8027>,
+			< 8554  9101  9628 10000>;
+		qcom,ocv = <30000 30863 31659 32364 32956>,
+			<33410 34016 34824 35559 36295>,
+			<36867 37001 37083 37388 37894>,
+			<38164 38590 38975 39497 39791>,
+			<40073 40586 40837 41110 41228>,
+			<41772 42360 42953 43365>;
+	};
+
+	qcom,bp-c-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>,
+			<43705 53789 44184 43942 44013 43604 41068 42903>,
+			<43661 53585 44179 43946 44012 43945 41181 42931>,
+			<43664 54350 44180 43614 44015 43949 41137 42589>,
+			<43748 11251 44267 43587 44014 43943 41746 42623>,
+			<43723 10728 44270 43639 44009 43961 41976 42526>,
+			<43554 12062 44268 43629 44010 43957 41534 42717>,
+			<43644  8826 44271 43523 43933 43920 44406 42687>,
+			<43922  8449 44185 43570 43907 43976 41611 41327>,
+			<43883  9254 44179 43730 43919 43808 44367 41425>,
+			<43255 14867 44167 43672 44001 44025 45053 41445>,
+			<43128 15244 44168 43672 44029 44024 45048 41451>,
+			<44783 15158 44173 43774 44013 43988 44048 41467>,
+			<44226 14421 44161 43540 44013 43793 41113 41326>,
+			<41107 15967 44173 43625 43776 43793 41789 41295>,
+			<42372 15526 44884 43584 43856 43898 41322 41282>,
+			<47409 15831 44867 43908 43900 43066 47981 41317>,
+			<48281 12906 44874 44012 43875 43131 48704 41247>,
+			<45800 13155 44916 43995 43899 43076 48598 41287>,
+			<45943 12500 44865 43789 43856 43091 45767 42694>,
+			<45533 12745 44884 43866 43224 43448 45801 42993>,
+			<46597 13859 44193 43189 43133 43499 45732 42112>,
+			<47093 14086 44221 43184 43128 43496 48592 42215>,
+			<46101  2729 44165 43176 43029 43392 48814 42199>,
+			<46577  2616 44188 43179 43085 43392 47122 42001>,
+			<35776  2202 44260 43180 43334 43496 42250 42316>,
+			<35111  3788 44259 43191 44671 43496 42897 48054>,
+			<36662  3128 44267 43146 44800 43421 41436 47272>,
+			<36282   748 44268 43594 44960 41594 44901 47858>;
+	};
+
+	qcom,bp-c-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>,
+			<43705 53789 44184 43942 44013 43604 41068 42903>,
+			<43661 53585 44179 43946 44012 43945 41181 42931>,
+			<43664 54350 44180 43614 44015 43949 41137 42589>,
+			<43748 11251 44267 43587 44014 43943 41746 42623>,
+			<43723 10728 44270 43639 44009 43961 41976 42526>,
+			<43554 12062 44268 43629 44010 43957 41534 42717>,
+			<43644  8826 44271 43523 43933 43920 44406 42687>,
+			<43922  8449 44185 43570 43907 43976 41611 41327>,
+			<43883  9254 44179 43730 43919 43808 44367 41425>,
+			<43255 14867 44167 43672 44001 44025 45053 41445>,
+			<43128 15244 44168 43672 44029 44024 45048 41451>,
+			<44783 15158 44173 43774 44013 43988 44048 41467>,
+			<44226 14421 44161 43540 44013 43793 41113 41326>,
+			<41107 15967 44173 43625 43776 43793 41789 41295>,
+			<42372 15526 44884 43584 43856 43898 41322 41282>,
+			<47409 15831 44867 43908 43900 43066 47981 41317>,
+			<48281 12906 44874 44012 43875 43131 48704 41247>,
+			<45800 13155 44916 43995 43899 43076 48598 41287>,
+			<45943 12500 44865 43789 43856 43091 45767 42694>,
+			<45533 12745 44884 43866 43224 43448 45801 42993>,
+			<46597 13859 44193 43189 43133 43499 45732 42112>,
+			<47093 14086 44221 43184 43128 43496 48592 42215>,
+			<46101  2729 44165 43176 43029 43392 48814 42199>,
+			<46577  2616 44188 43179 43085 43392 47122 42001>,
+			<35776  2202 44260 43180 43334 43496 42250 42316>,
+			<35111  3788 44259 43191 44671 43496 42897 48054>,
+			<36662  3128 44267 43146 44800 43421 41436 47272>,
+			<36282   748 44268 43594 44960 41594 44901 47858>;
+	};
+
+	qcom,bp-c-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>,
+			<43705 53789 44184 43942 44013 43604 41068 42903>,
+			<43661 53585 44179 43946 44012 43945 41181 42931>,
+			<43664 54350 44180 43614 44015 43949 41137 42589>,
+			<43748 11251 44267 43587 44014 43943 41746 42623>,
+			<43723 10728 44270 43639 44009 43961 41976 42526>,
+			<43554 12062 44268 43629 44010 43957 41534 42717>,
+			<43644  8826 44271 43523 43933 43920 44406 42687>,
+			<43922  8449 44185 43570 43907 43976 41611 41327>,
+			<43883  9254 44179 43730 43919 43808 44367 41425>,
+			<43255 14867 44167 43672 44001 44025 45053 41445>,
+			<43128 15244 44168 43672 44029 44024 45048 41451>,
+			<44783 15158 44173 43774 44013 43988 44048 41467>,
+			<44226 14421 44161 43540 44013 43793 41113 41326>,
+			<41107 15967 44173 43625 43776 43793 41789 41295>,
+			<42372 15526 44884 43584 43856 43898 41322 41282>,
+			<47409 15831 44867 43908 43900 43066 47981 41317>,
+			<48281 12906 44874 44012 43875 43131 48704 41247>,
+			<45800 13155 44916 43995 43899 43076 48598 41287>,
+			<45943 12500 44865 43789 43856 43091 45767 42694>,
+			<45533 12745 44884 43866 43224 43448 45801 42993>,
+			<46597 13859 44193 43189 43133 43499 45732 42112>,
+			<47093 14086 44221 43184 43128 43496 48592 42215>,
+			<46101  2729 44165 43176 43029 43392 48814 42199>,
+			<46577  2616 44188 43179 43085 43392 47122 42001>,
+			<35776  2202 44260 43180 43334 43496 42250 42316>,
+			<35111  3788 44259 43191 44671 43496 42897 48054>,
+			<36662  3128 44267 43146 44800 43421 41436 47272>,
+			<36282   748 44268 43594 44960 41594 44901 47858>;
+	};
+
+	qcom,bp-c-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 45033 43737 43603 43866 41563 41506>,
+			<43705 53766 44949 43738 43615 43178 41536 41690>,
+			<43661 53577 44945 43718 43611 43194 41551 41715>,
+			<43664 54292 44957 43715 43591 43147 41544 41705>,
+			<43748 11150 44953 43724 43587 43160 41547 41607>,
+			<43723 10326 44933 43721 43599 43246 41545 41661>,
+			<43554 12232 44930 43764 43636 43202 41536 44378>,
+			<43644  8751 44982 43774 43641 43036 41903 44295>,
+			<43922  8649 44987 43750 43619 43445 41931 44506>,
+			<43883  9454 44972 43751 43542 43300 41165 44527>,
+			<43255 15062 44630 43675 43626 43382 41676 44476>,
+			<43128 14925 44628 43679 43624 44718 41718 44452>,
+			<44783 15341 44627 43769 43549 43379 41249 44470>,
+			<44226 14371 44627 43637 43736 44651 37910 44528>,
+			<41107 15906 44613 43608 43735 44644 60857 44534>,
+			<42372 16330 44671 43960 43543 44544 57836 44350>,
+			<47409 15371 44642 43907 43608 44553 57110 44399>,
+			<48281 12899 44650 43963 43583 44742 57671 44522>,
+			<45800 12525 44571 43615 43579 44729 36578 44455>,
+			<45943 12714 44546 43958 43523 43379 36745 44437>,
+			<45533 13989 44546 44029 43592 43367 33164 44314>,
+			<46597 14183 44546 44013 43587 43369 36861 44292>,
+			<47093 13706 44550 43911 43595 43295 45396 44349>,
+			<46101  2616 44574 44008 43586 43268 45463 44309>,
+			<46577  2653 44562 44016 43607 43290 46905 44379>,
+			<35776  2120 44573 44021 44000 43285 45839 41703>,
+			<35111  4019 44651 44023 43872 43336 48949 41545>,
+			<36662  3523 44564 43604 43218 44073 42138 41879>,
+			<36282   937 44666 43576 43065 43488 41623 41555>;
+	};
+
+	qcom,bp-c-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 43332 43718 43763 43378 46676 44985>,
+			<43705 53797 43329 43712 43763 44712 46710 44963>,
+			<43661 53505 43341 43725 43762 44672 46649 44629>,
+			<43664 54470 43342 43726 43773 44792 46721 44636>,
+			<43748 10774 43339 43720 43773 44755 45338 44614>,
+			<43723 10280 43380 43722 43772 44597 45443 44617>,
+			<43554 11850 43378 43761 43775 44623 45199 44665>,
+			<43644  8866 43367 43774 43769 45042 46057 44573>,
+			<43922  8269 43368 43770 43770 44818 46020 44554>,
+			<43883 10093 43283 43769 43746 44874 46300 44581>,
+			<43255 15017 43289 43749 43755 44267 35516 44753>,
+			<43128 14883 43288 43668 43748 44088 48866 44766>,
+			<44783 14961 43291 43763 43757 44915 36601 44589>,
+			<44226 14502 43268 43733 43770 44193 64491 44571>,
+			<41107 16044 43276 43565 43766 44884 63795 44561>,
+			<42372 16318 43312 43571 43720 44857 63606 44643>,
+			<47409 15380 43301 43577 43582 45042 33472 44609>,
+			<48281 12949 43298 43570 43545 44804 61244 44962>,
+			<45800 12515 43307 43558 43724 44812 58642 44599>,
+			<45943 12741 43472 43562 43722 44959 35952 44579>,
+			<45533 13859 43474 43533 43735 45034 39071 44647>,
+			<46597 13344 43472 43561 43728 44966 35574 44546>,
+			<47093 13615 43478 43743 43741 44634 45953 44594>,
+			<46101  2620 43473 43576 43740 44978 35216 44575>,
+			<46577  2982 43473 43568 43740 44935 35895 44567>,
+			<35776  2438 43475 43531 43560 44929 36356 44645>,
+			<35111  4050 43474 43532 43547 44954 35561 44975>,
+			<36662  3427 43473 43582 43603 45036 45867 44945>,
+			<36282   975 43472 43723 43960 44931 42369 44980>;
+	};
+
+	qcom,bp-c-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 43505 43765 43675 44739 58612 44734>,
+			<43705 53966 43507 43767 43672 44606 58146 44709>,
+			<43661 53746 43517 43761 43672 44650 61420 44704>,
+			<43664 55133 43519 43763 43672 44615 60222 44716>,
+			<43748 10886 43513 43773 43673 44976 38086 44715>,
+			<43723 11080 43515 43775 43673 45039 37222 43351>,
+			<43554 11924 43495 43771 43673 44862 37542 43358>,
+			<43644 11736 43490 43751 43673 44202 40166 43341>,
+			<43922  8444 43497 43744 43674 44258 38461 43382>,
+			<43883 10129 43413 43756 43674 44094 38631 43384>,
+			<43255  9512 43414 43755 43648 44120 60617 43368>,
+			<43128 14976 43409 43666 43662 44472 40898 43289>,
+			<44783 15069 43408 43758 43678 44051 60003 43364>,
+			<44226 15113 43411 43750 43750 44093 59439 43332>,
+			<41107 14650 43420 43774 43770 44224 65165 43346>,
+			<42372 15936 43397 43763 43748 44800 38880 43357>,
+			<47409 15366 43394 43713 43721 44903 39733 44726>,
+			<48281 12945 43406 43721 43557 44205 40872 44688>,
+			<45800 12433 43402 43761 43714 44270 60945 44713>,
+			<45943 12572 43446 43774 43753 44908 40456 43385>,
+			<45533 13949 43440 43727 43723 44854 40753 44715>,
+			<46597 13367 43440 43749 43771 44922 35253 43377>,
+			<47093 13773 43441 43748 43750 44923 34973 43389>,
+			<46101  2603 43440 43764 43769 44811 34575 43334>,
+			<46577  2981 43443 43722 43775 44852 33813 43354>,
+			<35776  2543 43452 43720 43767 44850 33075 43346>,
+			<35111  3848 43455 43715 43730 44802 33637 44721>,
+			<36662  3422 43454 43765 43530 44914 34945 44700>,
+			<36282   808 43449 43712 43765 44073 36789 43345>;
+	};
+
+	qcom,bp-c-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 43415 43760 43651 44707 65307 43336>,
+			<43705 53993 43409 43762 43648 44776 63897 43381>,
+			<43661 53693 43408 43772 43649 44759 64131 43377>,
+			<43664 55092 43410 43769 43654 44560 58990 43378>,
+			<43748 54635 43421 43771 43654 44637 58265 43390>,
+			<43723 11226 43420 43749 43655 44953 61196 43387>,
+			<43554 10599 43417 43745 43653 44810 38392 43361>,
+			<43644 11680 43397 43759 43674 44167 36864 43370>,
+			<43922  9049 43398 43755 43674 44072 38762 43293>,
+			<43883  9841 43395 43668 43652 44132 60565 43268>,
+			<43255  9603 43405 43666 43651 44505 64189 43317>,
+			<43128  9539 43404 43654 43701 44304 38320 43299>,
+			<44783 14995 43404 43676 43678 44532 37230 43267>,
+			<44226 15345 43404 43671 43745 44471 59557 43373>,
+			<41107 14817 43401 43754 43749 44115 57646 43366>,
+			<42372 15972 43447 43745 43759 44219 61314 43360>,
+			<47409 15366 43452 43774 43764 44823 32791 43328>,
+			<48281 13038 43451 43772 43733 44214 39831 44718>,
+			<45800 12516 43428 43756 43760 44284 37974 43367>,
+			<45943 12665 43425 43759 43668 44209 38319 43270>,
+			<45533 14270 43427 43748 43769 44874 38717 43360>,
+			<46597 13355 43427 43744 43753 44871 37475 43294>,
+			<47093 13725 43427 43745 43755 44864 36926 43294>,
+			<46101  2768 43437 43770 43744 44870 36983 43370>,
+			<46577  2994 43436 43770 43750 44874 37629 43368>,
+			<35776  2559 43438 43774 43775 44905 40470 43364>,
+			<35111  3858 43435 43773 43739 44822 33978 43329>,
+			<36662   687 43093 43748 43582 44877 36384 44712>,
+			<36282   813 43088 43768 43723 44316 35572 43367>;
+	};
+
+	qcom,bp-d-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    19    39    58    78>,
+			<   97   136   214   312   449>,
+			<  605   722  1093  1640  2617>,
+			< 3886  5019  5683  6210  6621>,
+			< 7031  7343  7519  7871  8027>,
+			< 8554  9101  9628 10000>;
+		qcom,ocv = <28020 29554 30909 31906 32434>,
+			<32777 33252 34082 34943 35817>,
+			<36507 36768 36886 37109 37543>,
+			<37954 38397 38781 39283 39670>,
+			<39927 40519 40770 40989 41101>,
+			<41666 42257 42876 43360>;
+	};
+
+	qcom,bp-d-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 55845 41409 21845 21845 43694 43705 21845>,
+			<43705 57283 41409 21845 21845 43695 43649 21845>,
+			<43661 53814 41409 21845 21845 43692 43774 21845>,
+			<43664 53319 41409 21845 21845 43692 43553 21845>,
+			<43748 54810 41423 21845 21845 43693 43641 21845>,
+			<43723 54402 41459 21845 21845 43692 43908 21845>,
+			<43554 10764 41360   386 63661 43692 43862 21845>,
+			<43644 11815 41045 55488 35741 43693 43379 30577>,
+			<43922 11521 40982 63723 47555 43692 44886  2459>,
+			<43883  8395 40961 40248 41338 43693 41911 56339>,
+			<43255  9955 41091 36084 44402 43682 42515 62276>,
+			<43128 10223 41131 35399 44101 43683 42773 64460>,
+			<44783  9704 41823 46673 41699 43683 42089 59385>,
+			<44226 14850 41143 48413 44295 43683 41448 60636>,
+			<41107 14470 41122 47597 44870 43683 41937 38251>,
+			<42372 14606 41812 42195 44615 43680 41542 37878>,
+			<47409 15985 41854 41448 44604 43680 41607 40513>,
+			<48281 16148 41794 41828 44585 43681 41726 38979>,
+			<45800 15381 41806 41905 44594 43686 41969 39793>,
+			<45943 15731 41798 41478 44633 43686 41207 39887>,
+			<45533 13236 41801 41648 44856 43687 41125 39843>,
+			<46597 12457 41803 44366 44825 43684 41587 39528>,
+			<47093 12368 41847 44357 44282 43684 41945 39914>,
+			<46101 13694 41835 41903 42479 43707 48631 37286>,
+			<46577  2623 41749 41916 47842 43707 45706 38580>,
+			<35776  2973 41829 41705 42094 43684 44421 36912>,
+			<35111  2462 41744 42345 41789 43705 41209 38706>,
+			<36662  3291 41803 47453 41798 43680 44262 61324>,
+			<36282   824 41130 49041 41026 43690 43690 57741>;
+	};
+
+	qcom,bp-d-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 50529 41780 21845 21845 43695 43710 21845>,
+			<43705 56941 41780 21845 21845 43686 43649 21845>,
+			<43661 53781 41780 21845 21845 43707 43726 21845>,
+			<43664 53705 41786 21845 21845 43705 43639 21845>,
+			<43748 55191 41926 21845 21845 43705 43783 21845>,
+			<43723 54284 41887 26259 21845 43706 43084 21845>,
+			<43554 10827 41570 57991 33374 43683 44899 13506>,
+			<43644 11872 41693 34887 41483 43693 41148 58785>,
+			<43922  8945 41723 45501 44208 43683 42555 59581>,
+			<43883  8511 41617 48394 44812 43683 42113 38905>,
+			<43255 10081 41616 48662 45012 43683 47757 37739>,
+			<43128  9325 41620 47175 45045 43683 47861 40400>,
+			<44783 14980 41610 47875 44222 43680 42894 40088>,
+			<44226 15283 41655 42088 44658 43680 41019 39731>,
+			<41107 14547 41612 40973 43366 43681 41203 33074>,
+			<42372 14666 41636 44169 43504 43685 41934 36413>,
+			<47409 15952 41614 44693 43437 43711 41572 35331>,
+			<48281 15535 41661 43367 43452 43703 40975 46479>,
+			<45800 15822 41647 43281 43387 43661 42933 46164>,
+			<45943 12863 41660 43314 44773 43673 42509 46146>,
+			<45533 13183 41609 43470 44759 43714 41320 46141>,
+			<46597 12703 41656 44685 44644 43848 46238 46364>,
+			<47093 14042 41634 44693 44831 43198 35723 35713>,
+			<46101  2988 44380 43499 47654 43534 47325 32959>,
+			<46577  3026 44383 43403 47882 43724 42882 32895>,
+			<35776  2975 41639 43307 41368 43771 44987 36726>,
+			<35111  3791 41637 41594 44489 43612 47500 33289>,
+			<36662  3194 44373 44431 44116 43624 43080 33297>,
+			<36282   806 44381 43232 41661 43649 43690 33325>;
+	};
+
+	qcom,bp-d-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 50372 44353 21845 21845 43695 43710 21845>,
+			<43705 57283 44353 21845 21845 43706 43651 21845>,
+			<43661 54080 44352 21845 21845 43710 43767 21845>,
+			<43664 54960 44390 21845 21845 43705 43833 21845>,
+			<43748 55060 44326 20286 21845 43706 43351 21845>,
+			<43723 54697 44523  8575 21845 43687 44153 21845>,
+			<43554 11163 44149 45557 41969 43683 40987 59942>,
+			<43644 12268 44132 48903 44256 43683 41247 40065>,
+			<43922  8812 44055 47152 44840 43683 42691 39684>,
+			<43883  9907 44055 42216 44970 43680 42793 33116>,
+			<43255  9257 44086 41051 44639 43686 42381 36297>,
+			<43128  9715 44088 41774 44651 43687 42165 36436>,
+			<44783 14980 44069 41632 44713 43685 41084 34994>,
+			<44226 15283 44072 44620 43468 43699 41436 45364>,
+			<41107 14462 44078 43247 43096 43761 41254 48684>,
+			<42372 14663 44241 44008 43855 43946 41385 47752>,
+			<47409 16281 44235 43946 43899 43992 41413 41992>,
+			<48281 15459 44275 43985 43177 43085 48564 42109>,
+			<45800 13044 44278 43898 43217 43307 45390 42432>,
+			<45943 13097 44233 43841 43056 43487 45412 42281>,
+			<45533 12396 44287 43863 43054 43412 47092 42489>,
+			<46597 13455 44268 43144 41636 43507 46025 48762>,
+			<47093 13798 44267 43246 41974 43510 48267 48266>,
+			<46101 13662 44267 43124 44571 43041 42674 47342>,
+			<46577  2789 44264 43076 43384 43200 41381 48070>,
+			<35776  2249 44256 43229 43274 43134 47578 48041>,
+			<35111  3588 44256 43228 43437 43013 47562 47678>,
+			<36662  3472 44265 43198 43011 43114 47227 47750>,
+			<36282   980 44181 43897 43040 43100 47147 42319>;
+	};
+
+	qcom,bp-d-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 51163 44874 51317 21845 43695 43708 21845>,
+			<43705 55613 44874 64906 21845 43698 43636 21845>,
+			<43661 53829 44874 57837 21845 43679 43162 21845>,
+			<43664 54785 44874 60052 56852 43762 43376 29256>,
+			<43748 54323 44912 40533 38120 43555 44277 11699>,
+			<43723 54611 44911 35962 35922 43634 41066 62404>,
+			<43554 11097 44833 41332 41454 43823 48856 35640>,
+			<43644 12252 45045 43397 44689 43875 48244 47349>,
+			<43922  8820 45050 43053 43496 43850 48900 42268>,
+			<43883  9961 45035 43182 43056 43167 48201 42964>,
+			<43255  9333 44954 43886 43063 43045 48146 42504>,
+			<43128  9578 44955 43805 43041 43011 48180 42750>,
+			<44783 14999 44936 44013 43879 43149 47866 41069>,
+			<44226 15256 44939 43960 43990 43433 48721 41832>,
+			<41107 14462 44986 43549 43913 43510 47298 41530>,
+			<42372 16045 44973 43540 43590 44761 45578 41651>,
+			<47409 16231 44639 43630 43606 44546 48572 44353>,
+			<48281 15843 44638 43643 43966 44595 45772 44379>,
+			<45800 12823 44608 43607 44029 44757 46718 41724>,
+			<45943 13124 44608 43958 43795 44746 46866 41596>,
+			<45533 12766 44623 43926 43210 44698 46792 41787>,
+			<46597 13469 44656 43800 43394 43368 47963 41080>,
+			<47093 13805 44669 43879 43500 43321 42473 41376>,
+			<46101  2737 44662 43970 43868 43458 47973 41931>,
+			<46577  2594 44663 44024 43779 43471 47119 41903>,
+			<35776  2079 44656 44013 43987 43460 47382 41598>,
+			<35111  3666 44618 43936 44031 43298 47241 41518>,
+			<36662  3521 44662 43605 44015 43385 48696 41682>,
+			<36282   990 44665 43913 44000 44710 45581 41527>;
+	};
+
+	qcom,bp-d-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 51166 44775 47124 21845 43693 43709 21845>,
+			<43705 55768 44775 42052 21845 43629 44600 21845>,
+			<43661 53783 44775 41259 21845 43987 41550 21845>,
+			<43664 54792 44775 41501 61566 43196 42926 50758>,
+			<43748 54296 44769 44058 42233 43056 48033 45433>,
+			<43723 10915 44689 44659 41117 43444 48945 48852>,
+			<43554 11086 44717 43849 45025 44716 46210 41271>,
+			<43644 12168 43343 43548 43241 44764 35739 44523>,
+			<43922  8917 43382 43569 44012 44547 35662 44210>,
+			<43883  8515 43365 43554 43593 44988 35035 44838>,
+			<43255  9265 43372 43741 43644 45034 46786 45047>,
+			<43128  9482 43374 43566 43602 45013 46325 44832>,
+			<44783 15036 43371 43767 43558 45011 48146 44634>,
+			<44226 14943 43287 43774 43732 44830 48165 44644>,
+			<41107 14349 43282 43772 43738 44804 45963 44562>,
+			<42372 16104 43271 43737 43582 44926 36856 44609>,
+			<47409 16215 43316 43774 43564 44894 48867 44547>,
+			<48281 15831 43325 43762 43580 44861 48983 44569>,
+			<45800 13273 43320 43572 43912 45050 47025 44833>,
+			<45943 12380 43322 43549 43835 44981 45972 44217>,
+			<45533 12637 43303 43534 43950 44554 48740 45022>,
+			<46597 13549 43308 43538 43604 44773 48921 45008>,
+			<47093 13800 43311 43542 43602 44779 49021 45008>,
+			<46101  2743 43311 43552 43628 44746 47348 44985>,
+			<46577  2599 43311 43733 43551 44739 47972 44638>,
+			<35776  2152 43310 43730 43575 44582 48877 44666>,
+			<35111  4027 43310 43772 43529 44971 42101 44568>,
+			<36662  3542 43308 43769 43568 45054 42333 44546>,
+			<36282   970 43309 43761 43553 45012 47510 44568>;
+	};
+
+	qcom,bp-d-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 51194 43317 43723 21845 43904 43699 21845>,
+			<43705 55597 43317 43433 21845 43858 44606 21845>,
+			<43661 53857 43317 44608 21845 43009 41891 21845>,
+			<43664 54971 43317 44840 43003 43402 42967 48409>,
+			<43748 55122 43325 44623 41934 43470 47118 48114>,
+			<43723 54745 43308 43277 44139 43275 45814 42567>,
+			<43554 11017 43466 43944 43384 44707 35608 41661>,
+			<43644 12196 43515 43725 43983 44640 35080 45034>,
+			<43922  8933 43495 43764 43549 45017 35968 44591>,
+			<43883  8451 43501 43750 43562 44206 35810 44702>,
+			<43255  9457 43502 43745 43576 44228 46407 44779>,
+			<43128  9716 43497 43768 43647 44266 46648 44576>,
+			<44783  9572 43496 43753 43773 44229 36065 43345>,
+			<44226 14901 43498 43752 43775 44067 33852 43359>,
+			<41107 14564 43415 43754 43746 44071 39629 43337>,
+			<42372 16023 43423 43754 43735 44087 35414 44730>,
+			<47409 15530 43393 43752 43762 44272 35657 43337>,
+			<48281 15656 43404 43747 43764 44882 35074 43334>,
+			<45800 13269 43400 43721 43618 44855 46400 44762>,
+			<45943 12730 43402 43717 43614 44840 45218 44545>,
+			<45533 14004 43445 43764 43573 44629 45722 44777>,
+			<46597 13474 43446 43725 43533 44665 45641 44793>,
+			<47093 13389 43441 43715 43522 44645 45991 44796>,
+			<46101 13640 43443 43768 43735 44980 48200 44709>,
+			<46577  2762 43442 43750 43738 44948 48336 43345>,
+			<35776  2098 43452 43750 43722 44838 45237 43340>,
+			<35111  3676 43454 43746 43760 44803 45373 43379>,
+			<36662  3569 43454 43747 43774 44828 46449 43384>,
+			<36282   900 43454 43744 43768 44830 35264 43385>;
+	};
+
+	qcom,bp-d-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 51120 43482 43723 21845 43917 43696 21845>,
+			<43705 55378 43482 43228 21845 43244 44765 21845>,
+			<43661 56668 43482 43346 24109 43423 41585 21159>,
+			<43664 53659 43482 44743 41335 43294 42982 48852>,
+			<43748 55195 43456 43333 41722 43382 47309 42416>,
+			<43723 54370 43511 43098 44877 43356 45742 41469>,
+			<43554 11136 43496 43641 43414 44726 35620 44432>,
+			<43644 11793 43410 43766 43926 44646 36626 44613>,
+			<43922 11605 43423 43775 43532 44855 33761 44773>,
+			<43883  8703 43419 43758 43743 44170 35271 44717>,
+			<43255  9378 43396 43668 43561 44090 46107 44705>,
+			<43128  9610 43399 43747 43635 44034 46844 44742>,
+			<44783  9529 43399 43666 43775 44116 36331 43385>,
+			<44226 15093 43393 43676 43762 44430 39369 43384>,
+			<41107 14501 43395 43674 43745 44433 39567 43287>,
+			<42372 16024 43403 43672 43743 44489 46412 43337>,
+			<47409 16209 43442 43676 43770 44142 36065 43282>,
+			<48281 15829 43448 43667 43774 44283 36585 43286>,
+			<45800 13278 43431 43744 43535 44800 46795 44727>,
+			<45943 12724 43425 43774 43631 44998 45964 44768>,
+			<45533 14071 43424 43748 43565 44993 45928 44718>,
+			<46597 14205 43426 43768 43552 44982 45526 44707>,
+			<47093 13363 43436 43768 43552 44961 45429 44707>,
+			<46101 13675 43438 43752 43724 45001 45164 43384>,
+			<46577  2810 43438 43754 43767 45009 45137 43374>,
+			<35776  2093 43432 43755 43771 44814 35455 43292>,
+			<35111  3651 43435 43752 43745 44851 36039 43269>,
+			<36662  3552 43093 43667 43751 44276 35743 43279>,
+			<36282   954 43092 43674 43771 44148 48769 43318>;
+	};
+};

qcom/qbg-battery-profile-qrd-zwd-520mAh.dtsi

@@ -0,0 +1,642 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+qcom,qbg-battery-profile-qrd-zwd-520mAh {
+	qcom,battery-type = "QRD_ZWD_520MAH";
+	qcom,batt-id-kohm = <33>;
+	qcom,capacity = <503>;
+	qcom,battery-beta = <4250>;
+	qcom,battery-therm-kohm = <100>;
+	qcom,max-voltage-uv = <4350000>;
+	qcom,fastchg-current-ma = <1040>;
+	qcom,checksum = <4295719>; /*@5, 0.005V, 4% */
+	qcom,soh-range = <0 100>;
+	/* Nominal_Impedance in 10nohm @ SOC 50% 25C* 0:fresh cell, 1: aged cell */
+	qcom,battery-impedance = <63931000 127862000>;
+	/* Nominal_Capacity in mAh. 0: fresh cell, 1:aged cell */
+	qcom,battery-capacity = <477 377>;
+	/* SOC delta (in percent) dropped from EOC SOC to enable recharge */
+	qcom,recharge-soc-delta =<5>;
+	/* vfloat delta (in mV) dropped from regular vfloat in recharge */
+	qcom,recharge-vflt-delta =<50>;
+	/* Termination current (in mA) in recharge */
+	qcom,recharge-iterm-ma = <10>;
+
+	qcom,jeita-fcc-ranges = <0 150 156000
+				151 435 1040000
+				436 445 800000
+				446 450 650000>;
+
+	qcom,jeita-fv-ranges = <0 150 4300000
+				151 435 4350000
+				436 445 4350000
+				446 450 4350000>;
+
+	/* COOL = 15 DegC, WARM = 45 DegC */
+	qcom,jeita-soft-thresholds = <0x27c1 0x128c>;
+	/* COLD = 0 DegC, HOT = 45.1 DegC */
+	qcom,jeita-hard-thresholds = <0x3257 0x127e>;
+	/* COOL = 18 DegC, WARM = 44 DegC*/
+	qcom,jeita-soft-hys-thresholds = <0x256e 0x131c>;
+	qcom,step-jeita-hysteresis = <5 5>;
+	qcom,jeita-soft-fcc-ua = <156000 520000>;
+	qcom,jeita-soft-fv-uv = <4300000 4300000>;
+
+	qcom,bp-c-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    39    78    97   136>,
+			<  195   292   410   585   722>,
+			<  917  1347  1777  2207  2636>,
+			< 3066  3496  3925  4355  4785>,
+			< 5214  5644  6074  6503  6933>,
+			< 7363  7714  7968  8398  8828>,
+			< 9257  9687 10000>;
+		qcom,ocv = <30000 31558 32793 33239 33837>,
+			<34450 35224 35898 36621 36960>,
+			<37035 37138 37388 37663 37892>,
+			<38079 38213 38351 38505 38683>,
+			<38898 39150 39436 39808 40303>,
+			<40790 41083 41316 41735 42171>,
+			<42614 43061 43361>;
+	};
+
+	qcom,bp-c-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 46249 43823 42806 43710 43528 63481>,
+			<43661 53696 46923 43968 42940 43711 43581 61818>,
+			<43748 10968 46957 44004 42559 43708 43578 61693>,
+			<43723 10488 46871 44011 42748 43709 43559 62219>,
+			<43554 11874 46853 43917 41291 43698 43554 62183>,
+			<43625 11653 46863 43944 41443 43697 43567 64560>,
+			<43918  8326 46959 43625 41011 43659 43555 65029>,
+			<43824  9826 46947 43521 41801 43663 43571 63926>,
+			<43235  9533 46877 43554 41474 43654 43523 64121>,
+			<43128 14970 46226 43714 41666 43679 43530 58694>,
+			<43327 15254 46921 43738 41551 43673 43535 64158>,
+			<45033 15227 46855 43560 41806 43652 43548 64432>,
+			<44123 14462 46153 43581 40975 43649 43625 64304>,
+			<41525 14716 46966 43582 41354 43649 43539 64323>,
+			<41190 15933 46306 43631 42710 43662 43617 64313>,
+			<41296 16266 46933 43136 42601 43656 43916 64487>,
+			<42754 16162 46939 44544 42664 43654 43869 64483>,
+			<42495 16192 46875 44079 41436 43664 43097 64508>,
+			<48041 15555 46710 44477 41240 43669 43267 64440>,
+			<47131 15449 46679 44333 42738 43759 44588 64440>,
+			<48884 15669 46610 44354 42532 43768 45005 64069>,
+			<48294 13014 46812 41619 42535 43764 44263 64146>,
+			<48400 13256 46819 41505 42501 43714 44490 58677>,
+			<46029 12514 46783 41890 42767 43719 44399 64505>,
+			<45503 12744 46805 41837 42275 43716 44515 64740>,
+			<46697 14216 46900 41082 47831 43717 44236 62641>,
+			<46216 13396 46370 41282 47713 43738 44835 52442>,
+			<46474 13648 46400 42707 47876 43739 44653 49493>,
+			<35428  3037 35486 42605 47434 43736 43307 57045>,
+			<35030  2476 35739 42498 48155 43716 43009 55120>,
+			<36483  3592 35625 42702 45888 43770 43194  8928>,
+			<36733  3273 35768 44271 46636 43710 43939  9217>,
+			<36282  3381 35760 43042 45296 43680 43580 14429>;
+	};
+
+	qcom,bp-c-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 46249 43823 42806 43710 43528 63481>,
+			<43661 53696 46923 43968 42940 43711 43581 61818>,
+			<43748 10968 46957 44004 42559 43708 43578 61693>,
+			<43723 10488 46871 44011 42748 43709 43559 62219>,
+			<43554 11874 46853 43917 41291 43698 43554 62183>,
+			<43625 11653 46863 43944 41443 43697 43567 64560>,
+			<43918  8326 46959 43625 41011 43659 43555 65029>,
+			<43824  9826 46947 43521 41801 43663 43571 63926>,
+			<43235  9533 46877 43554 41474 43654 43523 64121>,
+			<43128 14970 46226 43714 41666 43679 43530 58694>,
+			<43327 15254 46921 43738 41551 43673 43535 64158>,
+			<45033 15227 46855 43560 41806 43652 43548 64432>,
+			<44123 14462 46153 43581 40975 43649 43625 64304>,
+			<41525 14716 46966 43582 41354 43649 43539 64323>,
+			<41190 15933 46306 43631 42710 43662 43617 64313>,
+			<41296 16266 46933 43136 42601 43656 43916 64487>,
+			<42754 16162 46939 44544 42664 43654 43869 64483>,
+			<42495 16192 46875 44079 41436 43664 43097 64508>,
+			<48041 15555 46710 44477 41240 43669 43267 64440>,
+			<47131 15449 46679 44333 42738 43759 44588 64440>,
+			<48884 15669 46610 44354 42532 43768 45005 64069>,
+			<48294 13014 46812 41619 42535 43764 44263 64146>,
+			<48400 13256 46819 41505 42501 43714 44490 58677>,
+			<46029 12514 46783 41890 42767 43719 44399 64505>,
+			<45503 12744 46805 41837 42275 43716 44515 64740>,
+			<46697 14216 46900 41082 47831 43717 44236 62641>,
+			<46216 13396 46370 41282 47713 43738 44835 52442>,
+			<46474 13648 46400 42707 47876 43739 44653 49493>,
+			<35428  3037 35486 42605 47434 43736 43307 57045>,
+			<35030  2476 35739 42498 48155 43716 43009 55120>,
+			<36483  3592 35625 42702 45888 43770 43194  8928>,
+			<36733  3273 35768 44271 46636 43710 43939  9217>,
+			<36282  3381 35760 43042 45296 43680 43580 14429>;
+	};
+
+	qcom,bp-c-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 46249 43823 42806 43710 43528 63481>,
+			<43661 53696 46923 43968 42940 43711 43581 61818>,
+			<43748 10968 46957 44004 42559 43708 43578 61693>,
+			<43723 10488 46871 44011 42748 43709 43559 62219>,
+			<43554 11874 46853 43917 41291 43698 43554 62183>,
+			<43625 11653 46863 43944 41443 43697 43567 64560>,
+			<43918  8326 46959 43625 41011 43659 43555 65029>,
+			<43824  9826 46947 43521 41801 43663 43571 63926>,
+			<43235  9533 46877 43554 41474 43654 43523 64121>,
+			<43128 14970 46226 43714 41666 43679 43530 58694>,
+			<43327 15254 46921 43738 41551 43673 43535 64158>,
+			<45033 15227 46855 43560 41806 43652 43548 64432>,
+			<44123 14462 46153 43581 40975 43649 43625 64304>,
+			<41525 14716 46966 43582 41354 43649 43539 64323>,
+			<41190 15933 46306 43631 42710 43662 43617 64313>,
+			<41296 16266 46933 43136 42601 43656 43916 64487>,
+			<42754 16162 46939 44544 42664 43654 43869 64483>,
+			<42495 16192 46875 44079 41436 43664 43097 64508>,
+			<48041 15555 46710 44477 41240 43669 43267 64440>,
+			<47131 15449 46679 44333 42738 43759 44588 64440>,
+			<48884 15669 46610 44354 42532 43768 45005 64069>,
+			<48294 13014 46812 41619 42535 43764 44263 64146>,
+			<48400 13256 46819 41505 42501 43714 44490 58677>,
+			<46029 12514 46783 41890 42767 43719 44399 64505>,
+			<45503 12744 46805 41837 42275 43716 44515 64740>,
+			<46697 14216 46900 41082 47831 43717 44236 62641>,
+			<46216 13396 46370 41282 47713 43738 44835 52442>,
+			<46474 13648 46400 42707 47876 43739 44653 49493>,
+			<35428  3037 35486 42605 47434 43736 43307 57045>,
+			<35030  2476 35739 42498 48155 43716 43009 55120>,
+			<36483  3592 35625 42702 45888 43770 43194  8928>,
+			<36733  3273 35768 44271 46636 43710 43939  9217>,
+			<36282  3381 35760 43042 45296 43680 43580 14429>;
+	};
+
+	qcom,bp-c-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 48492 43621 41539 43657 43521 38680>,
+			<43661 53705 48409 43543 41519 43661 43523 38594>,
+			<43748 10994 48432 43522 41614 43654 43523 37248>,
+			<43723 10371 48422 43572 44383 43653 43523 36920>,
+			<43554 11813 48600 43555 44340 43679 43521 37855>,
+			<43625 11358 48638 43739 44442 43671 43525 37551>,
+			<43918  9053 48528 43762 44062 43744 43536 40160>,
+			<43824  9776 48590 43757 44286 43773 43625 40543>,
+			<43235  9692 48237 43703 44906 43520 43618 39212>,
+			<43128 14873 48213 43705 44843 43596 43541 39122>,
+			<43327 15266 48178 43707 44876 43911 43542 38973>,
+			<45033 15166 48573 43674 44039 43732 43636 39343>,
+			<44123 14390 48234 43753 44459 43720 43602 39340>,
+			<41525 14606 48515 43763 44451 43774 43936 38950>,
+			<41190 16087 48131 43771 44478 43761 43612 39798>,
+			<41296 15966 48129 44766 43333 43555 44865 39146>,
+			<42754 16372 48178 44808 43303 43582 41716 39147>,
+			<42495 16254 48344 44894 43386 43583 41778 39041>,
+			<48041 15566 48382 44265 44719 43583 41024 39092>,
+			<47131 15794 48318 44066 44684 43580 42738 39083>,
+			<48884 12972 48292 44094 43348 43576 41408 39879>,
+			<48294 13237 48266 44091 43386 43559 41929 39494>,
+			<48400 12522 48311 44046 43378 43555 44358 39453>,
+			<46029 12786 48903 44452 44697 43552 44308 39499>,
+			<45503 13879 48958 44482 44557 43556 44354 39883>,
+			<46697 13316 49105 44033 44632 43555 44547 39743>,
+			<46216  2730 48904 44122 44809 43555 44729 39403>,
+			<46474  2683 48987 44530 44243 43552 43348 40812>,
+			<35428  2303 48309 44319 44307 43553 43282 37756>,
+			<35030  2373 48257 44365 41878 43556 43272 38299>,
+			<36483  3847 48266 44614 42982 43730 43221 61356>,
+			<36733  3536 48302 43756 47846 43753 43598 57367>,
+			<36282   513 48308 43769 42998 43667 43547 58712>;
+	};
+
+	qcom,bp-c-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 42192 43128 43244 43727 44594 46360>,
+			<43661 53740 42033 43027 43242 43719 44790 46504>,
+			<43748 10931 41985 43070 43163 43740 44676 46328>,
+			<43723 11133 41988 43050 43138 43728 44727 46934>,
+			<43554 11911 41989 43250 43196 43561 44713 47092>,
+			<43625 11320 41985 43136 43182 43559 43355 46603>,
+			<43918  9010 42202 43181 43858 43583 44711 45381>,
+			<43824  9872 42114 43199 43881 43575 44634 45547>,
+			<43235  9639 42864 43196 43827 43523 44916 45105>,
+			<43128 15050 42825 43815 43886 43551 43517 45891>,
+			<43327 14849 42844 43778 43903 43551 43504 45943>,
+			<45033 15288 42816 43063 43843 43527 41833 45265>,
+			<44123 14502 42850 43111 43167 43545 41290 45112>,
+			<41525 14773 42853 43072 43137 43543 42860 45186>,
+			<41190 16046 42779 43076 43156 43537 42902 45950>,
+			<41296 15893 42815 43110 43178 43550 41191 45652>,
+			<42754 16367 42968 43125 43180 43525 41810 45630>,
+			<42495 16229 42959 43103 43144 43520 41560 45766>,
+			<48041 15555 43002 43395 43259 43527 41895 45778>,
+			<47131 15793 42935 43463 43063 43538 41747 45679>,
+			<48884 15704 42923 43307 43405 43540 41763 45959>,
+			<48294 12868 42892 43307 43384 43628 41141 45835>,
+			<48400 12454 42939 43297 44789 43622 42133 45224>,
+			<46029 12586 42567 43298 43271 43642 42378 46003>,
+			<45503 14277 42584 43496 43204 43629 41437 48443>,
+			<46697 13820 42930 43089 43138 43547 44463 48615>,
+			<46216  2769 42890 43425 43222 43524 44241 48463>,
+			<46474  3022 42926 43392 43044 43547 44041 45697>,
+			<35428  2477 42573 43487 43008 43538 44505 45590>,
+			<35030  3601 42568 43271 43443 43551 44455 45926>,
+			<36483  3292 42565 43362 44582 43627 44872 46658>,
+			<36733   671 42898 43497 44078 43540 44672 35344>,
+			<36282   971 42578 43043 44115 43553 43059 35054>;
+	};
+
+	qcom,bp-c-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 41793 43858 43922 43542 41226 47804>,
+			<43661 53646 41849 43895 43930 43631 41458 42348>,
+			<43748 54642 41747 43796 43906 43620 40993 42461>,
+			<43723 11042 41734 43781 43919 43641 41120 42491>,
+			<43554 10616 41791 43832 43956 43633 41890 42400>,
+			<43625 11416 41940 43993 43964 43599 41663 42014>,
+			<43918  9116 41951 44017 43943 43611 44291 42227>,
+			<43824  8574 41958 44022 43950 43615 41695 42114>,
+			<43235  9230 41880 44012 43939 43605 44373 42827>,
+			<43128  9555 41884 44008 43598 43947 41001 42763>,
+			<43327 15085 41880 44001 43634 43608 41407 42966>,
+			<45033 14863 41869 43822 43832 43615 41081 42215>,
+			<44123 15106 41899 43815 43801 43614 41253 42212>,
+			<41525 14441 41554 43786 43803 43609 42813 42115>,
+			<41190 14605 41567 43777 43885 43589 42861 42162>,
+			<41296 16114 41590 43795 43899 43590 42201 42152>,
+			<42754 16299 41494 43800 43823 43587 42961 42975>,
+			<42495 16179 41527 43799 43822 43596 42643 43003>,
+			<48041 15598 41517 43884 43824 43595 41122 43000>,
+			<47131 15776 41683 43854 43887 43633 41771 42960>,
+			<48884 15706 41669 43177 43169 43634 41964 42879>,
+			<48294 13225 41675 43179 43218 43647 44345 42118>,
+			<48400 12521 41721 43171 43082 43647 44405 42023>,
+			<46029 12654 41717 43176 43129 43636 42633 42183>,
+			<45503 14091 41718 43879 43781 43599 41290 42936>,
+			<46697 13810 41717 43792 44028 43596 41818 42502>,
+			<46216  2570 41674 43793 43995 43596 41893 42610>,
+			<46474  2866 41675 43883 43811 43587 41495 42924>,
+			<35428  2531 41664 43898 43794 43597 41723 42952>,
+			<35030  4014 41680 43842 43866 43593 41672 42872>,
+			<36483  3181 41512 43179 43251 43595 44369 42022>,
+			<36733   553 41478 43856 43305 43586 44882 47752>,
+			<36282   769 41691 43829 43494 43964 43315 42352>;
+	};
+
+	qcom,bp-c-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 44354 44009 43908 43585 44092 41271>,
+			<43661 53331 44404 44014 43956 43611 44352 41434>,
+			<43748 54567 44411 44014 43936 43613 41958 41455>,
+			<43723 11167 44384 44009 43947 43600 41821 41370>,
+			<43554 10705 44311 44011 43588 43946 41357 41376>,
+			<43625 12145 44293 43926 43633 43949 42720 41075>,
+			<43918  8778 44303 43909 43623 43963 42544 41012>,
+			<43824  8491 44325 43906 43630 43966 42591 41177>,
+			<43235  9466 44504 43966 43616 43915 41225 41187>,
+			<43128  9497 44484 43610 43617 43930 41179 41144>,
+			<43327 15011 44535 43606 43550 43912 41989 41808>,
+			<45033 15053 44537 43955 43970 43913 41787 40978>,
+			<44123 15300 44513 43952 43974 43913 41169 40975>,
+			<41525 14372 44443 43913 43971 43913 42660 41017>,
+			<41190 14810 44467 43930 43811 43958 42710 41012>,
+			<41296 16010 44454 43921 43801 43964 42581 40978>,
+			<42754 15991 44120 43926 44000 43961 42210 41095>,
+			<42495 16340 44149 44013 44011 43939 42949 41149>,
+			<48041 15515 44140 44025 44027 43950 41275 41099>,
+			<47131 15787 44057 43983 43999 43605 41137 41196>,
+			<48884 15704 44044 43985 43780 43606 41552 40993>,
+			<48294 13216 44086 43810 43179 43600 44381 41032>,
+			<48400 12541 44095 43998 43233 43606 44468 41400>,
+			<46029 12623 44091 43983 43165 43607 41877 41033>,
+			<45503 14102 44094 43926 43932 43938 40990 41754>,
+			<46697 13762 44082 43917 43936 43942 41929 41950>,
+			<46216  2585 44081 43928 43959 43938 41957 41785>,
+			<46474  2817 44042 44001 43904 43948 40992 41832>,
+			<35428  2548 44033 44031 44024 43948 41100 41133>,
+			<35030  4021 44063 44031 43810 43950 41580 41191>,
+			<36483  3150 44143 43976 43892 43945 41648 41056>,
+			<36733   561 44152 43986 43218 43950 44124 41273>,
+			<36282   791 44033 43971 43227 44003 44622 41470>;
+	};
+
+	qcom,bp-d-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    39    78    97   136>,
+			<  195   292   410   585   722>,
+			<  917  1347  1777  2207  2636>,
+			< 3066  3496  3925  4355  4785>,
+			< 5214  5644  6074  6503  6933>,
+			< 7363  7714  7968  8398  8828>,
+			< 9257  9687 10000>;
+		qcom,ocv = <30573 31378 32148 32511 33171>,
+			<33946 34784 35511 36281 36628>,
+			<36800 36904 37089 37320 37504>,
+			<37676 37863 38059 38243 38435>,
+			<38653 38912 39204 39552 40019>,
+			<40572 40908 41136 41558 42004>,
+			<42457 42948 43345>;
+	};
+
+	qcom,bp-d-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 54254 59705 21845 21845 43691 43699 21845>,
+			<43661 53723 59506 21845 21845 43691 43705 21845>,
+			<43748 55249 60243 21845 21845 43691 43697 21845>,
+			<43723 54488 60202 21845 21845 43691 43662 21845>,
+			<43554 10900 59939 21845 21845 43690 43670 21845>,
+			<43625 10291 38323 21845 21845 43690 43738 21845>,
+			<43918 12097 38553 21845 10225 43690 43604 21845>,
+			<43824  8758 37091 21845 58409 43690 43998 21845>,
+			<43235  8578 37390 21845 36992 43690 43864 21845>,
+			<43128  9920 40220 21845 40738 43691 43191 21845>,
+			<43327 10090 40216 21845 40568 43691 43229 21845>,
+			<45033  9514 40151 24910 33285 43691 43017 21845>,
+			<44123 14884 40581  3528 35824 43691 43200 21845>,
+			<41525 15304 40648 12876 47073 43691 43232 21845>,
+			<41190 14500 39183 14356 45543 43691 43146 21845>,
+			<41296 14345 40480  9894 45193 43691 43862 21845>,
+			<42754 14750 40936 11355 46008 43691 43871 21845>,
+			<42495 14702 40544 10366 45750 43691 43862 21845>,
+			<48041 16122 40638 55123 48428 43691 43841 21845>,
+			<47131 15947 40911 54106 48220 43691 43889 21845>,
+			<48884 16340 40499 56417 48328 43691 43901 21845>,
+			<48294 15491 40593 55745 48308 43691 43875 21845>,
+			<48400 15450 40879 56134 48972 43691 43872 21845>,
+			<46029 15694 40788 56203 48974 43691 43899 21845>,
+			<45503 13236 40660 56235 48334 43691 43178 21845>,
+			<46697 12293 40931 55627 48468 43691 43256 21845>,
+			<46216 13989 40843 56529 45879 43691 43249 21845>,
+			<46474 14306 40874 54079 45366 43691 43230 21845>,
+			<35428  2786 40929 12141 36437 43691 44553 21845>,
+			<35030  2209 40450  9760 36155 43691 43205 21845>,
+			<36483  3734 40551 12780 36661 43691 43842 21845>,
+			<36733  3481 40093  7190 46961 43691 43842 21845>,
+			<36282   886 40262 24682 48397 43691 43863 21845>;
+	};
+
+	qcom,bp-d-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 56785 40870 21845 21845 43689 43690 21845>,
+			<43661 53639 39288 21845 21845 43688 43686 21845>,
+			<43748 54465 39134 21845 21845 43691 43727 21845>,
+			<43723 54631 39702 21845 21845 43691 43574 21845>,
+			<43554 10411 39582 21845  4257 43690 43914 21845>,
+			<43625 11819 34602 26974 37269 43691 43260 21845>,
+			<43918 11530 33620  8320 45420 43691 43280 21845>,
+			<43824  8344 33308 54068 49087 43691 43355 21845>,
+			<43235  9830 33695 55743 48755 43691 44747 21845>,
+			<43128  9379 33734 56293 48564 43691 44772 21845>,
+			<43327  9601 33715 56096 45294 43691 44729 21845>,
+			<45033 15095 33664 52620 48552 43691 43130 21845>,
+			<44123 15247 33717 62952 47594 43691 43213 21845>,
+			<41525 15201 33336 62243 47621 43691 43240 21845>,
+			<41190 14543 33335 63815 42243 43691 43144 21845>,
+			<41296 14419 33311 58803 42064 43691 43185 21845>,
+			<42754 14624 33362 57662 42043 43691 43147 21845>,
+			<42495 16063 33675 60766 42235 43691 43196 21505>,
+			<48041 15880 33737 61161 42833 43688 43188 20700>,
+			<47131 16280 33401 60355 42849 43688 43175 23937>,
+			<48884 16255 33570 38384 42753 43688 43192 24481>,
+			<48294 15419 33384 38819 42855 43688 43169 22640>,
+			<48400 15659 33339 38632 42216 43688 43164 22529>,
+			<46029 12829 33334 38633 42487 43688 43059 24261>,
+			<45503 12420 33690 38502 47968 43691 43015 23934>,
+			<46697 12667 33618 38362 47447 43691 43046 22349>,
+			<46216 13552 33788 60619 46526 43691 44565 21845>,
+			<46474 13641 33355 57366 36553 43691 44914 21845>,
+			<35428  2987 32907 58944 34908 43691 43213 21845>,
+			<35030  2069 33751 64791 35577 43691 43239 21845>,
+			<36483  3701 33677 52525 46855 43691 43136 21845>,
+			<36733  3549 33573 53471 45549 43691 43876 21845>,
+			<36282   878 33000  9066 45827 43691 43835 21845>;
+	};
+
+	qcom,bp-d-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53448 36742 21845 21845 43690 43690 21845>,
+			<43661 54856 36530 21845 18713 43690 43690 21845>,
+			<43748 54767 34937 23067  3610 43691 43554 21845>,
+			<43723 10959 34951 25029 10706 43691 43985 21845>,
+			<43554 10449 35409  8904 60678 43691 43411 21845>,
+			<43625 12199 46459 62192 46757 43691 44555 21845>,
+			<43918  8894 46468 64077 48883 43691 44620 21078>,
+			<43824  8223 46377 57543 47704 43691 44640 17971>,
+			<43235 10190 46102 59746 42343 43691 44974 19234>,
+			<43128  9229 46556 61372 47241 43691 44572 20215>,
+			<43327  9483 46343 60865 47384 43691 43339 19467>,
+			<45033 15059 46362 38238 42785 43691 43042 32143>,
+			<44123 15241 46544 37732 41001 43691 43261 26154>,
+			<41525 15206 46554 40612 41849 43688 43153 28185>,
+			<41190 14383 46108 33863 41821 43688 43218  5277>,
+			<41296 14727 46482 32977 41091 43688 43222  5027>,
+			<42754 14698 46588 35951 41140 43688 43223  7898>,
+			<42495 16108 46536 35289 41796 43688 43222  6792>,
+			<48041 15977 46520 35522 41801 43688 43153  1776>,
+			<47131 16356 46513 46216 41762 43688 43258   607>,
+			<48884 16196 46519 46735 41763 43688 43237  3111>,
+			<48294 15382 46515 45445 41849 43688 43045  3941>,
+			<48400 15712 46495 45262 41449 43688 43111  3214>,
+			<46029 13234 46487 45243 42826 43688 43128   716>,
+			<45503 12291 46511 46761 47791 43688 43106  1589>,
+			<46697 14209 46504 35167 45822 43688 44270  4509>,
+			<46216 13729 46190 36856 35348 43688 44977 27890>,
+			<46474  2738 46092 36017 35282 43688 43314 24610>,
+			<35428  3050 46498 32977 46316 43688 43191 26253>,
+			<35030  2490 46149 39096 46970 43688 43138 32343>,
+			<36483  3978 46198 38556 45388 43688 43187 29988>,
+			<36733  3375 46157 57970 48224 43691 43888 17212>,
+			<36282   822 46464 63920 48776 43691 43786 23160>;
+	};
+
+	qcom,bp-d-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 54128 46077  2519 53838 43688 43690 21845>,
+			<43661 54827 45661  8656 51542 43688 43659 21845>,
+			<43748 54691 45761 51143 57682 43688 43790 21845>,
+			<43723 10896 45706 62699 60085 43688 43200 21845>,
+			<43554 10432 48439 59762 33229 43688 43386 17457>,
+			<43625 12193 48610 39799 45453 43691 44630 27786>,
+			<43918 11607 48220 33115 47354 43688 45029  7998>,
+			<43824  8219 48338 36051 42020 43688 45017   820>,
+			<43235 10028 48140 35776 42995 43688 44832  2762>,
+			<43128  9339 48346 35267 42247 43688 44637  4029>,
+			<43327  9521 48367 36552 42842 43688 43477  3804>,
+			<45033 15077 48967 46812 44318 43688 43063 14644>,
+			<44123 15273 48338 49001 44468 43688 43034  9139>,
+			<41525 15178 48273 47709 44290 43689 43120 11219>,
+			<41190 14388 48373 42987 44406 43689 43128 53367>,
+			<41296 14742 48383 40999 44363 43694 43026 57248>,
+			<42754 14697 48348 41702 44388 43694 43055 50523>,
+			<42495 16110 48142 44095 44399 43695 43205 49438>,
+			<48041 15980 48255 44550 41606 43693 43144 52530>,
+			<47131 16368 48355 43408 41587 43683 43872 52912>,
+			<48884 15542 48187 43352 41510 43682 43045 51259>,
+			<48294 15780 48325 44789 41939 43682 43076 51254>,
+			<48400 12954 48352 44948 41229 43682 43425 51479>,
+			<46029 13266 48322 44308 42578 43682 43492 52384>,
+			<45503 12374 48284 41831 42146 43687 43402 49761>,
+			<46697 13498 48178 42588 46614 43733 44203 54838>,
+			<46216 13800 48329 42966 46744 43775 43387 54941>,
+			<46474  2729 48285 42844 45212 43670 43205 53550>,
+			<35428  2916 48256 48838 47420 43727 44660 54569>,
+			<35030  2517 48289 47421 48782 43749 43323 10389>,
+			<36483  4085 48284 48957 47386 43663 43219 12185>,
+			<36733  3391 48244 47001 48104 43690 43140  8708>,
+			<36282   990 48639 35657 42431 43690 43025  8667>;
+	};
+
+	qcom,bp-d-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 56775 47640 35996 39236 43753 43690 15573>,
+			<43661 53304 47855 46557 32848 43765 43956 10253>,
+			<43748 55102 42338 48239 35801 43717 43017 50882>,
+			<43723 54357 42273 47345 46711 43742 43471 52003>,
+			<43554 11065 42380 40989 48763 43730 44648 58416>,
+			<43625 11824 42054 44925 42771 43737 44207 38198>,
+			<43918 11594 42428 44545 41542 43773 44063 40239>,
+			<43824  8221 42202 44731 44083 43721 44439 39102>,
+			<43235 10003 42183 43277 44233 43743 44478 33808>,
+			<43128  9662 42129 43374 41662 43730 44883 39673>,
+			<43327  9578 42226 43484 44208 43740 45006 34565>,
+			<45033 14978 42226 43019 43088 43735 45012 36333>,
+			<44123 14923 42170 43049 43121 43558 44921 36769>,
+			<41525 15202 42123 43224 43130 43570 44816 35310>,
+			<41190 14378 42841 43218 43011 43530 44193 35657>,
+			<41296 14726 42146 43054 43118 43529 44287 35416>,
+			<42754 14669 42166 43020 43468 43533 44124 35454>,
+			<42495 15873 42841 43124 43356 43527 44401 35396>,
+			<48041 16329 42829 43083 43335 43551 44464 35490>,
+			<47131 15497 42853 43118 43270 43525 44880 46492>,
+			<48884 15447 42848 43024 43485 43522 45041 46126>,
+			<48294 12970 42862 43101 43301 43527 44284 46095>,
+			<48400 13198 42857 43405 43329 43524 44089 46571>,
+			<46029 12330 42856 43512 44619 43527 44882 35379>,
+			<45503 14073 42782 44689 44327 43542 44079 36491>,
+			<46697 13526 42846 44961 41473 43545 44550 35942>,
+			<46216 13670 42845 44615 44499 43522 44966 36674>,
+			<46474  2586 42841 44651 44273 43531 45043 36792>,
+			<35428  2300 42861 44791 44854 43572 45026 36397>,
+			<35030  3774 42160 44688 45053 43530 44922 36380>,
+			<36483  3955 42148 43389 44615 43574 45012 36574>,
+			<36733  3438 42949 43093 44689 43553 43286 35272>,
+			<36282  1019 42507 43231 43269 43733 43145 34830>;
+	};
+
+	qcom,bp-d-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57067 47769 21845 21845 43570 43690 21845>,
+			<43661 53839 42899 21845 21845 43644 43838 21845>,
+			<43748 54856 41403 57454 21845 43606 43454 21845>,
+			<43723 54317 40998 41129 33239 43946 43373 61234>,
+			<43554 11148 41209 43367 48002 43589 44984 35138>,
+			<43625 11967 41096 43226 42945 43616 44095 46219>,
+			<43918 11669 41823 43180 41874 43630 44389 45999>,
+			<43824  9048 41749 43892 44933 43623 41690 48833>,
+			<43235 10144 41778 43804 43114 43639 41908 48100>,
+			<43128  9239 41728 43795 43479 43585 44107 47948>,
+			<43327  9505 41786 43786 43075 43610 44180 48058>,
+			<45033  9588 41940 44027 43821 43584 44327 42070>,
+			<44123 14885 41933 44026 43834 43602 41639 42001>,
+			<41525 15317 41875 44030 43834 43605 41520 42196>,
+			<41190 14575 41879 44019 43836 43614 41513 42216>,
+			<41296 14783 41864 43968 43847 43614 41689 42201>,
+			<42754 14674 41889 43817 43105 43602 41503 42374>,
+			<42495 15995 41890 43823 43409 43612 44307 42451>,
+			<48041 16184 41556 43813 43130 43608 44329 42054>,
+			<47131 15612 41592 43988 43161 43588 44038 42160>,
+			<48884 15773 41598 43818 43849 43610 44100 42856>,
+			<48294 12956 41574 43808 43896 43591 44422 42776>,
+			<48400 13303 41572 43838 43849 43596 44124 42875>,
+			<46029 12397 41597 43781 43223 43639 44268 41991>,
+			<45503 13834 41547 43150 43379 43623 44279 47665>,
+			<46697 13355 41564 43145 43321 43541 44616 47660>,
+			<46216 13681 41554 43144 43101 43630 44815 47798>,
+			<46474  2660 41556 43191 43064 43618 44186 42256>,
+			<35428  2264 41918 43880 43248 43619 44661 42488>,
+			<35030  3712 41869 43886 43162 43620 44830 42465>,
+			<36483  3907 41881 43801 43197 43647 44866 42472>,
+			<36733  3347 41872 43818 43171 43594 44930 42372>,
+			<36282   944 41885 44031 43171 43596 43325 42378>;
+	};
+
+	qcom,bp-d-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57019 42570 21845 21845 43613 43729 21845>,
+			<43661 54005 41159 21845 21845 43920 43900 21845>,
+			<43748 54927 41473 57872 21845 44026 43406 21845>,
+			<43723 55061 41705 41932 32907 44003 43374 38047>,
+			<43554 10947 41614 43393 42000 43959 44637 45330>,
+			<43625 10704 41632 43799 41407 43597 44241 48273>,
+			<43918 11389 44403 43980 41956 43586 44360 47477>,
+			<43824  9173 44387 44014 44603 43588 41701 42007>,
+			<43235  9780 44299 43934 43147 43949 41947 41303>,
+			<43128  9417 44322 43907 43177 43955 44502 41232>,
+			<43327  9720 44501 43956 43144 43953 44166 41238>,
+			<45033  9472 44484 43947 43928 43912 41837 40992>,
+			<44123 15101 44531 43615 44006 43905 41916 41180>,
+			<41525 15332 44437 43608 43971 43918 41522 41159>,
+			<41190 14512 44420 43600 43977 43959 41978 41189>,
+			<41296 14427 44467 43951 43812 43912 41863 41157>,
+			<42754 14659 44449 43954 43238 43919 41492 41355>,
+			<42495 15986 44118 43956 43134 43912 44352 41264>,
+			<48041 16191 44096 43963 43243 43959 44112 41026>,
+			<47131 15604 44106 43967 43880 43919 44325 41161>,
+			<48884 15850 44147 43954 43992 43959 41631 41121>,
+			<48294 13034 44156 43913 44028 43961 41858 41808>,
+			<48400 13261 44156 43907 43978 43938 41536 41120>,
+			<46029 12410 44157 43927 43903 43600 44288 40960>,
+			<45503 13834 44108 43989 43081 43590 44239 42684>,
+			<46697 13527 44103 43835 43070 43584 44220 41293>,
+			<46216 13691 44120 43968 43145 43586 44824 41459>,
+			<46474  2667 44124 44007 43901 43586 44832 41052>,
+			<35428  2241 44449 44003 43832 43591 44094 40982>,
+			<35030  3723 44465 43924 43973 43614 44524 41013>,
+			<36483  3956 44425 43931 44016 43603 44395 40995>,
+			<36733  3342 44416 43915 44027 43607 41651 41183>,
+			<36282   605 44420 43953 44028 43605 44380 41153>;
+	};
+};

qcom/sun-cdp.dtsi

@@ -192,7 +192,7 @@
 
 	vdd-io-supply = <&pm_humu_l8>;
 	qcom,vdd-io-voltage-level = <1800000 2960000>;
-	qcom,vdd-io-current-level = <0 5600>;
+	qcom,vdd-io-current-level = <0 22000>;
 
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&sdc2_on>;

qcom/sun-coresight.dtsi

@@ -161,30 +161,6 @@
 			};
 		};
 
-		out-ports {
-			port {
-				funnel_gfx_dl_out_replicator_dummy: endpoint {
-				remote-endpoint =
-					<&replicator_dummy_in_funnel_gfx_dl>;
-				};
-			};
-		};
-	};
-
-	gpu-replicator {
-		compatible = "arm,coresight-static-replicator";
-
-		coresight-name = "coresight-replicator-gpu";
-
-		in-ports {
-			port {
-				replicator_dummy_in_funnel_gfx_dl: endpoint {
-					remote-endpoint =
-					<&funnel_gfx_dl_out_replicator_dummy>;
-				};
-			};
-		};
-
 		out-ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -194,6 +170,7 @@
 				replicator_dummy_out_tpda_dlet: endpoint {
 					remote-endpoint =
 					<&tpda_dlet_in_replicator_dummy>;
+					source = <&tpdm_gfx>;
 				};
 			};
 
@@ -205,7 +182,6 @@
 				};
 			};
 		};
-
 	};
 
 	tpda_dlet: tpda@10c38000 {
@@ -1047,15 +1023,24 @@
 		compatible = "arm,coresight-dummy-source";
 
 		coresight-name = "coresight-modem-diag";
-		atid = <50>;
-
+		qcom,atid-num = <1>;
+		trace-name = "modem-diag";
 		out-ports {
-			port {
+			port@0 {
+				reg = <0>;
 				modem_diag_out_funnel_modem_q6: endpoint {
 					remote-endpoint =
 					<&funnel_modem_q6_in_modem_diag>;
 				};
 			};
+
+			port@1 {
+				reg = <1>;
+				modem_diag_out_qmi: endpoint {
+					remote-endpoint =
+						<&qmi_in_modem_diag>;
+				};
+			};
 		};
 	};
 
@@ -1652,7 +1637,7 @@
 		};
 	};
 
-	tpdm_mm_bcv: tpdm@0x1084e000 {
+	tpdm_mm_bcv: tpdm@1084e000 {
 		compatible = "arm,primecell";
 		arm,primecell-periphid = <0x000bb968>;
 		reg = <0x1084e000 0x1000>;
@@ -2187,6 +2172,7 @@
 
 		cluster = <0>;
 		core = <0>;
+		power-domains = <&CLUSTER_PD0>;
 
 		out-ports {
 			port {
@@ -2243,6 +2229,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -2293,6 +2280,7 @@
 
 		cluster = <0>;
 		core = <1>;
+		power-domains = <&CLUSTER_PD0>;
 
 		out-ports {
 			port {
@@ -2348,6 +2336,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -2398,6 +2387,7 @@
 
 		cluster = <0>;
 		core = <2>;
+		power-domains = <&CLUSTER_PD0>;
 
 		out-ports {
 			port {
@@ -2453,6 +2443,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -2503,6 +2494,7 @@
 
 		cluster = <0>;
 		core = <3>;
+		power-domains = <&CLUSTER_PD0>;
 
 		out-ports {
 			port {
@@ -2558,6 +2550,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -2608,6 +2601,7 @@
 
 		cluster = <0>;
 		core = <4>;
+		power-domains = <&CLUSTER_PD0>;
 
 		out-ports {
 			port {
@@ -2663,6 +2657,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -2713,6 +2708,7 @@
 
 		cluster = <0>;
 		core = <5>;
+		power-domains = <&CLUSTER_PD0>;
 
 		out-ports {
 			port {
@@ -2768,6 +2764,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -2802,6 +2799,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			#address-cells = <1>;
@@ -2873,6 +2871,7 @@
 
 		cluster = <0>;
 		qcom,uncore_uetm;
+		power-domains = <&CLUSTER_PD0>;
 
 		out-ports {
 			port {
@@ -2893,6 +2892,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -2924,6 +2924,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -2958,6 +2959,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			#address-cells = <1>;
@@ -3000,6 +3002,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD0>;
 
 		in-ports {
 			port {
@@ -3046,6 +3049,7 @@
 
 		cluster = <1>;
 		core = <0>;
+		power-domains = <&CLUSTER_PD1>;
 
 		out-ports {
 			port {
@@ -3101,6 +3105,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD1>;
 
 		in-ports {
 			port {
@@ -3151,6 +3156,7 @@
 
 		cluster = <1>;
 		core = <1>;
+		power-domains = <&CLUSTER_PD1>;
 
 		out-ports {
 			port {
@@ -3206,6 +3212,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD1>;
 
 		in-ports {
 			port {
@@ -3240,6 +3247,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD1>;
 
 		in-ports {
 			#address-cells = <1>;
@@ -3279,6 +3287,7 @@
 
 		cluster = <1>;
 		qcom,uncore_uetm;
+		power-domains = <&CLUSTER_PD1>;
 
 		out-ports {
 			port {
@@ -3299,6 +3308,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD1>;
 
 		in-ports {
 			port {
@@ -3330,6 +3340,7 @@
 		qcom,replicator-loses-context;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD1>;
 
 		in-ports {
 			port {
@@ -3364,6 +3375,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD1>;
 
 		in-ports {
 			#address-cells = <1>;
@@ -3396,7 +3408,7 @@
 		};
 	};
 
-	tmc@1b109000 {
+	tmc@13d09000 {
 		compatible = "arm,primecell";
 		arm,primecell-periphid = <0x000bb961>;
 		reg = <0x13d09000 0x1000>;
@@ -3406,6 +3418,7 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+		power-domains = <&CLUSTER_PD1>;
 
 		in-ports {
 			port {
@@ -4092,7 +4105,6 @@
 		reg-names = "stm-base", "stm-stimulus-base";
 
 		coresight-name = "coresight-stm";
-		atid = <16>;
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
@@ -5325,7 +5337,6 @@
 
 		qcom,iommu-dma = "bypass";
 		iommus = <&apps_smmu 0x04e0 0x0>;
-		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
 		dma-coherent;
 		arm,scatter-gather;
 
@@ -5361,7 +5372,6 @@
 		coresight-name = "coresight-tmc-etr1";
 
 		iommus = <&apps_smmu 0x0500 0x0>;
-		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
 		dma-coherent;
 		arm,scatter-gather;
 
@@ -5481,6 +5491,14 @@
 						<&tmc_modem_out_qmi>;
 				};
 			};
+
+			port@3 {
+				reg = <3>;
+				qmi_in_modem_diag: endpoint {
+					remote-endpoint =
+						<&modem_diag_out_qmi>;
+				};
+			};
 		};
 	};
 
@@ -5505,13 +5523,24 @@
 		reg = <0x10010000 0x1000>;
 
 		arm,primecell-periphid = <0x000bb922>;
-		coresight-name = "coresight-cti-swao";
+		coresight-name = "coresight-cti-qdss";
 
 		qcom,extended_cti;
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
 	};
 
+	swao_cti: cti@10b00000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b00000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-swao";
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
 	cti@10b21000 {
 		compatible = "arm,coresight-cti", "arm,primecell";
 		reg = <0x10b21000 0x1000>;

qcom/sun-debug.dtsi

@@ -894,10 +894,5 @@
 			qcom,dump-size = <0x300000>;
 			qcom,dump-id = <0x221>;
 		};
-
-		scandump_ubwcp {
-			qcom,dump-size = <0x40000>;
-			qcom,dump-id = <0x222>;
-		};
 	};
 };

qcom/sun-mtp-3.5mm-overlay.dts

@@ -6,11 +6,12 @@
 /dts-v1/;
 /plugin/;
 
-#include "sun-mtp.dtsi"
+#include "sun-mtp-v8.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm";
-	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
+			   "qcom,mtp";
 	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
 	qcom,board-id = <0x60008 0>;
 };

qcom/sun-mtp-3.5mm.dtsi

@@ -3,4 +3,4 @@
  * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
-#include "sun-mtp.dtsi"
+#include "sun-mtp-v8.dtsi"

qcom/sun-mtp-qmp1000-overlay.dts

@@ -13,5 +13,5 @@
 	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
 			   "qcom,mtp";
 	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
-	qcom,board-id = <0x10108 0>;
+	qcom,board-id = <0x108 0>;
 };

qcom/sun-mtp.dtsi

@@ -268,7 +268,7 @@
 
 	vdd-io-supply = <&pm_humu_l8>;
 	qcom,vdd-io-voltage-level = <1800000 2960000>;
-	qcom,vdd-io-current-level = <0 5600>;
+	qcom,vdd-io-current-level = <0 22000>;
 
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&sdc2_on>;

qcom/sun-oemvm.dtsi

@@ -47,17 +47,15 @@
 			exit-latency-us = <129>;
 			min-residency-us = <560>;
 			arm,psci-suspend-param = <0x00000004>;
-			status = "disabled";
 		};
 
-		CLUSTER_PWR_DWN: cl5 { /* C4+CL5 */
+		CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
 			compatible = "arm,idle-state";
 			idle-state-name = "ret-pll-off";
 			entry-latency-us = <1964>;
 			exit-latency-us = <1901>;
 			min-residency-us = <24511>;
-			arm,psci-suspend-param = <0x01000054>;
-			status = "disabled";
+			arm,psci-suspend-param = <0x0000C354>;
 		};
 	};
 
@@ -109,6 +107,12 @@
 		vdevices {
 			generate = "/hypervisor";
 
+			minidump {
+				vdevice-type = "minidump";
+				push-compatible = "qcom,minidump_rm";
+				minidump_allowed;
+			};
+
 			rm-rpc {
 				vdevice-type = "rm-rpc";
 				generate = "/hypervisor/qcom,resource-mgr";
@@ -251,11 +255,11 @@
 		affinity = <0>;
 	};
 
-	qcom,gh-qtimer@16805000 {
+	qcom,gh-qtimer@1680b000 {
 		compatible = "qcom,gh-qtmr";
-		reg = <0x16805000 0x1000>;
+		reg = <0x1680b000 0x1000>;
 		reg-names = "qtmr-base";
-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "qcom,qtmr-intr";
 		qcom,secondary;
 	};

qcom/sun-pcie.dtsi

@@ -51,7 +51,8 @@
 				&pcie0_clkreq_sleep
 				&pcie0_wake_default>;
 
-		gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
+		power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
+		power-domain-names = "gdsc-phy-vdd";
 
 		qcom,bw-scale = /* Gen1 */
 				<RPMH_REGULATOR_LEVEL_LOW_SVS