Merge 89b9fca649
on remote branch
Change-Id: I7bdb8732fc7952867f80eddabea5a4136021f015
This commit is contained in:
@@ -83,6 +83,9 @@
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<MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */
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<MHZ_TO_KBPS(4761, 4)>; /* TURBO_L3 index=11 */
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nvmem-cells = <&gpu_speed_bin>;
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nvmem-cell-names = "speed_bin";
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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|
@@ -4,19 +4,18 @@
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*/
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/* ACD Control register values */
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#define ACD_LEVEL_TURBO_L3 0x882a5ffd
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#define ACD_LEVEL_TURBO_L1 0x882a5ffd
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#define ACD_LEVEL_NOM_L1 0x882b5ffd
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#define ACD_LEVEL_NOM 0x882b5ffd
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#define ACD_LEVEL_SVS_L2 0x882b5ffd
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#define ACD_LEVEL_SVS_L1 0xa82b5ffd
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#define ACD_LEVEL_SVS_L0 0x882d5ffd
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#define ACD_LEVEL_TURBO_L4 0x88295ffd
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#define ACD_LEVEL_TURBO_L3 0x88295ffd
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#define ACD_LEVEL_TURBO_L1 0xa8295ffd
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#define ACD_LEVEL_NOM_L1 0x882a5ffd
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#define ACD_LEVEL_NOM 0x882a5ffd
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#define ACD_LEVEL_SVS_L2 0x882a5ffd
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#define ACD_LEVEL_SVS_L1 0xa82a5ffd
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#define ACD_LEVEL_SVS_L0 0x882c5ffd
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#define ACD_LEVEL_SVS 0xa82e5ffd
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#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd
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#define ACD_LEVEL_LOW_SVS 0xe02d5ffd
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#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd
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#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd
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#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd
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#define ACD_LEVEL_LOW_SVS_L1 0xc02e5ffd
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#define ACD_LEVEL_LOW_SVS 0xc02e5ffd
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#define ACD_LEVEL_LOW_SVS_D0 0xc8285ffd
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&msm_gpu {
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/* Power levels */
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@@ -26,12 +25,16 @@
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compatible = "qcom,gpu-pwrlevels-bins";
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/*
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* The bins need to match based on speed bin first and then SKU.
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* Keep pwrlevel bins sorted in ascending order of the fmax of the bins.
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*/
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <10>;
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qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)>;
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qcom,speed-bin = <0xbe>;
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/* NOM */
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qcom,gpu-pwrlevel@0 {
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@@ -146,8 +149,6 @@
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
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};
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/* Low_SVS_D2 */
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@@ -159,8 +160,6 @@
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
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};
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/* Low_SVS_D3 */
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@@ -180,7 +179,7 @@
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#size-cells = <0>;
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qcom,initial-pwrlevel = <12>;
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qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
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qcom,speed-bin = <0xdd>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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@@ -321,8 +320,6 @@
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
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};
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/* Low_SVS_D2 */
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@@ -334,8 +331,6 @@
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
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};
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/* Low_SVS_D3 */
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@@ -354,8 +349,350 @@
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <12>;
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qcom,speed-bin = <0xe8>;
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/* TURBO_L3 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <1100000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <967000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_NOM_L1>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <900000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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qcom,acd-level = <ACD_LEVEL_NOM>;
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};
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/* SVS_L2 */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <832000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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qcom,acd-level = <ACD_LEVEL_SVS_L2>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <734000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <10>;
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qcom,acd-level = <ACD_LEVEL_SVS_L1>;
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};
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/* SVS_L0 */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <660000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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qcom,acd-level = <ACD_LEVEL_SVS_L0>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <607000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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||||
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qcom,bus-freq = <6>;
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||||
qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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qcom,acd-level = <ACD_LEVEL_SVS>;
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};
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/* Low_SVS_L1 */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <525000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
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};
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/* Low_SVS */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <443000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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||||
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qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
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};
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/* Low_SVS_D0 */
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <389000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
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};
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/* Low_SVS_D1 */
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qcom,gpu-pwrlevel@10 {
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reg = <10>;
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qcom,gpu-freq = <342000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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};
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/* Low_SVS_D2 */
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qcom,gpu-pwrlevel@11 {
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reg = <11>;
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qcom,gpu-freq = <222000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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};
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/* Low_SVS_D3 */
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qcom,gpu-pwrlevel@12 {
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reg = <12>;
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qcom,gpu-freq = <160000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
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||||
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qcom,bus-freq = <3>;
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||||
qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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};
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};
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qcom,gpu-pwrlevels-3 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <12>;
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qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)>;
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/* TURBO_L3 */
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qcom,gpu-pwrlevel@0 {
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||||
reg = <0>;
|
||||
qcom,gpu-freq = <1100000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
|
||||
};
|
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|
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/* NOM_L1 */
|
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
|
||||
qcom,gpu-freq = <967000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
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qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
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|
||||
/* NOM */
|
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qcom,gpu-pwrlevel@2 {
|
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reg = <2>;
|
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qcom,gpu-freq = <900000000>;
|
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <10>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <832000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <10>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <734000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <10>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <660000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <607000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <525000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <443000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <389000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <342000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <222000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D3 */
|
||||
qcom,gpu-pwrlevel@12 {
|
||||
reg = <12>;
|
||||
qcom,gpu-freq = <160000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <13>;
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
qcom,speed-bin = <0xf2>;
|
||||
|
||||
/* TURBO_L3 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
@@ -389,8 +726,8 @@
|
||||
qcom,gpu-freq = <967000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
@@ -509,8 +846,6 @@
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
@@ -522,8 +857,6 @@
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D3 */
|
||||
@@ -537,5 +870,203 @@
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <14>;
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)
|
||||
SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
/* TURBO_L4 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1200000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L4>;
|
||||
};
|
||||
|
||||
/* TURBO_L3 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <1100000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
|
||||
};
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <1050000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <967000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <10>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <832000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <10>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <734000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <10>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <660000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <607000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <525000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <443000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <389000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@12 {
|
||||
reg = <12>;
|
||||
qcom,gpu-freq = <342000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@13 {
|
||||
reg = <13>;
|
||||
qcom,gpu-freq = <222000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D3 */
|
||||
qcom,gpu-pwrlevel@14 {
|
||||
reg = <14>;
|
||||
qcom,gpu-freq = <160000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
Reference in New Issue
Block a user