From 48b0e9aa4476e3477904d05522b9d3a61bf9ac1f Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 8 May 2024 13:51:01 -0600 Subject: [PATCH 1/5] ARM: dts: msm: Update Sun V2 GPU frequencies Add new GPU frequency support for Sun V2. Change-Id: I66a6584a671e51a8420e2ceaace3c067ee56d009 Signed-off-by: Carter Cooper --- gpu/sun-v2-gpu-pwrlevels.dtsi | 72 +++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 29 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 7a70ac8d..3418c791 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -4,6 +4,7 @@ */ /* ACD Control register values */ +#define ACD_LEVEL_TURBO_L4 0x88295ffd #define ACD_LEVEL_TURBO_L3 0x882a5ffd #define ACD_LEVEL_TURBO_L1 0x882a5ffd #define ACD_LEVEL_NOM_L1 0x882b5ffd @@ -354,13 +355,26 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <13>; + qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; - /* TURBO_L3 */ + /* TURBO_L4 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1150000000>; + qcom,gpu-freq = <1200000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1100000000>; qcom,level = ; qcom,bus-freq = <11>; @@ -371,8 +385,8 @@ }; /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <1050000000>; qcom,level = ; @@ -384,8 +398,8 @@ }; /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <967000000>; qcom,level = ; @@ -397,8 +411,8 @@ }; /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <900000000>; qcom,level = ; @@ -410,8 +424,8 @@ }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <832000000>; qcom,level = ; @@ -423,8 +437,8 @@ }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <734000000>; qcom,level = ; @@ -436,8 +450,8 @@ }; /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <660000000>; qcom,level = ; @@ -449,8 +463,8 @@ }; /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <607000000>; qcom,level = ; @@ -462,8 +476,8 @@ }; /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <525000000>; qcom,level = ; @@ -475,8 +489,8 @@ }; /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; + qcom,gpu-pwrlevel@10 { + reg = <10>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -488,8 +502,8 @@ }; /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; + qcom,gpu-pwrlevel@11 { + reg = <11>; qcom,gpu-freq = <389000000>; qcom,level = ; @@ -501,8 +515,8 @@ }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; + qcom,gpu-pwrlevel@12 { + reg = <12>; qcom,gpu-freq = <342000000>; qcom,level = ; @@ -514,8 +528,8 @@ }; /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; + qcom,gpu-pwrlevel@13 { + reg = <13>; qcom,gpu-freq = <222000000>; qcom,level = ; @@ -527,8 +541,8 @@ }; /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; + qcom,gpu-pwrlevel@14 { + reg = <14>; qcom,gpu-freq = <160000000>; qcom,level = ; From 24406b833c59ec41815c38cd979aed15d3cbf7fd Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 3 Jun 2024 10:11:34 -0700 Subject: [PATCH 2/5] ARM: dts: msm: Read the gpu speed bin on sun devices Read the gpu speed bin devicetree property on sun devices. Change-Id: I54c444bc434a2475ffe5126b7452f642f4dc7b2a Signed-off-by: Lynus Vaz --- gpu/sun-gpu.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 34c90a61..a3e97828 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -83,6 +83,9 @@ , /* TURBO_L1 index=10 */ ; /* TURBO_L3 index=11 */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; From 8c6526dcaa74b5c955e0d36a12a23ba8638da7af Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Wed, 5 Jun 2024 22:31:35 -0700 Subject: [PATCH 3/5] ARM: dts: msm: Update ACD values for Sun v2 GPU Update ACD values with characterized values for Sun v2 GPU. Also disable ACD on lower levels. Change-Id: Ic5f0d7adb7a71be16f393ff90a6d0199179276a3 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-v2-gpu-pwrlevels.dtsi | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index 3418c791..cd161ec7 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -5,19 +5,17 @@ /* ACD Control register values */ #define ACD_LEVEL_TURBO_L4 0x88295ffd -#define ACD_LEVEL_TURBO_L3 0x882a5ffd -#define ACD_LEVEL_TURBO_L1 0x882a5ffd -#define ACD_LEVEL_NOM_L1 0x882b5ffd -#define ACD_LEVEL_NOM 0x882b5ffd -#define ACD_LEVEL_SVS_L2 0x882b5ffd -#define ACD_LEVEL_SVS_L1 0xa82b5ffd -#define ACD_LEVEL_SVS_L0 0x882d5ffd +#define ACD_LEVEL_TURBO_L3 0x88295ffd +#define ACD_LEVEL_TURBO_L1 0xa8295ffd +#define ACD_LEVEL_NOM_L1 0x882a5ffd +#define ACD_LEVEL_NOM 0x882a5ffd +#define ACD_LEVEL_SVS_L2 0x882a5ffd +#define ACD_LEVEL_SVS_L1 0xa82a5ffd +#define ACD_LEVEL_SVS_L0 0x882c5ffd #define ACD_LEVEL_SVS 0xa82e5ffd -#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd -#define ACD_LEVEL_LOW_SVS 0xe02d5ffd -#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd -#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd -#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd +#define ACD_LEVEL_LOW_SVS_L1 0xc02e5ffd +#define ACD_LEVEL_LOW_SVS 0xc02e5ffd +#define ACD_LEVEL_LOW_SVS_D0 0xc8285ffd &msm_gpu { /* Power levels */ @@ -147,8 +145,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -160,8 +156,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ @@ -322,8 +316,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -335,8 +327,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ @@ -523,8 +513,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D2 */ @@ -536,8 +524,6 @@ qcom,bus-freq = <3>; qcom,bus-min = <2>; qcom,bus-max = <3>; - - qcom,acd-level = ; }; /* Low_SVS_D3 */ From 361c4aa3498c9f35f766e14d40e10cf3f3fef779 Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Wed, 12 Jun 2024 12:00:01 -0700 Subject: [PATCH 4/5] ARM: dts: msm: Use the speed bin fuse to determine sun v2 powerlevels Add powerlevels on sun v2 GPUs based on the speed bin fuse on the device. Change-Id: Ia0b35aabce36ab210ed01ea3c8abb90c05e74ac6 Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 547 +++++++++++++++++++++++++++++++++- 1 file changed, 545 insertions(+), 2 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index cd161ec7..df211154 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -25,12 +25,16 @@ compatible = "qcom,gpu-pwrlevels-bins"; + /* + * The bins need to match based on speed bin first and then SKU. + * Keep pwrlevel bins sorted in ascending order of the fmax of the bins. + */ qcom,gpu-pwrlevels-0 { #address-cells = <1>; #size-cells = <0>; qcom,initial-pwrlevel = <10>; - qcom,sku-codes = ; + qcom,speed-bin = <0xbe>; /* NOM */ qcom,gpu-pwrlevel@0 { @@ -175,7 +179,7 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,speed-bin = <0xdd>; /* TURBO_L1 */ qcom,gpu-pwrlevel@0 { @@ -345,6 +349,545 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <12>; + qcom,sku-codes = ; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <13>; + qcom,speed-bin = <0xf2>; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <13>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@13 { + reg = <13>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <14>; qcom,sku-codes = ; From e718fd3680b91212ecfc6c21f62cb89646e90877 Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 24 Jun 2024 19:59:35 -0700 Subject: [PATCH 5/5] ARM: dts: msm: Update Sun v2 GPU power levels Add more powerlevel bins based on updated speed-bin fuse values. Change-Id: I4faf67ffad06ba5873c0e9879b7729f796952d3a Signed-off-by: Lynus Vaz --- gpu/sun-v2-gpu-pwrlevels.dtsi | 368 ++++++++++++++++------------------ 1 file changed, 178 insertions(+), 190 deletions(-) diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi index df211154..c299542b 100644 --- a/gpu/sun-v2-gpu-pwrlevels.dtsi +++ b/gpu/sun-v2-gpu-pwrlevels.dtsi @@ -350,19 +350,19 @@ #size-cells = <0>; qcom,initial-pwrlevel = <12>; - qcom,sku-codes = ; + qcom,speed-bin = <0xe8>; - /* TURBO_L1 */ + /* TURBO_L3 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; + qcom,gpu-freq = <1100000000>; + qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; - qcom,acd-level = ; + qcom,acd-level = ; }; /* NOM_L1 */ @@ -520,6 +520,177 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <12>; + qcom,sku-codes = ; + + /* TURBO_L3 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1100000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <967000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + + qcom,acd-level = ; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + + qcom,acd-level = ; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + + qcom,acd-level = ; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@11 { + reg = <11>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D3 */ + qcom,gpu-pwrlevel@12 { + reg = <12>; + qcom,gpu-freq = <160000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <13>; qcom,speed-bin = <0xf2>; @@ -700,196 +871,13 @@ }; }; - qcom,gpu-pwrlevels-4 { - #address-cells = <1>; - #size-cells = <0>; - - qcom,initial-pwrlevel = <13>; - qcom,sku-codes = ; - - /* TURBO_L3 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1150000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <967000000>; - qcom,level = ; - - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; - - qcom,acd-level = ; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <900000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <832000000>; - qcom,level = ; - - qcom,bus-freq = <10>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <734000000>; - qcom,level = ; - - qcom,bus-freq = <8>; - qcom,bus-min = <6>; - qcom,bus-max = <10>; - - qcom,acd-level = ; - }; - - /* SVS_L0 */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <660000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <607000000>; - qcom,level = ; - - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - - qcom,acd-level = ; - }; - - /* Low_SVS_L1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <525000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS */ - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <443000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D0 */ - qcom,gpu-pwrlevel@10 { - reg = <10>; - qcom,gpu-freq = <389000000>; - qcom,level = ; - - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - - qcom,acd-level = ; - }; - - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@11 { - reg = <11>; - qcom,gpu-freq = <342000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D2 */ - qcom,gpu-pwrlevel@12 { - reg = <12>; - qcom,gpu-freq = <222000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - - /* Low_SVS_D3 */ - qcom,gpu-pwrlevel@13 { - reg = <13>; - qcom,gpu-freq = <160000000>; - qcom,level = ; - - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <3>; - }; - }; - qcom,gpu-pwrlevels-5 { #address-cells = <1>; #size-cells = <0>; qcom,initial-pwrlevel = <14>; - qcom,sku-codes = ; + qcom,sku-codes = ; /* TURBO_L4 */ qcom,gpu-pwrlevel@0 {