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Merge changes Id5ce09d1,I39218bef,Ic6c313f0 into kernel.lnx.6.6.r1-rel

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* changes:
  ARM: dts: msm: correct tpdms'name for kera
  ARM: dts: msm: correct apss-tpda's element size
  ARM: dts: qcom: Add cooling cell property for gpu node for kera
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Linux Build Service Account
2024-12-27 10:37:35 -08:00
committed by Gerrit - the friendly Code Review server
parent d8032c8122 bde61842c6
commit 4870945758
2 changed files with 42 additions and 15 deletions
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34
qcom/kera-coresight.dtsi
View File

@@ -922,8 +922,12 @@
coresight-name = "coresight-tpda-apss"; coresight-name = "coresight-tpda-apss";
qcom,dsb-elem-size = <2 32>,
<8 32>;
qcom,cmb-elem-size = <0 32>, qcom,cmb-elem-size = <0 32>,
<1 32>; <1 32>,
<6 64>;
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -1819,10 +1823,10 @@
}; };
}; };
tpdm_lpass_crdl: tpdm@10bb4000 { tpdm_lpass_crdl: tpdm@10b84000 {
compatible = "arm,primecell"; compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb968>; arm,primecell-periphid = <0x000bb968>;
reg = <0x10bb4000 0x1000>; reg = <0x10b84000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-lpass-crdl"; coresight-name = "coresight-tpdm-lpass-crdl";
@@ -2879,7 +2883,7 @@
reg = <0x10820000 0x1000>; reg = <0x10820000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-dlct-dsb"; coresight-name = "coresight-tpdm-dlct-dsb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -2901,7 +2905,7 @@
reg = <0x10821000 0x1000>; reg = <0x10821000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-dlct-cmb"; coresight-name = "coresight-tpdm-dlct-cmb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3103,7 +3107,7 @@
reg = <0x109a4000 0x1000>; reg = <0x109a4000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-mm-dsb"; coresight-name = "coresight-tpdm-mm-dsb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3126,7 +3130,7 @@
reg = <0x109ae000 0x1000>; reg = <0x109ae000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-west-dsb"; coresight-name = "coresight-tpdm-west-dsb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3149,7 +3153,7 @@
reg = <0x109a5000 0x1000>; reg = <0x109a5000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-south-dsb"; coresight-name = "coresight-tpdm-south-dsb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3170,7 +3174,7 @@
reg = <0x109ab000 0x1000>; reg = <0x109ab000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-ipcc-cmb"; coresight-name = "coresight-tpdm-ipcc-cmb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3192,7 +3196,7 @@
reg = <0x109aa000 0x1000>; reg = <0x109aa000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-center-dsb"; coresight-name = "coresight-tpdm-center-dsb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3214,7 +3218,7 @@
reg = <0x109a7000 0x1000>; reg = <0x109a7000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-rdpm-cx"; coresight-name = "coresight-tpdm-rdpm-cx";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3236,7 +3240,7 @@
reg = <0x109a9000 0x1000>; reg = <0x109a9000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-rdpm-mxc"; coresight-name = "coresight-tpdm-rdpm-mxc";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3258,7 +3262,7 @@
reg = <0x109a8000 0x1000>; reg = <0x109a8000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-rdpm-mxa"; coresight-name = "coresight-tpdm-rdpm-mxa";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3280,7 +3284,7 @@
reg = <0x109ac000 0x1000>; reg = <0x109ac000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-center-cmb"; coresight-name = "coresight-tpdm-center-cmb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -3302,7 +3306,7 @@
reg = <0x109af000 0x1000>; reg = <0x109af000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-south-cmb"; coresight-name = "coresight-tpdm-south-cmb";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";

23
qcom/kera-thermal.dtsi
View File

@@ -5,6 +5,10 @@
#include <dt-bindings/thermal/thermal_qti.h> #include <dt-bindings/thermal/thermal_qti.h>
&msm_gpu {
#cooling-cells = <2>;
};
&soc { &soc {
tsens0: tsens0@c228000 { tsens0: tsens0@c228000 {
compatible = "qcom,tsens-v2"; compatible = "qcom,tsens-v2";
@@ -196,6 +200,11 @@
}; };
}; };
qcom,devfreq-cdev {
compatible = "qcom,devfreq-cdev";
qcom,devfreq = <&msm_gpu>;
};
qcom,cpufreq-cdev { qcom,cpufreq-cdev {
compatible = "qcom,cpufreq-cdev"; compatible = "qcom,cpufreq-cdev";
@@ -977,6 +986,13 @@
type = "hot"; type = "hot";
}; };
}; };
cooling-maps {
gpu0_cdev {
trip = <&gpu0_tj_cfg>;
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
};
};
}; };
gpuss-1 { gpuss-1 {
@@ -1009,6 +1025,13 @@
type = "hot"; type = "hot";
}; };
}; };
cooling-maps {
gpu1_cdev {
trip = <&gpu1_tj_cfg>;
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
};
};
}; };
video { video {