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Merge "ARM: dts: msm: Mention class cpus as cpu phandles for sun/pineapple"

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QCTECMDR Service
2024-07-24 01:49:20 -07:00
committed by Gerrit - the friendly Code Review server
parent d8ac094241 8e39e7601f
commit 47753bb575
2 changed files with 4 additions and 4 deletions
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4
qcom/pineapple.dtsi
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@@ -2389,9 +2389,9 @@
gic-interrupt-router { gic-interrupt-router {
compatible = "qcom,gic-intr-routing"; compatible = "qcom,gic-intr-routing";
/* keep silver core only to avoid wakeup of gold cores */ /* keep silver core only to avoid wakeup of gold cores */
qcom,gic-class0-cpus = <0 1>; qcom,gic-class0-cpus = <&CPU0 &CPU1>;
/* keep gold and gold+ cores in class1 */ /* keep gold and gold+ cores in class1 */
qcom,gic-class1-cpus = <2 3 4 5 6 7>; qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
}; };
qcom,secure-buffer { qcom,secure-buffer {

4
qcom/sun.dtsi
View File

@@ -928,9 +928,9 @@
gic-interrupt-router { gic-interrupt-router {
compatible = "qcom,gic-intr-routing"; compatible = "qcom,gic-intr-routing";
/* keep a few m cores in class0 only to avoid wakeup of l cores */ /* keep a few m cores in class0 only to avoid wakeup of l cores */
qcom,gic-class0-cpus = <0 1>; qcom,gic-class0-cpus = <&CPU0 &CPU1>;
/* keep other cores in class1 */ /* keep other cores in class1 */
qcom,gic-class1-cpus = <2 3 4 5 6 7>; qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
}; };
qcom,secure-buffer { qcom,secure-buffer {