From 8e39e7601fbf9533a2fa4ca75a01bad3df2d55f9 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 18 Jul 2024 21:14:19 +0530 Subject: [PATCH] ARM: dts: msm: Mention class cpus as cpu phandles for sun/pineapple Remove the hard coded class cpus and replace them with their phandles. Change-Id: I283ac79d64d945e12477f61a67b058574bde7031 Signed-off-by: Mukesh Ojha --- qcom/pineapple.dtsi | 4 ++-- qcom/sun.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi index 394325b8..de39ea3a 100644 --- a/qcom/pineapple.dtsi +++ b/qcom/pineapple.dtsi @@ -2389,9 +2389,9 @@ gic-interrupt-router { compatible = "qcom,gic-intr-routing"; /* keep silver core only to avoid wakeup of gold cores */ - qcom,gic-class0-cpus = <0 1>; + qcom,gic-class0-cpus = <&CPU0 &CPU1>; /* keep gold and gold+ cores in class1 */ - qcom,gic-class1-cpus = <2 3 4 5 6 7>; + qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; }; qcom,secure-buffer { diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index a32f4531..154e21cf 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -928,9 +928,9 @@ gic-interrupt-router { compatible = "qcom,gic-intr-routing"; /* keep a few m cores in class0 only to avoid wakeup of l cores */ - qcom,gic-class0-cpus = <0 1>; + qcom,gic-class0-cpus = <&CPU0 &CPU1>; /* keep other cores in class1 */ - qcom,gic-class1-cpus = <2 3 4 5 6 7>; + qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; }; qcom,secure-buffer {