dt-bindings: Add devicetree bindings for dcvs drivers

Add snapshot of dcvs dt bindings as of qcom-6.1
commit 96af901712d3 ("dt-bindings: soc: qcom: Document
CRMB and CRMC regs").

Change-Id: I305f06bee1895feabec2b85b2c5ed4fa80895f83
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Signed-off-by: Gurbir Arora <quic_gurbaror@quicinc.com>

bindings/perf/qcom-llcc-pmu.yaml

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom-llcc-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) LLCC PMU Bindings
+
+maintainers:
+  - avajid@quicinc.com <quic_avajid@quicinc.com>
+  - gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
+
+description: |
+  This represents the miss counters located in the LLCC hardware counters.
+  Only one event is supported.
+
+properties:
+  compatible:
+    enum:
+      - qcom,llcc-pmu-ver1
+      - qcom,llcc-pmu-ver2
+
+  reg:
+    description: base address and size of DDR_LAGG region
+
+  reg-names:
+    const: lagg-base
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+examples:
+  - |
+    llcc_pmu: llcc-pmu {
+        compatible = "qcom,qcom-llcc-pmu-ver1";
+        reg = < 0x090CC000 0x300 >;
+        reg-names = "lagg-base";
+    };