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ARM: dts: msm: add dp dt change for sun platform

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Add dp device tree change for sun platform.

Change-Id: I56d1d7e542fa4de971d5803dc4a40a66ea34dcf3
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
This commit is contained in:
Yahui Wang
2023-11-07 17:11:43 +08:00
parent 313d6ad696
commit 3f35daf3cf
1 changed files with 154 additions and 0 deletions
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154
display/sun-sde.dtsi
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@@ -12,6 +12,160 @@
#include "sun-sde-common.dtsi"
&soc {
ext_disp: qcom,msm-ext-disp {
compatible = "qcom,msm-ext-disp";
};
sde_dp: qcom,dp_display@af54000 {
status = "disabled";
cell-index = <0>;
compatible = "qcom,dp-display";
usb-phy = <&usb_qmp_dp_phy>;
qcom,ext-disp = <&ext_disp>;
usb-controller = <&usb0>;
reg = <0xaf54000 0x104>,
<0xaf54200 0x0c0>,
<0xaf55000 0x770>,
<0xaf56000 0x09c>,
<0x88ebc00 0x200>,
<0x88eb400 0x200>,
<0x88eb800 0x200>,
<0x88eb000 0x200>,
<0x88e8000 0x020>,
<0xaee1000 0x034>,
<0xaf57000 0x09c>,
<0xaf09000 0x014>;
reg-names = "dp_ahb", "dp_aux", "dp_link",
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
"dp_pll", "usb3_dp_com", "hdcp_physical",
"dp_p1", "gdsc";
interrupt-parent = <&mdss_mdp>;
interrupts = <12 0>;
#clock-cells = <1>;
clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&tcsrcc TCSR_USB3_CLKREF_EN>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&sde_dp 0>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&sde_dp 1>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent",
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
qcom,pll-revision = "3nm-v1";
qcom,phy-version = <0x800>;
qcom,aux-cfg0-settings = [20 00];
qcom,aux-cfg1-settings = [24 13];
qcom,aux-cfg2-settings = [28 A4];
qcom,aux-cfg3-settings = [2c 00];
qcom,aux-cfg4-settings = [30 0a];
qcom,aux-cfg5-settings = [34 26];
qcom,aux-cfg6-settings = [38 0a];
qcom,aux-cfg7-settings = [3c 03];
qcom,aux-cfg8-settings = [40 b7];
qcom,aux-cfg9-settings = [44 03];
qcom,max-pclk-frequency-khz = <675000>;
qcom,widebus-enable;
qcom,mst-enable;
qcom,dsc-feature-enable;
qcom,fec-feature-enable;
qcom,dsc-continuous-pps;
qcom,qos-cpu-mask = <0xf>;
qcom,qos-cpu-latency-us = <300>;
vdda-1p2-supply = <&L3G>;
vdda-0p9-supply = <&L2D>;
vdda_usb-0p9-supply = <&L2D>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
qcom,hbr-rbr-voltage-swing = <0x27 0x2f 0x36 0x3f>,
<0x31 0x3e 0x3f 0xff>,
<0x36 0x3f 0xff 0xff>,
<0x3f 0xff 0xff 0xff>;
qcom,hbr-rbr-pre-emphasis = <0x20 0x2d 0x34 0x3a>,
<0x20 0x2e 0x35 0xff>,
<0x20 0x2e 0xff 0xff>,
<0x22 0xff 0xff 0xff>;
qcom,hbr2-3-voltage-swing = <0x22 0x32 0x36 0x3a>,
<0x29 0x39 0x3f 0xff>,
<0x30 0x3f 0xff 0xff>,
<0x3f 0xff 0xff 0xff>;
qcom,hbr2-3-pre-emphasis = <0x20 0x2c 0x35 0x3b>,
<0x22 0x2e 0x36 0xff>,
<0x22 0x31 0xff 0xff>,
<0x24 0xff 0xff 0xff>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <30000>;
qcom,supply-disable-load = <0>;
};
};
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <912000>;
qcom,supply-max-voltage = <912000>;
qcom,supply-enable-load = <114000>;
qcom,supply-disable-load = <0>;
};
qcom,phy-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdda_usb-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <880000>;
qcom,supply-enable-load = <2500>;
qcom,supply-disable-load = <0>;
};
};
qcom,pll-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,pll-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdd_mx";
qcom,supply-min-voltage =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,supply-max-voltage =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x800 0x2>;