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ARM: dts: msm: Add GCC phandle to GDSC driver for Sun

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GCC needs to probe before GDSC regulator driver as driver will be
unable to read registers without required gcc config ahb clocks. These
config ahb clocks are enabled in GCC probe. Thus GCC needs to probe
before GDSC driver. Adding GCC phandles to sequence the probe order
during kernel boot.

Change-Id: Icd13d18f07540f96cb4175edc5bd41526b6a3841
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
This commit is contained in:
Vivek Aknurwar
2023-09-06 14:44:42 -07:00
parent 10e42d9078
commit 3ad392617c
1 changed files with 14 additions and 0 deletions
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14
qcom/sun.dtsi
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@@ -868,6 +868,7 @@
cam_cc_ipe_0_gdsc: qcom,gdsc@adf017c { cam_cc_ipe_0_gdsc: qcom,gdsc@adf017c {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xadf017c 0x4>; reg = <0xadf017c 0x4>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
regulator-name = "cam_cc_ipe_0_gdsc"; regulator-name = "cam_cc_ipe_0_gdsc";
parent-supply = <&cam_cc_titan_top_gdsc>; parent-supply = <&cam_cc_titan_top_gdsc>;
qcom,retain-regs; qcom,retain-regs;
@@ -878,6 +879,7 @@
cam_cc_ofe_gdsc: qcom,gdsc@adf00c8 { cam_cc_ofe_gdsc: qcom,gdsc@adf00c8 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xadf00c8 0x4>; reg = <0xadf00c8 0x4>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
regulator-name = "cam_cc_ofe_gdsc"; regulator-name = "cam_cc_ofe_gdsc";
parent-supply = <&cam_cc_titan_top_gdsc>; parent-supply = <&cam_cc_titan_top_gdsc>;
qcom,retain-regs; qcom,retain-regs;
@@ -888,6 +890,7 @@
cam_cc_tfe_0_gdsc: qcom,gdsc@adf1004 { cam_cc_tfe_0_gdsc: qcom,gdsc@adf1004 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xadf1004 0x4>; reg = <0xadf1004 0x4>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
regulator-name = "cam_cc_tfe_0_gdsc"; regulator-name = "cam_cc_tfe_0_gdsc";
parent-supply = <&cam_cc_titan_top_gdsc>; parent-supply = <&cam_cc_titan_top_gdsc>;
qcom,retain-regs; qcom,retain-regs;
@@ -897,6 +900,7 @@
cam_cc_tfe_1_gdsc: qcom,gdsc@adf1084 { cam_cc_tfe_1_gdsc: qcom,gdsc@adf1084 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xadf1084 0x4>; reg = <0xadf1084 0x4>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
regulator-name = "cam_cc_tfe_1_gdsc"; regulator-name = "cam_cc_tfe_1_gdsc";
parent-supply = <&cam_cc_titan_top_gdsc>; parent-supply = <&cam_cc_titan_top_gdsc>;
qcom,retain-regs; qcom,retain-regs;
@@ -906,6 +910,7 @@
cam_cc_tfe_2_gdsc: qcom,gdsc@adf10ec { cam_cc_tfe_2_gdsc: qcom,gdsc@adf10ec {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xadf10ec 0x4>; reg = <0xadf10ec 0x4>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
regulator-name = "cam_cc_tfe_2_gdsc"; regulator-name = "cam_cc_tfe_2_gdsc";
parent-supply = <&cam_cc_titan_top_gdsc>; parent-supply = <&cam_cc_titan_top_gdsc>;
qcom,retain-regs; qcom,retain-regs;
@@ -915,6 +920,7 @@
cam_cc_titan_top_gdsc: qcom,gdsc@adf134c { cam_cc_titan_top_gdsc: qcom,gdsc@adf134c {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xadf134c 0x4>; reg = <0xadf134c 0x4>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
regulator-name = "cam_cc_titan_top_gdsc"; regulator-name = "cam_cc_titan_top_gdsc";
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
qcom,retain-regs; qcom,retain-regs;
@@ -925,6 +931,7 @@
disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 { disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xaf09000 0x4>; reg = <0xaf09000 0x4>;
clocks = <&gcc GCC_DISP_AHB_CLK>;
regulator-name = "disp_cc_mdss_core_gdsc"; regulator-name = "disp_cc_mdss_core_gdsc";
parent-supply = <&VDD_MM_LEVEL>; parent-supply = <&VDD_MM_LEVEL>;
proxy-supply = <&disp_cc_mdss_core_gdsc>; proxy-supply = <&disp_cc_mdss_core_gdsc>;
@@ -937,6 +944,7 @@
disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 { disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xaf0b000 0x4>; reg = <0xaf0b000 0x4>;
clocks = <&gcc GCC_DISP_AHB_CLK>;
regulator-name = "disp_cc_mdss_core_int2_gdsc"; regulator-name = "disp_cc_mdss_core_int2_gdsc";
parent-supply = <&VDD_MM_LEVEL>; parent-supply = <&VDD_MM_LEVEL>;
qcom,retain-regs; qcom,retain-regs;
@@ -948,6 +956,7 @@
eva_cc_mvs0_gdsc: qcom,gdsc@abf8068 { eva_cc_mvs0_gdsc: qcom,gdsc@abf8068 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xabf8068 0x4>; reg = <0xabf8068 0x4>;
clocks = <&gcc GCC_EVA_AHB_CLK>;
regulator-name = "eva_cc_mvs0_gdsc"; regulator-name = "eva_cc_mvs0_gdsc";
parent-supply = <&eva_cc_mvs0c_gdsc>; parent-supply = <&eva_cc_mvs0c_gdsc>;
qcom,retain-regs; qcom,retain-regs;
@@ -958,6 +967,7 @@
eva_cc_mvs0c_gdsc: qcom,gdsc@abf8034 { eva_cc_mvs0c_gdsc: qcom,gdsc@abf8034 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xabf8034 0x4>; reg = <0xabf8034 0x4>;
clocks = <&gcc GCC_EVA_AHB_CLK>;
regulator-name = "eva_cc_mvs0c_gdsc"; regulator-name = "eva_cc_mvs0c_gdsc";
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
qcom,retain-regs; qcom,retain-regs;
@@ -1044,6 +1054,7 @@
gpu_cc_cx_gdsc: qcom,gdsc@3d99080 { gpu_cc_cx_gdsc: qcom,gdsc@3d99080 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0x3d99080 0x4>; reg = <0x3d99080 0x4>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
regulator-name = "gpu_cc_cx_gdsc"; regulator-name = "gpu_cc_cx_gdsc";
parent-supply = <&VDD_CX_LEVEL>; parent-supply = <&VDD_CX_LEVEL>;
hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>; hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
@@ -1055,6 +1066,7 @@
gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 { gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0x3d68024 0x4>; reg = <0x3d68024 0x4>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
regulator-name = "gx_clkctl_gx_gdsc"; regulator-name = "gx_clkctl_gx_gdsc";
parent-supply = <&VDD_GFX_GFX_MXC_VOTER_LEVEL>; parent-supply = <&VDD_GFX_GFX_MXC_VOTER_LEVEL>;
qcom,retain-regs; qcom,retain-regs;
@@ -1065,6 +1077,7 @@
video_cc_mvs0_gdsc: qcom,gdsc@aaf8068 { video_cc_mvs0_gdsc: qcom,gdsc@aaf8068 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xaaf8068 0x4>; reg = <0xaaf8068 0x4>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
regulator-name = "video_cc_mvs0_gdsc"; regulator-name = "video_cc_mvs0_gdsc";
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
qcom,retain-regs; qcom,retain-regs;
@@ -1075,6 +1088,7 @@
video_cc_mvs0c_gdsc: qcom,gdsc@aaf8034 { video_cc_mvs0c_gdsc: qcom,gdsc@aaf8034 {
compatible = "qcom,gdsc"; compatible = "qcom,gdsc";
reg = <0xaaf8034 0x4>; reg = <0xaaf8034 0x4>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
regulator-name = "video_cc_mvs0c_gdsc"; regulator-name = "video_cc_mvs0c_gdsc";
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
qcom,retain-regs; qcom,retain-regs;