diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 032ba826..110a4183 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -868,6 +868,7 @@
 	cam_cc_ipe_0_gdsc: qcom,gdsc@adf017c {
 		compatible = "qcom,gdsc";
 		reg = <0xadf017c 0x4>;
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 		regulator-name = "cam_cc_ipe_0_gdsc";
 		parent-supply = <&cam_cc_titan_top_gdsc>;
 		qcom,retain-regs;
@@ -878,6 +879,7 @@
 	cam_cc_ofe_gdsc: qcom,gdsc@adf00c8 {
 		compatible = "qcom,gdsc";
 		reg = <0xadf00c8 0x4>;
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 		regulator-name = "cam_cc_ofe_gdsc";
 		parent-supply = <&cam_cc_titan_top_gdsc>;
 		qcom,retain-regs;
@@ -888,6 +890,7 @@
 	cam_cc_tfe_0_gdsc: qcom,gdsc@adf1004 {
 		compatible = "qcom,gdsc";
 		reg = <0xadf1004 0x4>;
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 		regulator-name = "cam_cc_tfe_0_gdsc";
 		parent-supply = <&cam_cc_titan_top_gdsc>;
 		qcom,retain-regs;
@@ -897,6 +900,7 @@
 	cam_cc_tfe_1_gdsc: qcom,gdsc@adf1084 {
 		compatible = "qcom,gdsc";
 		reg = <0xadf1084 0x4>;
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 		regulator-name = "cam_cc_tfe_1_gdsc";
 		parent-supply = <&cam_cc_titan_top_gdsc>;
 		qcom,retain-regs;
@@ -906,6 +910,7 @@
 	cam_cc_tfe_2_gdsc: qcom,gdsc@adf10ec {
 		compatible = "qcom,gdsc";
 		reg = <0xadf10ec 0x4>;
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 		regulator-name = "cam_cc_tfe_2_gdsc";
 		parent-supply = <&cam_cc_titan_top_gdsc>;
 		qcom,retain-regs;
@@ -915,6 +920,7 @@
 	cam_cc_titan_top_gdsc: qcom,gdsc@adf134c {
 		compatible = "qcom,gdsc";
 		reg = <0xadf134c 0x4>;
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 		regulator-name = "cam_cc_titan_top_gdsc";
 		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 		qcom,retain-regs;
@@ -925,6 +931,7 @@
 	disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
 		compatible = "qcom,gdsc";
 		reg = <0xaf09000 0x4>;
+		clocks = <&gcc GCC_DISP_AHB_CLK>;
 		regulator-name = "disp_cc_mdss_core_gdsc";
 		parent-supply = <&VDD_MM_LEVEL>;
 		proxy-supply = <&disp_cc_mdss_core_gdsc>;
@@ -937,6 +944,7 @@
 	disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
 		compatible = "qcom,gdsc";
 		reg = <0xaf0b000 0x4>;
+		clocks = <&gcc GCC_DISP_AHB_CLK>;
 		regulator-name = "disp_cc_mdss_core_int2_gdsc";
 		parent-supply = <&VDD_MM_LEVEL>;
 		qcom,retain-regs;
@@ -948,6 +956,7 @@
 	eva_cc_mvs0_gdsc: qcom,gdsc@abf8068 {
 		compatible = "qcom,gdsc";
 		reg = <0xabf8068 0x4>;
+		clocks = <&gcc GCC_EVA_AHB_CLK>;
 		regulator-name = "eva_cc_mvs0_gdsc";
 		parent-supply = <&eva_cc_mvs0c_gdsc>;
 		qcom,retain-regs;
@@ -958,6 +967,7 @@
 	eva_cc_mvs0c_gdsc: qcom,gdsc@abf8034 {
 		compatible = "qcom,gdsc";
 		reg = <0xabf8034 0x4>;
+		clocks = <&gcc GCC_EVA_AHB_CLK>;
 		regulator-name = "eva_cc_mvs0c_gdsc";
 		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 		qcom,retain-regs;
@@ -1044,6 +1054,7 @@
 	gpu_cc_cx_gdsc: qcom,gdsc@3d99080 {
 		compatible = "qcom,gdsc";
 		reg = <0x3d99080 0x4>;
+		clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
 		regulator-name = "gpu_cc_cx_gdsc";
 		parent-supply = <&VDD_CX_LEVEL>;
 		hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
@@ -1055,6 +1066,7 @@
 	gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 {
 		compatible = "qcom,gdsc";
 		reg = <0x3d68024 0x4>;
+		clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
 		regulator-name = "gx_clkctl_gx_gdsc";
 		parent-supply = <&VDD_GFX_GFX_MXC_VOTER_LEVEL>;
 		qcom,retain-regs;
@@ -1065,6 +1077,7 @@
 	video_cc_mvs0_gdsc: qcom,gdsc@aaf8068 {
 		compatible = "qcom,gdsc";
 		reg = <0xaaf8068 0x4>;
+		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
 		regulator-name = "video_cc_mvs0_gdsc";
 		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 		qcom,retain-regs;
@@ -1075,6 +1088,7 @@
 	video_cc_mvs0c_gdsc: qcom,gdsc@aaf8034 {
 		compatible = "qcom,gdsc";
 		reg = <0xaaf8034 0x4>;
+		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
 		regulator-name = "video_cc_mvs0c_gdsc";
 		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 		qcom,retain-regs;